1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11#include <linux/acpi.h> 12#include <linux/bitmap.h> 13#include <linux/gpio/consumer.h> 14#include <linux/gpio/driver.h> 15#include <linux/i2c.h> 16#include <linux/init.h> 17#include <linux/interrupt.h> 18#include <linux/module.h> 19#include <linux/of_platform.h> 20#include <linux/platform_data/pca953x.h> 21#include <linux/regmap.h> 22#include <linux/regulator/consumer.h> 23#include <linux/seq_file.h> 24#include <linux/slab.h> 25 26#include <asm/unaligned.h> 27 28#define PCA953X_INPUT 0x00 29#define PCA953X_OUTPUT 0x01 30#define PCA953X_INVERT 0x02 31#define PCA953X_DIRECTION 0x03 32 33#define REG_ADDR_MASK GENMASK(5, 0) 34#define REG_ADDR_EXT BIT(6) 35#define REG_ADDR_AI BIT(7) 36 37#define PCA957X_IN 0x00 38#define PCA957X_INVRT 0x01 39#define PCA957X_BKEN 0x02 40#define PCA957X_PUPD 0x03 41#define PCA957X_CFG 0x04 42#define PCA957X_OUT 0x05 43#define PCA957X_MSK 0x06 44#define PCA957X_INTS 0x07 45 46#define PCAL953X_OUT_STRENGTH 0x20 47#define PCAL953X_IN_LATCH 0x22 48#define PCAL953X_PULL_EN 0x23 49#define PCAL953X_PULL_SEL 0x24 50#define PCAL953X_INT_MASK 0x25 51#define PCAL953X_INT_STAT 0x26 52#define PCAL953X_OUT_CONF 0x27 53 54#define PCAL6524_INT_EDGE 0x28 55#define PCAL6524_INT_CLR 0x2a 56#define PCAL6524_IN_STATUS 0x2b 57#define PCAL6524_OUT_INDCONF 0x2c 58#define PCAL6524_DEBOUNCE 0x2d 59 60#define PCA_GPIO_MASK GENMASK(7, 0) 61 62#define PCAL_GPIO_MASK GENMASK(4, 0) 63#define PCAL_PINCTRL_MASK GENMASK(6, 5) 64 65#define PCA_INT BIT(8) 66#define PCA_PCAL BIT(9) 67#define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 68#define PCA953X_TYPE BIT(12) 69#define PCA957X_TYPE BIT(13) 70#define PCAL653X_TYPE BIT(14) 71#define PCA_TYPE_MASK GENMASK(15, 12) 72 73#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 74 75static const struct i2c_device_id pca953x_id[] = { 76 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 77 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 78 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 79 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 81 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9536", 4 | PCA953X_TYPE, }, 83 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 84 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 85 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 86 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 87 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 88 { "pca9556", 8 | PCA953X_TYPE, }, 89 { "pca9557", 8 | PCA953X_TYPE, }, 90 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 91 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 92 { "pca9698", 40 | PCA953X_TYPE, }, 93 94 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 95 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 96 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 97 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 98 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 99 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 100 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 101 102 { "max7310", 8 | PCA953X_TYPE, }, 103 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 104 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 105 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 106 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 107 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 108 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 109 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 110 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 111 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, }, 112 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 113 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 114 { "xra1202", 8 | PCA953X_TYPE }, 115 { } 116}; 117MODULE_DEVICE_TABLE(i2c, pca953x_id); 118 119#ifdef CONFIG_GPIO_PCA953X_IRQ 120 121#include <linux/dmi.h> 122 123static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 124 125static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 126 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 127 { } 128}; 129 130static int pca953x_acpi_get_irq(struct device *dev) 131{ 132 int ret; 133 134 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 135 if (ret) 136 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 137 138 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); 139 if (ret < 0) 140 return ret; 141 142 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 143 return ret; 144} 145 146static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 147 { 148 /* 149 * On Intel Galileo Gen 2 board the IRQ pin of one of 150 * the I²C GPIO expanders, which has GpioInt() resource, 151 * is provided as an absolute number instead of being 152 * relative. Since first controller (gpio-sch.c) and 153 * second (gpio-dwapb.c) are at the fixed bases, we may 154 * safely refer to the number in the global space to get 155 * an IRQ out of it. 156 */ 157 .matches = { 158 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 159 }, 160 }, 161 {} 162}; 163#endif 164 165static const struct acpi_device_id pca953x_acpi_ids[] = { 166 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 167 { } 168}; 169MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 170 171#define MAX_BANK 5 172#define BANK_SZ 8 173#define MAX_LINE (MAX_BANK * BANK_SZ) 174 175#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 176 177struct pca953x_reg_config { 178 int direction; 179 int output; 180 int input; 181 int invert; 182}; 183 184static const struct pca953x_reg_config pca953x_regs = { 185 .direction = PCA953X_DIRECTION, 186 .output = PCA953X_OUTPUT, 187 .input = PCA953X_INPUT, 188 .invert = PCA953X_INVERT, 189}; 190 191static const struct pca953x_reg_config pca957x_regs = { 192 .direction = PCA957X_CFG, 193 .output = PCA957X_OUT, 194 .input = PCA957X_IN, 195 .invert = PCA957X_INVRT, 196}; 197 198struct pca953x_chip { 199 unsigned gpio_start; 200 struct mutex i2c_lock; 201 struct regmap *regmap; 202 203#ifdef CONFIG_GPIO_PCA953X_IRQ 204 struct mutex irq_lock; 205 DECLARE_BITMAP(irq_mask, MAX_LINE); 206 DECLARE_BITMAP(irq_stat, MAX_LINE); 207 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 208 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 209#endif 210 atomic_t wakeup_path; 211 212 struct i2c_client *client; 213 struct gpio_chip gpio_chip; 214 const char *const *names; 215 unsigned long driver_data; 216 struct regulator *regulator; 217 218 const struct pca953x_reg_config *regs; 219 220 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 221 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 222 u32 checkbank); 223}; 224 225static int pca953x_bank_shift(struct pca953x_chip *chip) 226{ 227 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 228} 229 230#define PCA953x_BANK_INPUT BIT(0) 231#define PCA953x_BANK_OUTPUT BIT(1) 232#define PCA953x_BANK_POLARITY BIT(2) 233#define PCA953x_BANK_CONFIG BIT(3) 234 235#define PCA957x_BANK_INPUT BIT(0) 236#define PCA957x_BANK_POLARITY BIT(1) 237#define PCA957x_BANK_BUSHOLD BIT(2) 238#define PCA957x_BANK_CONFIG BIT(4) 239#define PCA957x_BANK_OUTPUT BIT(5) 240 241#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 242#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 243#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 244#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 245#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 246 247/* 248 * We care about the following registers: 249 * - Standard set, below 0x40, each port can be replicated up to 8 times 250 * - PCA953x standard 251 * Input port 0x00 + 0 * bank_size R 252 * Output port 0x00 + 1 * bank_size RW 253 * Polarity Inversion port 0x00 + 2 * bank_size RW 254 * Configuration port 0x00 + 3 * bank_size RW 255 * - PCA957x with mixed up registers 256 * Input port 0x00 + 0 * bank_size R 257 * Polarity Inversion port 0x00 + 1 * bank_size RW 258 * Bus hold port 0x00 + 2 * bank_size RW 259 * Configuration port 0x00 + 4 * bank_size RW 260 * Output port 0x00 + 5 * bank_size RW 261 * 262 * - Extended set, above 0x40, often chip specific. 263 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 264 * Input latch register 0x40 + 2 * bank_size RW 265 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 266 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 267 * Interrupt mask register 0x40 + 5 * bank_size RW 268 * Interrupt status register 0x40 + 6 * bank_size R 269 * 270 * - Registers with bit 0x80 set, the AI bit 271 * The bit is cleared and the registers fall into one of the 272 * categories above. 273 */ 274 275static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 276 u32 checkbank) 277{ 278 int bank_shift = pca953x_bank_shift(chip); 279 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 280 int offset = reg & (BIT(bank_shift) - 1); 281 282 /* Special PCAL extended register check. */ 283 if (reg & REG_ADDR_EXT) { 284 if (!(chip->driver_data & PCA_PCAL)) 285 return false; 286 bank += 8; 287 } 288 289 /* Register is not in the matching bank. */ 290 if (!(BIT(bank) & checkbank)) 291 return false; 292 293 /* Register is not within allowed range of bank. */ 294 if (offset >= NBANK(chip)) 295 return false; 296 297 return true; 298} 299 300/* 301 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 302 * same register layout as the PCAL6524, the spacing of the registers has been 303 * fundamentally altered by compacting them and thus does not obey the same 304 * rules, including being able to use bit shifting to determine bank. These 305 * chips hence need special handling here. 306 */ 307static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 308 u32 checkbank) 309{ 310 int bank_shift; 311 int bank; 312 int offset; 313 314 if (reg >= 0x54) { 315 /* 316 * Handle lack of reserved registers after output port 317 * configuration register to form a bank. 318 */ 319 reg -= 0x54; 320 bank_shift = 16; 321 } else if (reg >= 0x30) { 322 /* 323 * Reserved block between 14h and 2Fh does not align on 324 * expected bank boundaries like other devices. 325 */ 326 reg -= 0x30; 327 bank_shift = 8; 328 } else { 329 bank_shift = 0; 330 } 331 332 bank = bank_shift + reg / NBANK(chip); 333 offset = reg % NBANK(chip); 334 335 /* Register is not in the matching bank. */ 336 if (!(BIT(bank) & checkbank)) 337 return false; 338 339 /* Register is not within allowed range of bank. */ 340 if (offset >= NBANK(chip)) 341 return false; 342 343 return true; 344} 345 346static bool pca953x_readable_register(struct device *dev, unsigned int reg) 347{ 348 struct pca953x_chip *chip = dev_get_drvdata(dev); 349 u32 bank; 350 351 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 352 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 353 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 354 PCA957x_BANK_BUSHOLD; 355 } else { 356 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 357 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 358 } 359 360 if (chip->driver_data & PCA_PCAL) { 361 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 362 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 363 PCAL9xxx_BANK_IRQ_STAT; 364 } 365 366 return chip->check_reg(chip, reg, bank); 367} 368 369static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 370{ 371 struct pca953x_chip *chip = dev_get_drvdata(dev); 372 u32 bank; 373 374 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 375 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 376 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 377 } else { 378 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 379 PCA953x_BANK_CONFIG; 380 } 381 382 if (chip->driver_data & PCA_PCAL) 383 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 384 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 385 386 return chip->check_reg(chip, reg, bank); 387} 388 389static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 390{ 391 struct pca953x_chip *chip = dev_get_drvdata(dev); 392 u32 bank; 393 394 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 395 bank = PCA957x_BANK_INPUT; 396 else 397 bank = PCA953x_BANK_INPUT; 398 399 if (chip->driver_data & PCA_PCAL) 400 bank |= PCAL9xxx_BANK_IRQ_STAT; 401 402 return chip->check_reg(chip, reg, bank); 403} 404 405static const struct regmap_config pca953x_i2c_regmap = { 406 .reg_bits = 8, 407 .val_bits = 8, 408 409 .use_single_read = true, 410 .use_single_write = true, 411 412 .readable_reg = pca953x_readable_register, 413 .writeable_reg = pca953x_writeable_register, 414 .volatile_reg = pca953x_volatile_register, 415 416 .disable_locking = true, 417 .cache_type = REGCACHE_RBTREE, 418 .max_register = 0x7f, 419}; 420 421static const struct regmap_config pca953x_ai_i2c_regmap = { 422 .reg_bits = 8, 423 .val_bits = 8, 424 425 .read_flag_mask = REG_ADDR_AI, 426 .write_flag_mask = REG_ADDR_AI, 427 428 .readable_reg = pca953x_readable_register, 429 .writeable_reg = pca953x_writeable_register, 430 .volatile_reg = pca953x_volatile_register, 431 432 .disable_locking = true, 433 .cache_type = REGCACHE_RBTREE, 434 .max_register = 0x7f, 435}; 436 437static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 438{ 439 int bank_shift = pca953x_bank_shift(chip); 440 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 441 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 442 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 443 444 return regaddr; 445} 446 447/* 448 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 449 * fit within the bit shifting scheme used for other devices. 450 */ 451static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 452{ 453 int addr; 454 int pinctrl; 455 456 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 457 458 switch (reg) { 459 case PCAL953X_OUT_STRENGTH: 460 case PCAL953X_IN_LATCH: 461 case PCAL953X_PULL_EN: 462 case PCAL953X_PULL_SEL: 463 case PCAL953X_INT_MASK: 464 case PCAL953X_INT_STAT: 465 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 466 break; 467 case PCAL6524_INT_EDGE: 468 case PCAL6524_INT_CLR: 469 case PCAL6524_IN_STATUS: 470 case PCAL6524_OUT_INDCONF: 471 case PCAL6524_DEBOUNCE: 472 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 473 break; 474 default: 475 pinctrl = 0; 476 break; 477 } 478 479 return pinctrl + addr + (off / BANK_SZ); 480} 481 482static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 483{ 484 u8 regaddr = chip->recalc_addr(chip, reg, 0); 485 u8 value[MAX_BANK]; 486 int i, ret; 487 488 for (i = 0; i < NBANK(chip); i++) 489 value[i] = bitmap_get_value8(val, i * BANK_SZ); 490 491 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 492 if (ret < 0) { 493 dev_err(&chip->client->dev, "failed writing register\n"); 494 return ret; 495 } 496 497 return 0; 498} 499 500static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 501{ 502 u8 regaddr = chip->recalc_addr(chip, reg, 0); 503 u8 value[MAX_BANK]; 504 int i, ret; 505 506 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 507 if (ret < 0) { 508 dev_err(&chip->client->dev, "failed reading register\n"); 509 return ret; 510 } 511 512 for (i = 0; i < NBANK(chip); i++) 513 bitmap_set_value8(val, value[i], i * BANK_SZ); 514 515 return 0; 516} 517 518static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 519{ 520 struct pca953x_chip *chip = gpiochip_get_data(gc); 521 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 522 u8 bit = BIT(off % BANK_SZ); 523 int ret; 524 525 mutex_lock(&chip->i2c_lock); 526 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 527 mutex_unlock(&chip->i2c_lock); 528 return ret; 529} 530 531static int pca953x_gpio_direction_output(struct gpio_chip *gc, 532 unsigned off, int val) 533{ 534 struct pca953x_chip *chip = gpiochip_get_data(gc); 535 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 536 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 537 u8 bit = BIT(off % BANK_SZ); 538 int ret; 539 540 mutex_lock(&chip->i2c_lock); 541 /* set output level */ 542 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 543 if (ret) 544 goto exit; 545 546 /* then direction */ 547 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 548exit: 549 mutex_unlock(&chip->i2c_lock); 550 return ret; 551} 552 553static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 554{ 555 struct pca953x_chip *chip = gpiochip_get_data(gc); 556 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 557 u8 bit = BIT(off % BANK_SZ); 558 u32 reg_val; 559 int ret; 560 561 mutex_lock(&chip->i2c_lock); 562 ret = regmap_read(chip->regmap, inreg, ®_val); 563 mutex_unlock(&chip->i2c_lock); 564 if (ret < 0) 565 return ret; 566 567 return !!(reg_val & bit); 568} 569 570static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 571{ 572 struct pca953x_chip *chip = gpiochip_get_data(gc); 573 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 574 u8 bit = BIT(off % BANK_SZ); 575 576 mutex_lock(&chip->i2c_lock); 577 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 578 mutex_unlock(&chip->i2c_lock); 579} 580 581static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 582{ 583 struct pca953x_chip *chip = gpiochip_get_data(gc); 584 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 585 u8 bit = BIT(off % BANK_SZ); 586 u32 reg_val; 587 int ret; 588 589 mutex_lock(&chip->i2c_lock); 590 ret = regmap_read(chip->regmap, dirreg, ®_val); 591 mutex_unlock(&chip->i2c_lock); 592 if (ret < 0) 593 return ret; 594 595 if (reg_val & bit) 596 return GPIO_LINE_DIRECTION_IN; 597 598 return GPIO_LINE_DIRECTION_OUT; 599} 600 601static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 602 unsigned long *mask, unsigned long *bits) 603{ 604 struct pca953x_chip *chip = gpiochip_get_data(gc); 605 DECLARE_BITMAP(reg_val, MAX_LINE); 606 int ret; 607 608 mutex_lock(&chip->i2c_lock); 609 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 610 mutex_unlock(&chip->i2c_lock); 611 if (ret) 612 return ret; 613 614 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 615 return 0; 616} 617 618static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 619 unsigned long *mask, unsigned long *bits) 620{ 621 struct pca953x_chip *chip = gpiochip_get_data(gc); 622 DECLARE_BITMAP(reg_val, MAX_LINE); 623 int ret; 624 625 mutex_lock(&chip->i2c_lock); 626 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 627 if (ret) 628 goto exit; 629 630 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 631 632 pca953x_write_regs(chip, chip->regs->output, reg_val); 633exit: 634 mutex_unlock(&chip->i2c_lock); 635} 636 637static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 638 unsigned int offset, 639 unsigned long config) 640{ 641 enum pin_config_param param = pinconf_to_config_param(config); 642 643 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 644 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 645 u8 bit = BIT(offset % BANK_SZ); 646 int ret; 647 648 /* 649 * pull-up/pull-down configuration requires PCAL extended 650 * registers 651 */ 652 if (!(chip->driver_data & PCA_PCAL)) 653 return -ENOTSUPP; 654 655 mutex_lock(&chip->i2c_lock); 656 657 /* Configure pull-up/pull-down */ 658 if (param == PIN_CONFIG_BIAS_PULL_UP) 659 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 660 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 661 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 662 else 663 ret = 0; 664 if (ret) 665 goto exit; 666 667 /* Disable/Enable pull-up/pull-down */ 668 if (param == PIN_CONFIG_BIAS_DISABLE) 669 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 670 else 671 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 672 673exit: 674 mutex_unlock(&chip->i2c_lock); 675 return ret; 676} 677 678static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 679 unsigned long config) 680{ 681 struct pca953x_chip *chip = gpiochip_get_data(gc); 682 683 switch (pinconf_to_config_param(config)) { 684 case PIN_CONFIG_BIAS_PULL_UP: 685 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 686 case PIN_CONFIG_BIAS_PULL_DOWN: 687 case PIN_CONFIG_BIAS_DISABLE: 688 return pca953x_gpio_set_pull_up_down(chip, offset, config); 689 default: 690 return -ENOTSUPP; 691 } 692} 693 694static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 695{ 696 struct gpio_chip *gc; 697 698 gc = &chip->gpio_chip; 699 700 gc->direction_input = pca953x_gpio_direction_input; 701 gc->direction_output = pca953x_gpio_direction_output; 702 gc->get = pca953x_gpio_get_value; 703 gc->set = pca953x_gpio_set_value; 704 gc->get_direction = pca953x_gpio_get_direction; 705 gc->get_multiple = pca953x_gpio_get_multiple; 706 gc->set_multiple = pca953x_gpio_set_multiple; 707 gc->set_config = pca953x_gpio_set_config; 708 gc->can_sleep = true; 709 710 gc->base = chip->gpio_start; 711 gc->ngpio = gpios; 712 gc->label = dev_name(&chip->client->dev); 713 gc->parent = &chip->client->dev; 714 gc->owner = THIS_MODULE; 715 gc->names = chip->names; 716} 717 718#ifdef CONFIG_GPIO_PCA953X_IRQ 719static void pca953x_irq_mask(struct irq_data *d) 720{ 721 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 722 struct pca953x_chip *chip = gpiochip_get_data(gc); 723 irq_hw_number_t hwirq = irqd_to_hwirq(d); 724 725 clear_bit(hwirq, chip->irq_mask); 726 gpiochip_disable_irq(gc, hwirq); 727} 728 729static void pca953x_irq_unmask(struct irq_data *d) 730{ 731 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 732 struct pca953x_chip *chip = gpiochip_get_data(gc); 733 irq_hw_number_t hwirq = irqd_to_hwirq(d); 734 735 gpiochip_enable_irq(gc, hwirq); 736 set_bit(hwirq, chip->irq_mask); 737} 738 739static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 740{ 741 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 742 struct pca953x_chip *chip = gpiochip_get_data(gc); 743 744 if (on) 745 atomic_inc(&chip->wakeup_path); 746 else 747 atomic_dec(&chip->wakeup_path); 748 749 return irq_set_irq_wake(chip->client->irq, on); 750} 751 752static void pca953x_irq_bus_lock(struct irq_data *d) 753{ 754 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 755 struct pca953x_chip *chip = gpiochip_get_data(gc); 756 757 mutex_lock(&chip->irq_lock); 758} 759 760static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 761{ 762 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 763 struct pca953x_chip *chip = gpiochip_get_data(gc); 764 DECLARE_BITMAP(irq_mask, MAX_LINE); 765 DECLARE_BITMAP(reg_direction, MAX_LINE); 766 int level; 767 768 if (chip->driver_data & PCA_PCAL) { 769 /* Enable latch on interrupt-enabled inputs */ 770 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 771 772 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 773 774 /* Unmask enabled interrupts */ 775 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 776 } 777 778 /* Switch direction to input if needed */ 779 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 780 781 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 782 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 783 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 784 785 /* Look for any newly setup interrupt */ 786 for_each_set_bit(level, irq_mask, gc->ngpio) 787 pca953x_gpio_direction_input(&chip->gpio_chip, level); 788 789 mutex_unlock(&chip->irq_lock); 790} 791 792static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 793{ 794 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 795 struct pca953x_chip *chip = gpiochip_get_data(gc); 796 irq_hw_number_t hwirq = irqd_to_hwirq(d); 797 798 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 799 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 800 d->irq, type); 801 return -EINVAL; 802 } 803 804 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 805 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 806 807 return 0; 808} 809 810static void pca953x_irq_shutdown(struct irq_data *d) 811{ 812 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 813 struct pca953x_chip *chip = gpiochip_get_data(gc); 814 irq_hw_number_t hwirq = irqd_to_hwirq(d); 815 816 clear_bit(hwirq, chip->irq_trig_raise); 817 clear_bit(hwirq, chip->irq_trig_fall); 818} 819 820static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 821{ 822 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 823 824 seq_printf(p, dev_name(gc->parent)); 825} 826 827static const struct irq_chip pca953x_irq_chip = { 828 .irq_mask = pca953x_irq_mask, 829 .irq_unmask = pca953x_irq_unmask, 830 .irq_set_wake = pca953x_irq_set_wake, 831 .irq_bus_lock = pca953x_irq_bus_lock, 832 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 833 .irq_set_type = pca953x_irq_set_type, 834 .irq_shutdown = pca953x_irq_shutdown, 835 .irq_print_chip = pca953x_irq_print_chip, 836 .flags = IRQCHIP_IMMUTABLE, 837 GPIOCHIP_IRQ_RESOURCE_HELPERS, 838}; 839 840static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 841{ 842 struct gpio_chip *gc = &chip->gpio_chip; 843 DECLARE_BITMAP(reg_direction, MAX_LINE); 844 DECLARE_BITMAP(old_stat, MAX_LINE); 845 DECLARE_BITMAP(cur_stat, MAX_LINE); 846 DECLARE_BITMAP(new_stat, MAX_LINE); 847 DECLARE_BITMAP(trigger, MAX_LINE); 848 int ret; 849 850 if (chip->driver_data & PCA_PCAL) { 851 /* Read the current interrupt status from the device */ 852 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 853 if (ret) 854 return false; 855 856 /* Check latched inputs and clear interrupt status */ 857 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 858 if (ret) 859 return false; 860 861 /* Apply filter for rising/falling edge selection */ 862 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio); 863 864 bitmap_and(pending, new_stat, trigger, gc->ngpio); 865 866 return !bitmap_empty(pending, gc->ngpio); 867 } 868 869 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 870 if (ret) 871 return false; 872 873 /* Remove output pins from the equation */ 874 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 875 876 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 877 878 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 879 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 880 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 881 882 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 883 884 if (bitmap_empty(trigger, gc->ngpio)) 885 return false; 886 887 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 888 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 889 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); 890 bitmap_and(pending, new_stat, trigger, gc->ngpio); 891 892 return !bitmap_empty(pending, gc->ngpio); 893} 894 895static irqreturn_t pca953x_irq_handler(int irq, void *devid) 896{ 897 struct pca953x_chip *chip = devid; 898 struct gpio_chip *gc = &chip->gpio_chip; 899 DECLARE_BITMAP(pending, MAX_LINE); 900 int level; 901 bool ret; 902 903 bitmap_zero(pending, MAX_LINE); 904 905 mutex_lock(&chip->i2c_lock); 906 ret = pca953x_irq_pending(chip, pending); 907 mutex_unlock(&chip->i2c_lock); 908 909 if (ret) { 910 ret = 0; 911 912 for_each_set_bit(level, pending, gc->ngpio) { 913 int nested_irq = irq_find_mapping(gc->irq.domain, level); 914 915 if (unlikely(nested_irq <= 0)) { 916 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 917 continue; 918 } 919 920 handle_nested_irq(nested_irq); 921 ret = 1; 922 } 923 } 924 925 return IRQ_RETVAL(ret); 926} 927 928static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 929{ 930 struct i2c_client *client = chip->client; 931 DECLARE_BITMAP(reg_direction, MAX_LINE); 932 DECLARE_BITMAP(irq_stat, MAX_LINE); 933 struct gpio_irq_chip *girq; 934 int ret; 935 936 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 937 ret = pca953x_acpi_get_irq(&client->dev); 938 if (ret > 0) 939 client->irq = ret; 940 } 941 942 if (!client->irq) 943 return 0; 944 945 if (irq_base == -1) 946 return 0; 947 948 if (!(chip->driver_data & PCA_INT)) 949 return 0; 950 951 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 952 if (ret) 953 return ret; 954 955 /* 956 * There is no way to know which GPIO line generated the 957 * interrupt. We have to rely on the previous read for 958 * this purpose. 959 */ 960 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 961 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio); 962 mutex_init(&chip->irq_lock); 963 964 girq = &chip->gpio_chip.irq; 965 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 966 /* This will let us handle the parent IRQ in the driver */ 967 girq->parent_handler = NULL; 968 girq->num_parents = 0; 969 girq->parents = NULL; 970 girq->default_type = IRQ_TYPE_NONE; 971 girq->handler = handle_simple_irq; 972 girq->threaded = true; 973 girq->first = irq_base; /* FIXME: get rid of this */ 974 975 ret = devm_request_threaded_irq(&client->dev, client->irq, 976 NULL, pca953x_irq_handler, 977 IRQF_ONESHOT | IRQF_SHARED, 978 dev_name(&client->dev), chip); 979 if (ret) { 980 dev_err(&client->dev, "failed to request irq %d\n", 981 client->irq); 982 return ret; 983 } 984 985 return 0; 986} 987 988#else /* CONFIG_GPIO_PCA953X_IRQ */ 989static int pca953x_irq_setup(struct pca953x_chip *chip, 990 int irq_base) 991{ 992 struct i2c_client *client = chip->client; 993 994 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 995 dev_warn(&client->dev, "interrupt support not compiled in\n"); 996 997 return 0; 998} 999#endif 1000 1001static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 1002{ 1003 DECLARE_BITMAP(val, MAX_LINE); 1004 u8 regaddr; 1005 int ret; 1006 1007 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1008 ret = regcache_sync_region(chip->regmap, regaddr, 1009 regaddr + NBANK(chip) - 1); 1010 if (ret) 1011 goto out; 1012 1013 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1014 ret = regcache_sync_region(chip->regmap, regaddr, 1015 regaddr + NBANK(chip) - 1); 1016 if (ret) 1017 goto out; 1018 1019 /* set platform specific polarity inversion */ 1020 if (invert) 1021 bitmap_fill(val, MAX_LINE); 1022 else 1023 bitmap_zero(val, MAX_LINE); 1024 1025 ret = pca953x_write_regs(chip, chip->regs->invert, val); 1026out: 1027 return ret; 1028} 1029 1030static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 1031{ 1032 DECLARE_BITMAP(val, MAX_LINE); 1033 unsigned int i; 1034 int ret; 1035 1036 ret = device_pca95xx_init(chip, invert); 1037 if (ret) 1038 goto out; 1039 1040 /* To enable register 6, 7 to control pull up and pull down */ 1041 for (i = 0; i < NBANK(chip); i++) 1042 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1043 1044 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 1045 if (ret) 1046 goto out; 1047 1048 return 0; 1049out: 1050 return ret; 1051} 1052 1053static int pca953x_probe(struct i2c_client *client) 1054{ 1055 struct pca953x_platform_data *pdata; 1056 struct pca953x_chip *chip; 1057 int irq_base = 0; 1058 int ret; 1059 u32 invert = 0; 1060 struct regulator *reg; 1061 const struct regmap_config *regmap_config; 1062 1063 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 1064 if (chip == NULL) 1065 return -ENOMEM; 1066 1067 pdata = dev_get_platdata(&client->dev); 1068 if (pdata) { 1069 irq_base = pdata->irq_base; 1070 chip->gpio_start = pdata->gpio_base; 1071 invert = pdata->invert; 1072 chip->names = pdata->names; 1073 } else { 1074 struct gpio_desc *reset_gpio; 1075 1076 chip->gpio_start = -1; 1077 irq_base = 0; 1078 1079 /* 1080 * See if we need to de-assert a reset pin. 1081 * 1082 * There is no known ACPI-enabled platforms that are 1083 * using "reset" GPIO. Otherwise any of those platform 1084 * must use _DSD method with corresponding property. 1085 */ 1086 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1087 GPIOD_OUT_LOW); 1088 if (IS_ERR(reset_gpio)) 1089 return PTR_ERR(reset_gpio); 1090 } 1091 1092 chip->client = client; 1093 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1094 if (!chip->driver_data) 1095 return -ENODEV; 1096 1097 reg = devm_regulator_get(&client->dev, "vcc"); 1098 if (IS_ERR(reg)) 1099 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n"); 1100 1101 ret = regulator_enable(reg); 1102 if (ret) { 1103 dev_err(&client->dev, "reg en err: %d\n", ret); 1104 return ret; 1105 } 1106 chip->regulator = reg; 1107 1108 i2c_set_clientdata(client, chip); 1109 1110 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1111 1112 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1113 dev_info(&client->dev, "using AI\n"); 1114 regmap_config = &pca953x_ai_i2c_regmap; 1115 } else { 1116 dev_info(&client->dev, "using no AI\n"); 1117 regmap_config = &pca953x_i2c_regmap; 1118 } 1119 1120 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { 1121 chip->recalc_addr = pcal6534_recalc_addr; 1122 chip->check_reg = pcal6534_check_register; 1123 } else { 1124 chip->recalc_addr = pca953x_recalc_addr; 1125 chip->check_reg = pca953x_check_register; 1126 } 1127 1128 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1129 if (IS_ERR(chip->regmap)) { 1130 ret = PTR_ERR(chip->regmap); 1131 goto err_exit; 1132 } 1133 1134 regcache_mark_dirty(chip->regmap); 1135 1136 mutex_init(&chip->i2c_lock); 1137 /* 1138 * In case we have an i2c-mux controlled by a GPIO provided by an 1139 * expander using the same driver higher on the device tree, read the 1140 * i2c adapter nesting depth and use the retrieved value as lockdep 1141 * subclass for chip->i2c_lock. 1142 * 1143 * REVISIT: This solution is not complete. It protects us from lockdep 1144 * false positives when the expander controlling the i2c-mux is on 1145 * a different level on the device tree, but not when it's on the same 1146 * level on a different branch (in which case the subclass number 1147 * would be the same). 1148 * 1149 * TODO: Once a correct solution is developed, a similar fix should be 1150 * applied to all other i2c-controlled GPIO expanders (and potentially 1151 * regmap-i2c). 1152 */ 1153 lockdep_set_subclass(&chip->i2c_lock, 1154 i2c_adapter_depth(client->adapter)); 1155 1156 /* initialize cached registers from their original values. 1157 * we can't share this chip with another i2c master. 1158 */ 1159 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1160 chip->regs = &pca957x_regs; 1161 ret = device_pca957x_init(chip, invert); 1162 } else { 1163 chip->regs = &pca953x_regs; 1164 ret = device_pca95xx_init(chip, invert); 1165 } 1166 if (ret) 1167 goto err_exit; 1168 1169 ret = pca953x_irq_setup(chip, irq_base); 1170 if (ret) 1171 goto err_exit; 1172 1173 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 1174 if (ret) 1175 goto err_exit; 1176 1177 if (pdata && pdata->setup) { 1178 ret = pdata->setup(client, chip->gpio_chip.base, 1179 chip->gpio_chip.ngpio, pdata->context); 1180 if (ret < 0) 1181 dev_warn(&client->dev, "setup failed, %d\n", ret); 1182 } 1183 1184 return 0; 1185 1186err_exit: 1187 regulator_disable(chip->regulator); 1188 return ret; 1189} 1190 1191static void pca953x_remove(struct i2c_client *client) 1192{ 1193 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1194 struct pca953x_chip *chip = i2c_get_clientdata(client); 1195 1196 if (pdata && pdata->teardown) { 1197 pdata->teardown(client, chip->gpio_chip.base, 1198 chip->gpio_chip.ngpio, pdata->context); 1199 } 1200 1201 regulator_disable(chip->regulator); 1202} 1203 1204#ifdef CONFIG_PM_SLEEP 1205static int pca953x_regcache_sync(struct device *dev) 1206{ 1207 struct pca953x_chip *chip = dev_get_drvdata(dev); 1208 int ret; 1209 u8 regaddr; 1210 1211 /* 1212 * The ordering between direction and output is important, 1213 * sync these registers first and only then sync the rest. 1214 */ 1215 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1216 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1217 if (ret) { 1218 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1219 return ret; 1220 } 1221 1222 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1223 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1224 if (ret) { 1225 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1226 return ret; 1227 } 1228 1229#ifdef CONFIG_GPIO_PCA953X_IRQ 1230 if (chip->driver_data & PCA_PCAL) { 1231 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1232 ret = regcache_sync_region(chip->regmap, regaddr, 1233 regaddr + NBANK(chip) - 1); 1234 if (ret) { 1235 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1236 ret); 1237 return ret; 1238 } 1239 1240 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1241 ret = regcache_sync_region(chip->regmap, regaddr, 1242 regaddr + NBANK(chip) - 1); 1243 if (ret) { 1244 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1245 ret); 1246 return ret; 1247 } 1248 } 1249#endif 1250 1251 return 0; 1252} 1253 1254static int pca953x_suspend(struct device *dev) 1255{ 1256 struct pca953x_chip *chip = dev_get_drvdata(dev); 1257 1258 mutex_lock(&chip->i2c_lock); 1259 regcache_cache_only(chip->regmap, true); 1260 mutex_unlock(&chip->i2c_lock); 1261 1262 if (atomic_read(&chip->wakeup_path)) 1263 device_set_wakeup_path(dev); 1264 else 1265 regulator_disable(chip->regulator); 1266 1267 return 0; 1268} 1269 1270static int pca953x_resume(struct device *dev) 1271{ 1272 struct pca953x_chip *chip = dev_get_drvdata(dev); 1273 int ret; 1274 1275 if (!atomic_read(&chip->wakeup_path)) { 1276 ret = regulator_enable(chip->regulator); 1277 if (ret) { 1278 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1279 return 0; 1280 } 1281 } 1282 1283 mutex_lock(&chip->i2c_lock); 1284 regcache_cache_only(chip->regmap, false); 1285 regcache_mark_dirty(chip->regmap); 1286 ret = pca953x_regcache_sync(dev); 1287 if (ret) { 1288 mutex_unlock(&chip->i2c_lock); 1289 return ret; 1290 } 1291 1292 ret = regcache_sync(chip->regmap); 1293 mutex_unlock(&chip->i2c_lock); 1294 if (ret) { 1295 dev_err(dev, "Failed to restore register map: %d\n", ret); 1296 return ret; 1297 } 1298 1299 return 0; 1300} 1301#endif 1302 1303/* convenience to stop overlong match-table lines */ 1304#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1305#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1306#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1307 1308static const struct of_device_id pca953x_dt_ids[] = { 1309 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1310 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1311 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1312 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1313 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1314 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1315 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1316 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1317 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1318 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1319 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1320 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1321 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1322 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1323 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1324 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1325 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1326 1327 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1328 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1329 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1330 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1331 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1332 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1333 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1334 1335 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1336 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1337 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1338 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1339 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1340 1341 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1342 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1343 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1344 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1345 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1346 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1347 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1348 1349 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1350 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1351 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1352 1353 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1354 { } 1355}; 1356 1357MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1358 1359static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1360 1361static struct i2c_driver pca953x_driver = { 1362 .driver = { 1363 .name = "pca953x", 1364 .pm = &pca953x_pm_ops, 1365 .of_match_table = pca953x_dt_ids, 1366 .acpi_match_table = pca953x_acpi_ids, 1367 }, 1368 .probe = pca953x_probe, 1369 .remove = pca953x_remove, 1370 .id_table = pca953x_id, 1371}; 1372 1373static int __init pca953x_init(void) 1374{ 1375 return i2c_add_driver(&pca953x_driver); 1376} 1377/* register after i2c postcore initcall and before 1378 * subsys initcalls that may rely on these GPIOs 1379 */ 1380subsys_initcall(pca953x_init); 1381 1382static void __exit pca953x_exit(void) 1383{ 1384 i2c_del_driver(&pca953x_driver); 1385} 1386module_exit(pca953x_exit); 1387 1388MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1389MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1390MODULE_LICENSE("GPL"); 1391