162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 462306a36Sopenharmony_ci * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#include <linux/err.h> 862306a36Sopenharmony_ci#include <linux/gpio/driver.h> 962306a36Sopenharmony_ci#include <linux/interrupt.h> 1062306a36Sopenharmony_ci#include <linux/io.h> 1162306a36Sopenharmony_ci#include <linux/module.h> 1262306a36Sopenharmony_ci#include <linux/platform_device.h> 1362306a36Sopenharmony_ci#include <linux/spinlock.h> 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#define MTK_BANK_CNT 3 1662306a36Sopenharmony_ci#define MTK_BANK_WIDTH 32 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci#define GPIO_BANK_STRIDE 0x04 1962306a36Sopenharmony_ci#define GPIO_REG_CTRL 0x00 2062306a36Sopenharmony_ci#define GPIO_REG_POL 0x10 2162306a36Sopenharmony_ci#define GPIO_REG_DATA 0x20 2262306a36Sopenharmony_ci#define GPIO_REG_DSET 0x30 2362306a36Sopenharmony_ci#define GPIO_REG_DCLR 0x40 2462306a36Sopenharmony_ci#define GPIO_REG_REDGE 0x50 2562306a36Sopenharmony_ci#define GPIO_REG_FEDGE 0x60 2662306a36Sopenharmony_ci#define GPIO_REG_HLVL 0x70 2762306a36Sopenharmony_ci#define GPIO_REG_LLVL 0x80 2862306a36Sopenharmony_ci#define GPIO_REG_STAT 0x90 2962306a36Sopenharmony_ci#define GPIO_REG_EDGE 0xA0 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_cistruct mtk_gc { 3262306a36Sopenharmony_ci struct irq_chip irq_chip; 3362306a36Sopenharmony_ci struct gpio_chip chip; 3462306a36Sopenharmony_ci spinlock_t lock; 3562306a36Sopenharmony_ci int bank; 3662306a36Sopenharmony_ci u32 rising; 3762306a36Sopenharmony_ci u32 falling; 3862306a36Sopenharmony_ci u32 hlevel; 3962306a36Sopenharmony_ci u32 llevel; 4062306a36Sopenharmony_ci}; 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci/** 4362306a36Sopenharmony_ci * struct mtk - state container for 4462306a36Sopenharmony_ci * data of the platform driver. It is 3 4562306a36Sopenharmony_ci * separate gpio-chip each one with its 4662306a36Sopenharmony_ci * own irq_chip. 4762306a36Sopenharmony_ci * @dev: device instance 4862306a36Sopenharmony_ci * @base: memory base address 4962306a36Sopenharmony_ci * @gpio_irq: irq number from the device tree 5062306a36Sopenharmony_ci * @gc_map: array of the gpio chips 5162306a36Sopenharmony_ci */ 5262306a36Sopenharmony_cistruct mtk { 5362306a36Sopenharmony_ci struct device *dev; 5462306a36Sopenharmony_ci void __iomem *base; 5562306a36Sopenharmony_ci int gpio_irq; 5662306a36Sopenharmony_ci struct mtk_gc gc_map[MTK_BANK_CNT]; 5762306a36Sopenharmony_ci}; 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_cistatic inline struct mtk_gc * 6062306a36Sopenharmony_cito_mediatek_gpio(struct gpio_chip *chip) 6162306a36Sopenharmony_ci{ 6262306a36Sopenharmony_ci return container_of(chip, struct mtk_gc, chip); 6362306a36Sopenharmony_ci} 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_cistatic inline void 6662306a36Sopenharmony_cimtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) 6762306a36Sopenharmony_ci{ 6862306a36Sopenharmony_ci struct gpio_chip *gc = &rg->chip; 6962306a36Sopenharmony_ci struct mtk *mtk = gpiochip_get_data(gc); 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ci offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 7262306a36Sopenharmony_ci gc->write_reg(mtk->base + offset, val); 7362306a36Sopenharmony_ci} 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_cistatic inline u32 7662306a36Sopenharmony_cimtk_gpio_r32(struct mtk_gc *rg, u32 offset) 7762306a36Sopenharmony_ci{ 7862306a36Sopenharmony_ci struct gpio_chip *gc = &rg->chip; 7962306a36Sopenharmony_ci struct mtk *mtk = gpiochip_get_data(gc); 8062306a36Sopenharmony_ci 8162306a36Sopenharmony_ci offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 8262306a36Sopenharmony_ci return gc->read_reg(mtk->base + offset); 8362306a36Sopenharmony_ci} 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_cistatic irqreturn_t 8662306a36Sopenharmony_cimediatek_gpio_irq_handler(int irq, void *data) 8762306a36Sopenharmony_ci{ 8862306a36Sopenharmony_ci struct gpio_chip *gc = data; 8962306a36Sopenharmony_ci struct mtk_gc *rg = to_mediatek_gpio(gc); 9062306a36Sopenharmony_ci irqreturn_t ret = IRQ_NONE; 9162306a36Sopenharmony_ci unsigned long pending; 9262306a36Sopenharmony_ci int bit; 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ci pending = mtk_gpio_r32(rg, GPIO_REG_STAT); 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ci for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { 9762306a36Sopenharmony_ci generic_handle_domain_irq(gc->irq.domain, bit); 9862306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); 9962306a36Sopenharmony_ci ret |= IRQ_HANDLED; 10062306a36Sopenharmony_ci } 10162306a36Sopenharmony_ci 10262306a36Sopenharmony_ci return ret; 10362306a36Sopenharmony_ci} 10462306a36Sopenharmony_ci 10562306a36Sopenharmony_cistatic void 10662306a36Sopenharmony_cimediatek_gpio_irq_unmask(struct irq_data *d) 10762306a36Sopenharmony_ci{ 10862306a36Sopenharmony_ci struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 10962306a36Sopenharmony_ci struct mtk_gc *rg = to_mediatek_gpio(gc); 11062306a36Sopenharmony_ci int pin = d->hwirq; 11162306a36Sopenharmony_ci unsigned long flags; 11262306a36Sopenharmony_ci u32 rise, fall, high, low; 11362306a36Sopenharmony_ci 11462306a36Sopenharmony_ci gpiochip_enable_irq(gc, d->hwirq); 11562306a36Sopenharmony_ci 11662306a36Sopenharmony_ci spin_lock_irqsave(&rg->lock, flags); 11762306a36Sopenharmony_ci rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 11862306a36Sopenharmony_ci fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 11962306a36Sopenharmony_ci high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 12062306a36Sopenharmony_ci low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 12162306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); 12262306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); 12362306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); 12462306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); 12562306a36Sopenharmony_ci spin_unlock_irqrestore(&rg->lock, flags); 12662306a36Sopenharmony_ci} 12762306a36Sopenharmony_ci 12862306a36Sopenharmony_cistatic void 12962306a36Sopenharmony_cimediatek_gpio_irq_mask(struct irq_data *d) 13062306a36Sopenharmony_ci{ 13162306a36Sopenharmony_ci struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13262306a36Sopenharmony_ci struct mtk_gc *rg = to_mediatek_gpio(gc); 13362306a36Sopenharmony_ci int pin = d->hwirq; 13462306a36Sopenharmony_ci unsigned long flags; 13562306a36Sopenharmony_ci u32 rise, fall, high, low; 13662306a36Sopenharmony_ci 13762306a36Sopenharmony_ci spin_lock_irqsave(&rg->lock, flags); 13862306a36Sopenharmony_ci rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 13962306a36Sopenharmony_ci fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 14062306a36Sopenharmony_ci high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 14162306a36Sopenharmony_ci low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 14262306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); 14362306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); 14462306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); 14562306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); 14662306a36Sopenharmony_ci spin_unlock_irqrestore(&rg->lock, flags); 14762306a36Sopenharmony_ci 14862306a36Sopenharmony_ci gpiochip_disable_irq(gc, d->hwirq); 14962306a36Sopenharmony_ci} 15062306a36Sopenharmony_ci 15162306a36Sopenharmony_cistatic int 15262306a36Sopenharmony_cimediatek_gpio_irq_type(struct irq_data *d, unsigned int type) 15362306a36Sopenharmony_ci{ 15462306a36Sopenharmony_ci struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 15562306a36Sopenharmony_ci struct mtk_gc *rg = to_mediatek_gpio(gc); 15662306a36Sopenharmony_ci int pin = d->hwirq; 15762306a36Sopenharmony_ci u32 mask = BIT(pin); 15862306a36Sopenharmony_ci 15962306a36Sopenharmony_ci if (type == IRQ_TYPE_PROBE) { 16062306a36Sopenharmony_ci if ((rg->rising | rg->falling | 16162306a36Sopenharmony_ci rg->hlevel | rg->llevel) & mask) 16262306a36Sopenharmony_ci return 0; 16362306a36Sopenharmony_ci 16462306a36Sopenharmony_ci type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 16562306a36Sopenharmony_ci } 16662306a36Sopenharmony_ci 16762306a36Sopenharmony_ci rg->rising &= ~mask; 16862306a36Sopenharmony_ci rg->falling &= ~mask; 16962306a36Sopenharmony_ci rg->hlevel &= ~mask; 17062306a36Sopenharmony_ci rg->llevel &= ~mask; 17162306a36Sopenharmony_ci 17262306a36Sopenharmony_ci switch (type & IRQ_TYPE_SENSE_MASK) { 17362306a36Sopenharmony_ci case IRQ_TYPE_EDGE_BOTH: 17462306a36Sopenharmony_ci rg->rising |= mask; 17562306a36Sopenharmony_ci rg->falling |= mask; 17662306a36Sopenharmony_ci break; 17762306a36Sopenharmony_ci case IRQ_TYPE_EDGE_RISING: 17862306a36Sopenharmony_ci rg->rising |= mask; 17962306a36Sopenharmony_ci break; 18062306a36Sopenharmony_ci case IRQ_TYPE_EDGE_FALLING: 18162306a36Sopenharmony_ci rg->falling |= mask; 18262306a36Sopenharmony_ci break; 18362306a36Sopenharmony_ci case IRQ_TYPE_LEVEL_HIGH: 18462306a36Sopenharmony_ci rg->hlevel |= mask; 18562306a36Sopenharmony_ci break; 18662306a36Sopenharmony_ci case IRQ_TYPE_LEVEL_LOW: 18762306a36Sopenharmony_ci rg->llevel |= mask; 18862306a36Sopenharmony_ci break; 18962306a36Sopenharmony_ci } 19062306a36Sopenharmony_ci 19162306a36Sopenharmony_ci return 0; 19262306a36Sopenharmony_ci} 19362306a36Sopenharmony_ci 19462306a36Sopenharmony_cistatic int 19562306a36Sopenharmony_cimediatek_gpio_xlate(struct gpio_chip *chip, 19662306a36Sopenharmony_ci const struct of_phandle_args *spec, u32 *flags) 19762306a36Sopenharmony_ci{ 19862306a36Sopenharmony_ci int gpio = spec->args[0]; 19962306a36Sopenharmony_ci struct mtk_gc *rg = to_mediatek_gpio(chip); 20062306a36Sopenharmony_ci 20162306a36Sopenharmony_ci if (rg->bank != gpio / MTK_BANK_WIDTH) 20262306a36Sopenharmony_ci return -EINVAL; 20362306a36Sopenharmony_ci 20462306a36Sopenharmony_ci if (flags) 20562306a36Sopenharmony_ci *flags = spec->args[1]; 20662306a36Sopenharmony_ci 20762306a36Sopenharmony_ci return gpio % MTK_BANK_WIDTH; 20862306a36Sopenharmony_ci} 20962306a36Sopenharmony_ci 21062306a36Sopenharmony_cistatic const struct irq_chip mt7621_irq_chip = { 21162306a36Sopenharmony_ci .name = "mt7621-gpio", 21262306a36Sopenharmony_ci .irq_mask_ack = mediatek_gpio_irq_mask, 21362306a36Sopenharmony_ci .irq_mask = mediatek_gpio_irq_mask, 21462306a36Sopenharmony_ci .irq_unmask = mediatek_gpio_irq_unmask, 21562306a36Sopenharmony_ci .irq_set_type = mediatek_gpio_irq_type, 21662306a36Sopenharmony_ci .flags = IRQCHIP_IMMUTABLE, 21762306a36Sopenharmony_ci GPIOCHIP_IRQ_RESOURCE_HELPERS, 21862306a36Sopenharmony_ci}; 21962306a36Sopenharmony_ci 22062306a36Sopenharmony_cistatic int 22162306a36Sopenharmony_cimediatek_gpio_bank_probe(struct device *dev, int bank) 22262306a36Sopenharmony_ci{ 22362306a36Sopenharmony_ci struct mtk *mtk = dev_get_drvdata(dev); 22462306a36Sopenharmony_ci struct mtk_gc *rg; 22562306a36Sopenharmony_ci void __iomem *dat, *set, *ctrl, *diro; 22662306a36Sopenharmony_ci int ret; 22762306a36Sopenharmony_ci 22862306a36Sopenharmony_ci rg = &mtk->gc_map[bank]; 22962306a36Sopenharmony_ci memset(rg, 0, sizeof(*rg)); 23062306a36Sopenharmony_ci 23162306a36Sopenharmony_ci spin_lock_init(&rg->lock); 23262306a36Sopenharmony_ci rg->bank = bank; 23362306a36Sopenharmony_ci 23462306a36Sopenharmony_ci dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); 23562306a36Sopenharmony_ci set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); 23662306a36Sopenharmony_ci ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); 23762306a36Sopenharmony_ci diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); 23862306a36Sopenharmony_ci 23962306a36Sopenharmony_ci ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, 24062306a36Sopenharmony_ci BGPIOF_NO_SET_ON_INPUT); 24162306a36Sopenharmony_ci if (ret) { 24262306a36Sopenharmony_ci dev_err(dev, "bgpio_init() failed\n"); 24362306a36Sopenharmony_ci return ret; 24462306a36Sopenharmony_ci } 24562306a36Sopenharmony_ci 24662306a36Sopenharmony_ci rg->chip.of_gpio_n_cells = 2; 24762306a36Sopenharmony_ci rg->chip.of_xlate = mediatek_gpio_xlate; 24862306a36Sopenharmony_ci rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", 24962306a36Sopenharmony_ci dev_name(dev), bank); 25062306a36Sopenharmony_ci if (!rg->chip.label) 25162306a36Sopenharmony_ci return -ENOMEM; 25262306a36Sopenharmony_ci 25362306a36Sopenharmony_ci rg->chip.offset = bank * MTK_BANK_WIDTH; 25462306a36Sopenharmony_ci 25562306a36Sopenharmony_ci if (mtk->gpio_irq) { 25662306a36Sopenharmony_ci struct gpio_irq_chip *girq; 25762306a36Sopenharmony_ci 25862306a36Sopenharmony_ci /* 25962306a36Sopenharmony_ci * Directly request the irq here instead of passing 26062306a36Sopenharmony_ci * a flow-handler because the irq is shared. 26162306a36Sopenharmony_ci */ 26262306a36Sopenharmony_ci ret = devm_request_irq(dev, mtk->gpio_irq, 26362306a36Sopenharmony_ci mediatek_gpio_irq_handler, IRQF_SHARED, 26462306a36Sopenharmony_ci rg->chip.label, &rg->chip); 26562306a36Sopenharmony_ci 26662306a36Sopenharmony_ci if (ret) { 26762306a36Sopenharmony_ci dev_err(dev, "Error requesting IRQ %d: %d\n", 26862306a36Sopenharmony_ci mtk->gpio_irq, ret); 26962306a36Sopenharmony_ci return ret; 27062306a36Sopenharmony_ci } 27162306a36Sopenharmony_ci 27262306a36Sopenharmony_ci girq = &rg->chip.irq; 27362306a36Sopenharmony_ci gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); 27462306a36Sopenharmony_ci /* This will let us handle the parent IRQ in the driver */ 27562306a36Sopenharmony_ci girq->parent_handler = NULL; 27662306a36Sopenharmony_ci girq->num_parents = 0; 27762306a36Sopenharmony_ci girq->parents = NULL; 27862306a36Sopenharmony_ci girq->default_type = IRQ_TYPE_NONE; 27962306a36Sopenharmony_ci girq->handler = handle_simple_irq; 28062306a36Sopenharmony_ci } 28162306a36Sopenharmony_ci 28262306a36Sopenharmony_ci ret = devm_gpiochip_add_data(dev, &rg->chip, mtk); 28362306a36Sopenharmony_ci if (ret < 0) { 28462306a36Sopenharmony_ci dev_err(dev, "Could not register gpio %d, ret=%d\n", 28562306a36Sopenharmony_ci rg->chip.ngpio, ret); 28662306a36Sopenharmony_ci return ret; 28762306a36Sopenharmony_ci } 28862306a36Sopenharmony_ci 28962306a36Sopenharmony_ci /* set polarity to low for all gpios */ 29062306a36Sopenharmony_ci mtk_gpio_w32(rg, GPIO_REG_POL, 0); 29162306a36Sopenharmony_ci 29262306a36Sopenharmony_ci dev_info(dev, "registering %d gpios\n", rg->chip.ngpio); 29362306a36Sopenharmony_ci 29462306a36Sopenharmony_ci return 0; 29562306a36Sopenharmony_ci} 29662306a36Sopenharmony_ci 29762306a36Sopenharmony_cistatic int 29862306a36Sopenharmony_cimediatek_gpio_probe(struct platform_device *pdev) 29962306a36Sopenharmony_ci{ 30062306a36Sopenharmony_ci struct device *dev = &pdev->dev; 30162306a36Sopenharmony_ci struct mtk *mtk; 30262306a36Sopenharmony_ci int i; 30362306a36Sopenharmony_ci int ret; 30462306a36Sopenharmony_ci 30562306a36Sopenharmony_ci mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 30662306a36Sopenharmony_ci if (!mtk) 30762306a36Sopenharmony_ci return -ENOMEM; 30862306a36Sopenharmony_ci 30962306a36Sopenharmony_ci mtk->base = devm_platform_ioremap_resource(pdev, 0); 31062306a36Sopenharmony_ci if (IS_ERR(mtk->base)) 31162306a36Sopenharmony_ci return PTR_ERR(mtk->base); 31262306a36Sopenharmony_ci 31362306a36Sopenharmony_ci mtk->gpio_irq = platform_get_irq(pdev, 0); 31462306a36Sopenharmony_ci if (mtk->gpio_irq < 0) 31562306a36Sopenharmony_ci return mtk->gpio_irq; 31662306a36Sopenharmony_ci 31762306a36Sopenharmony_ci mtk->dev = dev; 31862306a36Sopenharmony_ci platform_set_drvdata(pdev, mtk); 31962306a36Sopenharmony_ci 32062306a36Sopenharmony_ci for (i = 0; i < MTK_BANK_CNT; i++) { 32162306a36Sopenharmony_ci ret = mediatek_gpio_bank_probe(dev, i); 32262306a36Sopenharmony_ci if (ret) 32362306a36Sopenharmony_ci return ret; 32462306a36Sopenharmony_ci } 32562306a36Sopenharmony_ci 32662306a36Sopenharmony_ci return 0; 32762306a36Sopenharmony_ci} 32862306a36Sopenharmony_ci 32962306a36Sopenharmony_cistatic const struct of_device_id mediatek_gpio_match[] = { 33062306a36Sopenharmony_ci { .compatible = "mediatek,mt7621-gpio" }, 33162306a36Sopenharmony_ci {}, 33262306a36Sopenharmony_ci}; 33362306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, mediatek_gpio_match); 33462306a36Sopenharmony_ci 33562306a36Sopenharmony_cistatic struct platform_driver mediatek_gpio_driver = { 33662306a36Sopenharmony_ci .probe = mediatek_gpio_probe, 33762306a36Sopenharmony_ci .driver = { 33862306a36Sopenharmony_ci .name = "mt7621_gpio", 33962306a36Sopenharmony_ci .of_match_table = mediatek_gpio_match, 34062306a36Sopenharmony_ci }, 34162306a36Sopenharmony_ci}; 34262306a36Sopenharmony_ci 34362306a36Sopenharmony_cibuiltin_platform_driver(mediatek_gpio_driver); 344