1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7#include <linux/bitops.h> 8#include <linux/gpio/driver.h> 9#include <linux/interrupt.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/platform_device.h> 14#include <linux/spinlock.h> 15 16/* EIC registers definition */ 17#define SPRD_EIC_DBNC_DATA 0x0 18#define SPRD_EIC_DBNC_DMSK 0x4 19#define SPRD_EIC_DBNC_IEV 0x14 20#define SPRD_EIC_DBNC_IE 0x18 21#define SPRD_EIC_DBNC_RIS 0x1c 22#define SPRD_EIC_DBNC_MIS 0x20 23#define SPRD_EIC_DBNC_IC 0x24 24#define SPRD_EIC_DBNC_TRIG 0x28 25#define SPRD_EIC_DBNC_CTRL0 0x40 26 27#define SPRD_EIC_LATCH_INTEN 0x0 28#define SPRD_EIC_LATCH_INTRAW 0x4 29#define SPRD_EIC_LATCH_INTMSK 0x8 30#define SPRD_EIC_LATCH_INTCLR 0xc 31#define SPRD_EIC_LATCH_INTPOL 0x10 32#define SPRD_EIC_LATCH_INTMODE 0x14 33 34#define SPRD_EIC_ASYNC_INTIE 0x0 35#define SPRD_EIC_ASYNC_INTRAW 0x4 36#define SPRD_EIC_ASYNC_INTMSK 0x8 37#define SPRD_EIC_ASYNC_INTCLR 0xc 38#define SPRD_EIC_ASYNC_INTMODE 0x10 39#define SPRD_EIC_ASYNC_INTBOTH 0x14 40#define SPRD_EIC_ASYNC_INTPOL 0x18 41#define SPRD_EIC_ASYNC_DATA 0x1c 42 43#define SPRD_EIC_SYNC_INTIE 0x0 44#define SPRD_EIC_SYNC_INTRAW 0x4 45#define SPRD_EIC_SYNC_INTMSK 0x8 46#define SPRD_EIC_SYNC_INTCLR 0xc 47#define SPRD_EIC_SYNC_INTMODE 0x10 48#define SPRD_EIC_SYNC_INTBOTH 0x14 49#define SPRD_EIC_SYNC_INTPOL 0x18 50#define SPRD_EIC_SYNC_DATA 0x1c 51 52/* 53 * The digital-chip EIC controller can support maximum 3 banks, and each bank 54 * contains 8 EICs. 55 */ 56#define SPRD_EIC_MAX_BANK 3 57#define SPRD_EIC_PER_BANK_NR 8 58#define SPRD_EIC_DATA_MASK GENMASK(7, 0) 59#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1)) 60#define SPRD_EIC_DBNC_MASK GENMASK(11, 0) 61 62/* 63 * The Spreadtrum EIC (external interrupt controller) can be used only in 64 * input mode to generate interrupts if detecting input signals. 65 * 66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules: 67 * debounce EIC, latch EIC, async EIC and sync EIC, 68 * 69 * The debounce EIC is used to capture the input signals' stable status 70 * (millisecond resolution) and a single-trigger mechanism is introduced 71 * into this sub-module to enhance the input event detection reliability. 72 * The debounce range is from 1ms to 4s with a step size of 1ms. 73 * 74 * The latch EIC is used to latch some special power down signals and 75 * generate interrupts, since the latch EIC does not depend on the APB clock 76 * to capture signals. 77 * 78 * The async EIC uses a 32k clock to capture the short signals (microsecond 79 * resolution) to generate interrupts by level or edge trigger. 80 * 81 * The EIC-sync is similar with GPIO's input function, which is a synchronized 82 * signal input register. 83 */ 84enum sprd_eic_type { 85 SPRD_EIC_DEBOUNCE, 86 SPRD_EIC_LATCH, 87 SPRD_EIC_ASYNC, 88 SPRD_EIC_SYNC, 89 SPRD_EIC_MAX, 90}; 91 92struct sprd_eic { 93 struct gpio_chip chip; 94 void __iomem *base[SPRD_EIC_MAX_BANK]; 95 enum sprd_eic_type type; 96 spinlock_t lock; 97 int irq; 98}; 99 100struct sprd_eic_variant_data { 101 enum sprd_eic_type type; 102 u32 num_eics; 103}; 104 105static const char *sprd_eic_label_name[SPRD_EIC_MAX] = { 106 "eic-debounce", "eic-latch", "eic-async", 107 "eic-sync", 108}; 109 110static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = { 111 .type = SPRD_EIC_DEBOUNCE, 112 .num_eics = 8, 113}; 114 115static const struct sprd_eic_variant_data sc9860_eic_latch_data = { 116 .type = SPRD_EIC_LATCH, 117 .num_eics = 8, 118}; 119 120static const struct sprd_eic_variant_data sc9860_eic_async_data = { 121 .type = SPRD_EIC_ASYNC, 122 .num_eics = 8, 123}; 124 125static const struct sprd_eic_variant_data sc9860_eic_sync_data = { 126 .type = SPRD_EIC_SYNC, 127 .num_eics = 8, 128}; 129 130static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic, 131 unsigned int bank) 132{ 133 if (bank >= SPRD_EIC_MAX_BANK) 134 return NULL; 135 136 return sprd_eic->base[bank]; 137} 138 139static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, 140 u16 reg, unsigned int val) 141{ 142 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 143 void __iomem *base = 144 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 145 unsigned long flags; 146 u32 tmp; 147 148 spin_lock_irqsave(&sprd_eic->lock, flags); 149 tmp = readl_relaxed(base + reg); 150 151 if (val) 152 tmp |= BIT(SPRD_EIC_BIT(offset)); 153 else 154 tmp &= ~BIT(SPRD_EIC_BIT(offset)); 155 156 writel_relaxed(tmp, base + reg); 157 spin_unlock_irqrestore(&sprd_eic->lock, flags); 158} 159 160static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) 161{ 162 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 163 void __iomem *base = 164 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 165 166 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); 167} 168 169static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) 170{ 171 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); 172 return 0; 173} 174 175static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) 176{ 177 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); 178} 179 180static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) 181{ 182 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 183 184 switch (sprd_eic->type) { 185 case SPRD_EIC_DEBOUNCE: 186 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); 187 case SPRD_EIC_ASYNC: 188 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); 189 case SPRD_EIC_SYNC: 190 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); 191 default: 192 return -ENOTSUPP; 193 } 194} 195 196static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) 197{ 198 /* EICs are always input, nothing need to do here. */ 199 return 0; 200} 201 202static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) 203{ 204 /* EICs are always input, nothing need to do here. */ 205} 206 207static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, 208 unsigned int debounce) 209{ 210 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 211 void __iomem *base = 212 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 213 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; 214 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; 215 216 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK; 217 writel_relaxed(value, base + reg); 218 219 return 0; 220} 221 222static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, 223 unsigned long config) 224{ 225 unsigned long param = pinconf_to_config_param(config); 226 u32 arg = pinconf_to_config_argument(config); 227 228 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 229 return sprd_eic_set_debounce(chip, offset, arg); 230 231 return -ENOTSUPP; 232} 233 234static void sprd_eic_irq_mask(struct irq_data *data) 235{ 236 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 237 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 238 u32 offset = irqd_to_hwirq(data); 239 240 switch (sprd_eic->type) { 241 case SPRD_EIC_DEBOUNCE: 242 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); 243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); 244 break; 245 case SPRD_EIC_LATCH: 246 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); 247 break; 248 case SPRD_EIC_ASYNC: 249 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); 250 break; 251 case SPRD_EIC_SYNC: 252 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); 253 break; 254 default: 255 dev_err(chip->parent, "Unsupported EIC type.\n"); 256 } 257 258 gpiochip_disable_irq(chip, offset); 259} 260 261static void sprd_eic_irq_unmask(struct irq_data *data) 262{ 263 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 264 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 265 u32 offset = irqd_to_hwirq(data); 266 267 gpiochip_enable_irq(chip, offset); 268 269 switch (sprd_eic->type) { 270 case SPRD_EIC_DEBOUNCE: 271 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); 272 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); 273 break; 274 case SPRD_EIC_LATCH: 275 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); 276 break; 277 case SPRD_EIC_ASYNC: 278 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); 279 break; 280 case SPRD_EIC_SYNC: 281 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); 282 break; 283 default: 284 dev_err(chip->parent, "Unsupported EIC type.\n"); 285 } 286} 287 288static void sprd_eic_irq_ack(struct irq_data *data) 289{ 290 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 291 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 292 u32 offset = irqd_to_hwirq(data); 293 294 switch (sprd_eic->type) { 295 case SPRD_EIC_DEBOUNCE: 296 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 297 break; 298 case SPRD_EIC_LATCH: 299 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 300 break; 301 case SPRD_EIC_ASYNC: 302 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 303 break; 304 case SPRD_EIC_SYNC: 305 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 306 break; 307 default: 308 dev_err(chip->parent, "Unsupported EIC type.\n"); 309 } 310} 311 312static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) 313{ 314 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 315 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 316 u32 offset = irqd_to_hwirq(data); 317 int state; 318 319 switch (sprd_eic->type) { 320 case SPRD_EIC_DEBOUNCE: 321 switch (flow_type) { 322 case IRQ_TYPE_LEVEL_HIGH: 323 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 324 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 325 break; 326 case IRQ_TYPE_LEVEL_LOW: 327 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 328 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 329 break; 330 case IRQ_TYPE_EDGE_RISING: 331 case IRQ_TYPE_EDGE_FALLING: 332 case IRQ_TYPE_EDGE_BOTH: 333 state = sprd_eic_get(chip, offset); 334 if (state) { 335 sprd_eic_update(chip, offset, 336 SPRD_EIC_DBNC_IEV, 0); 337 sprd_eic_update(chip, offset, 338 SPRD_EIC_DBNC_IC, 1); 339 } else { 340 sprd_eic_update(chip, offset, 341 SPRD_EIC_DBNC_IEV, 1); 342 sprd_eic_update(chip, offset, 343 SPRD_EIC_DBNC_IC, 1); 344 } 345 break; 346 default: 347 return -ENOTSUPP; 348 } 349 350 irq_set_handler_locked(data, handle_level_irq); 351 break; 352 case SPRD_EIC_LATCH: 353 switch (flow_type) { 354 case IRQ_TYPE_LEVEL_HIGH: 355 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 356 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 357 break; 358 case IRQ_TYPE_LEVEL_LOW: 359 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 360 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 361 break; 362 case IRQ_TYPE_EDGE_RISING: 363 case IRQ_TYPE_EDGE_FALLING: 364 case IRQ_TYPE_EDGE_BOTH: 365 state = sprd_eic_get(chip, offset); 366 if (state) { 367 sprd_eic_update(chip, offset, 368 SPRD_EIC_LATCH_INTPOL, 0); 369 sprd_eic_update(chip, offset, 370 SPRD_EIC_LATCH_INTCLR, 1); 371 } else { 372 sprd_eic_update(chip, offset, 373 SPRD_EIC_LATCH_INTPOL, 1); 374 sprd_eic_update(chip, offset, 375 SPRD_EIC_LATCH_INTCLR, 1); 376 } 377 break; 378 default: 379 return -ENOTSUPP; 380 } 381 382 irq_set_handler_locked(data, handle_level_irq); 383 break; 384 case SPRD_EIC_ASYNC: 385 switch (flow_type) { 386 case IRQ_TYPE_EDGE_RISING: 387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 388 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 389 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 390 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 391 irq_set_handler_locked(data, handle_edge_irq); 392 break; 393 case IRQ_TYPE_EDGE_FALLING: 394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 396 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 397 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 398 irq_set_handler_locked(data, handle_edge_irq); 399 break; 400 case IRQ_TYPE_EDGE_BOTH: 401 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 402 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); 403 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 404 irq_set_handler_locked(data, handle_edge_irq); 405 break; 406 case IRQ_TYPE_LEVEL_HIGH: 407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 408 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 409 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 410 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 411 irq_set_handler_locked(data, handle_level_irq); 412 break; 413 case IRQ_TYPE_LEVEL_LOW: 414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 415 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 416 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 417 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 418 irq_set_handler_locked(data, handle_level_irq); 419 break; 420 default: 421 return -ENOTSUPP; 422 } 423 break; 424 case SPRD_EIC_SYNC: 425 switch (flow_type) { 426 case IRQ_TYPE_EDGE_RISING: 427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 428 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 429 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 430 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 431 irq_set_handler_locked(data, handle_edge_irq); 432 break; 433 case IRQ_TYPE_EDGE_FALLING: 434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 435 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 436 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 437 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 438 irq_set_handler_locked(data, handle_edge_irq); 439 break; 440 case IRQ_TYPE_EDGE_BOTH: 441 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 442 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); 443 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 444 irq_set_handler_locked(data, handle_edge_irq); 445 break; 446 case IRQ_TYPE_LEVEL_HIGH: 447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 448 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 449 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 450 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 451 irq_set_handler_locked(data, handle_level_irq); 452 break; 453 case IRQ_TYPE_LEVEL_LOW: 454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 455 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 456 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 457 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 458 irq_set_handler_locked(data, handle_level_irq); 459 break; 460 default: 461 return -ENOTSUPP; 462 } 463 break; 464 default: 465 dev_err(chip->parent, "Unsupported EIC type.\n"); 466 return -ENOTSUPP; 467 } 468 469 return 0; 470} 471 472static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq, 473 unsigned int offset) 474{ 475 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 476 struct irq_data *data = irq_get_irq_data(irq); 477 u32 trigger = irqd_get_trigger_type(data); 478 int state, post_state; 479 480 /* 481 * The debounce EIC and latch EIC can only support level trigger, so we 482 * can toggle the level trigger to emulate the edge trigger. 483 */ 484 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE && 485 sprd_eic->type != SPRD_EIC_LATCH) || 486 !(trigger & IRQ_TYPE_EDGE_BOTH)) 487 return; 488 489 sprd_eic_irq_mask(data); 490 state = sprd_eic_get(chip, offset); 491 492retry: 493 switch (sprd_eic->type) { 494 case SPRD_EIC_DEBOUNCE: 495 if (state) 496 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 497 else 498 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 499 break; 500 case SPRD_EIC_LATCH: 501 if (state) 502 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 503 else 504 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 505 break; 506 default: 507 sprd_eic_irq_unmask(data); 508 return; 509 } 510 511 post_state = sprd_eic_get(chip, offset); 512 if (state != post_state) { 513 dev_warn(chip->parent, "EIC level was changed.\n"); 514 state = post_state; 515 goto retry; 516 } 517 518 sprd_eic_irq_unmask(data); 519} 520 521static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data) 522{ 523 enum sprd_eic_type type = *(enum sprd_eic_type *)data; 524 525 return !strcmp(chip->label, sprd_eic_label_name[type]); 526} 527 528static void sprd_eic_handle_one_type(struct gpio_chip *chip) 529{ 530 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 531 u32 bank, n, girq; 532 533 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) { 534 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); 535 unsigned long reg; 536 537 switch (sprd_eic->type) { 538 case SPRD_EIC_DEBOUNCE: 539 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & 540 SPRD_EIC_DATA_MASK; 541 break; 542 case SPRD_EIC_LATCH: 543 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & 544 SPRD_EIC_DATA_MASK; 545 break; 546 case SPRD_EIC_ASYNC: 547 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & 548 SPRD_EIC_DATA_MASK; 549 break; 550 case SPRD_EIC_SYNC: 551 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & 552 SPRD_EIC_DATA_MASK; 553 break; 554 default: 555 dev_err(chip->parent, "Unsupported EIC type.\n"); 556 return; 557 } 558 559 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { 560 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; 561 562 girq = irq_find_mapping(chip->irq.domain, offset); 563 564 generic_handle_irq(girq); 565 sprd_eic_toggle_trigger(chip, girq, offset); 566 } 567 } 568} 569 570static void sprd_eic_irq_handler(struct irq_desc *desc) 571{ 572 struct irq_chip *ic = irq_desc_get_chip(desc); 573 struct gpio_chip *chip; 574 enum sprd_eic_type type; 575 576 chained_irq_enter(ic, desc); 577 578 /* 579 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async 580 * and sync) share one same interrupt line, we should iterate each 581 * EIC module to check if there are EIC interrupts were triggered. 582 */ 583 for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) { 584 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type); 585 if (!chip) 586 continue; 587 588 sprd_eic_handle_one_type(chip); 589 } 590 591 chained_irq_exit(ic, desc); 592} 593 594static const struct irq_chip sprd_eic_irq = { 595 .name = "sprd-eic", 596 .irq_ack = sprd_eic_irq_ack, 597 .irq_mask = sprd_eic_irq_mask, 598 .irq_unmask = sprd_eic_irq_unmask, 599 .irq_set_type = sprd_eic_irq_set_type, 600 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 601 GPIOCHIP_IRQ_RESOURCE_HELPERS, 602}; 603static int sprd_eic_probe(struct platform_device *pdev) 604{ 605 const struct sprd_eic_variant_data *pdata; 606 struct gpio_irq_chip *irq; 607 struct sprd_eic *sprd_eic; 608 struct resource *res; 609 int ret, i; 610 611 pdata = of_device_get_match_data(&pdev->dev); 612 if (!pdata) { 613 dev_err(&pdev->dev, "No matching driver data found.\n"); 614 return -EINVAL; 615 } 616 617 sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL); 618 if (!sprd_eic) 619 return -ENOMEM; 620 621 spin_lock_init(&sprd_eic->lock); 622 sprd_eic->type = pdata->type; 623 624 sprd_eic->irq = platform_get_irq(pdev, 0); 625 if (sprd_eic->irq < 0) 626 return sprd_eic->irq; 627 628 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) { 629 /* 630 * We can have maximum 3 banks EICs, and each EIC has 631 * its own base address. But some platform maybe only 632 * have one bank EIC, thus base[1] and base[2] can be 633 * optional. 634 */ 635 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 636 if (!res) 637 break; 638 639 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res); 640 if (IS_ERR(sprd_eic->base[i])) 641 return PTR_ERR(sprd_eic->base[i]); 642 } 643 644 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type]; 645 sprd_eic->chip.ngpio = pdata->num_eics; 646 sprd_eic->chip.base = -1; 647 sprd_eic->chip.parent = &pdev->dev; 648 sprd_eic->chip.direction_input = sprd_eic_direction_input; 649 switch (sprd_eic->type) { 650 case SPRD_EIC_DEBOUNCE: 651 sprd_eic->chip.request = sprd_eic_request; 652 sprd_eic->chip.free = sprd_eic_free; 653 sprd_eic->chip.set_config = sprd_eic_set_config; 654 sprd_eic->chip.set = sprd_eic_set; 655 fallthrough; 656 case SPRD_EIC_ASYNC: 657 case SPRD_EIC_SYNC: 658 sprd_eic->chip.get = sprd_eic_get; 659 break; 660 case SPRD_EIC_LATCH: 661 default: 662 break; 663 } 664 665 irq = &sprd_eic->chip.irq; 666 gpio_irq_chip_set_chip(irq, &sprd_eic_irq); 667 irq->handler = handle_bad_irq; 668 irq->default_type = IRQ_TYPE_NONE; 669 irq->parent_handler = sprd_eic_irq_handler; 670 irq->parent_handler_data = sprd_eic; 671 irq->num_parents = 1; 672 irq->parents = &sprd_eic->irq; 673 674 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic); 675 if (ret < 0) { 676 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret); 677 return ret; 678 } 679 680 return 0; 681} 682 683static const struct of_device_id sprd_eic_of_match[] = { 684 { 685 .compatible = "sprd,sc9860-eic-debounce", 686 .data = &sc9860_eic_dbnc_data, 687 }, 688 { 689 .compatible = "sprd,sc9860-eic-latch", 690 .data = &sc9860_eic_latch_data, 691 }, 692 { 693 .compatible = "sprd,sc9860-eic-async", 694 .data = &sc9860_eic_async_data, 695 }, 696 { 697 .compatible = "sprd,sc9860-eic-sync", 698 .data = &sc9860_eic_sync_data, 699 }, 700 { 701 /* end of list */ 702 } 703}; 704MODULE_DEVICE_TABLE(of, sprd_eic_of_match); 705 706static struct platform_driver sprd_eic_driver = { 707 .probe = sprd_eic_probe, 708 .driver = { 709 .name = "sprd-eic", 710 .of_match_table = sprd_eic_of_match, 711 }, 712}; 713 714module_platform_driver(sprd_eic_driver); 715 716MODULE_DESCRIPTION("Spreadtrum EIC driver"); 717MODULE_LICENSE("GPL v2"); 718