162306a36Sopenharmony_ci# 262306a36Sopenharmony_ci# EDAC Kconfig 362306a36Sopenharmony_ci# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 462306a36Sopenharmony_ci# Licensed and distributed under the GPL 562306a36Sopenharmony_ci 662306a36Sopenharmony_ciconfig EDAC_ATOMIC_SCRUB 762306a36Sopenharmony_ci bool 862306a36Sopenharmony_ci 962306a36Sopenharmony_ciconfig EDAC_SUPPORT 1062306a36Sopenharmony_ci bool 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cimenuconfig EDAC 1362306a36Sopenharmony_ci tristate "EDAC (Error Detection And Correction) reporting" 1462306a36Sopenharmony_ci depends on HAS_IOMEM && EDAC_SUPPORT && RAS 1562306a36Sopenharmony_ci help 1662306a36Sopenharmony_ci EDAC is a subsystem along with hardware-specific drivers designed to 1762306a36Sopenharmony_ci report hardware errors. These are low-level errors that are reported 1862306a36Sopenharmony_ci in the CPU or supporting chipset or other subsystems: 1962306a36Sopenharmony_ci memory errors, cache errors, PCI errors, thermal throttling, etc.. 2062306a36Sopenharmony_ci If unsure, select 'Y'. 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci The mailing list for the EDAC project is linux-edac@vger.kernel.org. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciif EDAC 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciconfig EDAC_LEGACY_SYSFS 2762306a36Sopenharmony_ci bool "EDAC legacy sysfs" 2862306a36Sopenharmony_ci default y 2962306a36Sopenharmony_ci help 3062306a36Sopenharmony_ci Enable the compatibility sysfs nodes. 3162306a36Sopenharmony_ci Use 'Y' if your edac utilities aren't ported to work with the newer 3262306a36Sopenharmony_ci structures. 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ciconfig EDAC_DEBUG 3562306a36Sopenharmony_ci bool "Debugging" 3662306a36Sopenharmony_ci select DEBUG_FS 3762306a36Sopenharmony_ci help 3862306a36Sopenharmony_ci This turns on debugging information for the entire EDAC subsystem. 3962306a36Sopenharmony_ci You do so by inserting edac_module with "edac_debug_level=x." Valid 4062306a36Sopenharmony_ci levels are 0-4 (from low to high) and by default it is set to 2. 4162306a36Sopenharmony_ci Usually you should select 'N' here. 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ciconfig EDAC_DECODE_MCE 4462306a36Sopenharmony_ci tristate "Decode MCEs in human-readable form (only on AMD for now)" 4562306a36Sopenharmony_ci depends on CPU_SUP_AMD && X86_MCE_AMD 4662306a36Sopenharmony_ci default y 4762306a36Sopenharmony_ci help 4862306a36Sopenharmony_ci Enable this option if you want to decode Machine Check Exceptions 4962306a36Sopenharmony_ci occurring on your machine in human-readable form. 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci You should definitely say Y here in case you want to decode MCEs 5262306a36Sopenharmony_ci which occur really early upon boot, before the module infrastructure 5362306a36Sopenharmony_ci has been initialized. 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciconfig EDAC_GHES 5662306a36Sopenharmony_ci tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC" 5762306a36Sopenharmony_ci depends on ACPI_APEI_GHES 5862306a36Sopenharmony_ci select UEFI_CPER 5962306a36Sopenharmony_ci help 6062306a36Sopenharmony_ci Not all machines support hardware-driven error report. Some of those 6162306a36Sopenharmony_ci provide a BIOS-driven error report mechanism via ACPI, using the 6262306a36Sopenharmony_ci APEI/GHES driver. By enabling this option, the error reports provided 6362306a36Sopenharmony_ci by GHES are sent to userspace via the EDAC API. 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ci When this option is enabled, it will disable the hardware-driven 6662306a36Sopenharmony_ci mechanisms, if a GHES BIOS is detected, entering into the 6762306a36Sopenharmony_ci "Firmware First" mode. 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ci It should be noticed that keeping both GHES and a hardware-driven 7062306a36Sopenharmony_ci error mechanism won't work well, as BIOS will race with OS, while 7162306a36Sopenharmony_ci reading the error registers. So, if you want to not use "Firmware 7262306a36Sopenharmony_ci first" GHES error mechanism, you should disable GHES either at 7362306a36Sopenharmony_ci compilation time or by passing "ghes.disable=1" Kernel parameter 7462306a36Sopenharmony_ci at boot time. 7562306a36Sopenharmony_ci 7662306a36Sopenharmony_ci In doubt, say 'Y'. 7762306a36Sopenharmony_ci 7862306a36Sopenharmony_ciconfig EDAC_AMD64 7962306a36Sopenharmony_ci tristate "AMD64 (Opteron, Athlon64)" 8062306a36Sopenharmony_ci depends on AMD_NB && EDAC_DECODE_MCE 8162306a36Sopenharmony_ci help 8262306a36Sopenharmony_ci Support for error detection and correction of DRAM ECC errors on 8362306a36Sopenharmony_ci the AMD64 families (>= K8) of memory controllers. 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci When EDAC_DEBUG is enabled, hardware error injection facilities 8662306a36Sopenharmony_ci through sysfs are available: 8762306a36Sopenharmony_ci 8862306a36Sopenharmony_ci AMD CPUs up to and excluding family 0x17 provide for Memory 8962306a36Sopenharmony_ci Error Injection into the ECC detection circuits. The amd64_edac 9062306a36Sopenharmony_ci module allows the operator/user to inject Uncorrectable and 9162306a36Sopenharmony_ci Correctable errors into DRAM. 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci When enabled, in each of the respective memory controller directories 9462306a36Sopenharmony_ci (/sys/devices/system/edac/mc/mcX), there are 3 input files: 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ci - inject_section (0..3, 16-byte section of 64-byte cacheline), 9762306a36Sopenharmony_ci - inject_word (0..8, 16-bit word of 16-byte section), 9862306a36Sopenharmony_ci - inject_ecc_vector (hex ecc vector: select bits of inject word) 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci In addition, there are two control files, inject_read and inject_write, 10162306a36Sopenharmony_ci which trigger the DRAM ECC Read and Write respectively. 10262306a36Sopenharmony_ci 10362306a36Sopenharmony_ciconfig EDAC_AL_MC 10462306a36Sopenharmony_ci tristate "Amazon's Annapurna Lab Memory Controller" 10562306a36Sopenharmony_ci depends on (ARCH_ALPINE || COMPILE_TEST) 10662306a36Sopenharmony_ci help 10762306a36Sopenharmony_ci Support for error detection and correction for Amazon's Annapurna 10862306a36Sopenharmony_ci Labs Alpine chips which allow 1 bit correction and 2 bits detection. 10962306a36Sopenharmony_ci 11062306a36Sopenharmony_ciconfig EDAC_AMD76X 11162306a36Sopenharmony_ci tristate "AMD 76x (760, 762, 768)" 11262306a36Sopenharmony_ci depends on PCI && X86_32 11362306a36Sopenharmony_ci help 11462306a36Sopenharmony_ci Support for error detection and correction on the AMD 76x 11562306a36Sopenharmony_ci series of chipsets used with the Athlon processor. 11662306a36Sopenharmony_ci 11762306a36Sopenharmony_ciconfig EDAC_E7XXX 11862306a36Sopenharmony_ci tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 11962306a36Sopenharmony_ci depends on PCI && X86_32 12062306a36Sopenharmony_ci help 12162306a36Sopenharmony_ci Support for error detection and correction on the Intel 12262306a36Sopenharmony_ci E7205, E7500, E7501 and E7505 server chipsets. 12362306a36Sopenharmony_ci 12462306a36Sopenharmony_ciconfig EDAC_E752X 12562306a36Sopenharmony_ci tristate "Intel e752x (e7520, e7525, e7320) and 3100" 12662306a36Sopenharmony_ci depends on PCI && X86 12762306a36Sopenharmony_ci help 12862306a36Sopenharmony_ci Support for error detection and correction on the Intel 12962306a36Sopenharmony_ci E7520, E7525, E7320 server chipsets. 13062306a36Sopenharmony_ci 13162306a36Sopenharmony_ciconfig EDAC_I82443BXGX 13262306a36Sopenharmony_ci tristate "Intel 82443BX/GX (440BX/GX)" 13362306a36Sopenharmony_ci depends on PCI && X86_32 13462306a36Sopenharmony_ci depends on BROKEN 13562306a36Sopenharmony_ci help 13662306a36Sopenharmony_ci Support for error detection and correction on the Intel 13762306a36Sopenharmony_ci 82443BX/GX memory controllers (440BX/GX chipsets). 13862306a36Sopenharmony_ci 13962306a36Sopenharmony_ciconfig EDAC_I82875P 14062306a36Sopenharmony_ci tristate "Intel 82875p (D82875P, E7210)" 14162306a36Sopenharmony_ci depends on PCI && X86_32 14262306a36Sopenharmony_ci help 14362306a36Sopenharmony_ci Support for error detection and correction on the Intel 14462306a36Sopenharmony_ci DP82785P and E7210 server chipsets. 14562306a36Sopenharmony_ci 14662306a36Sopenharmony_ciconfig EDAC_I82975X 14762306a36Sopenharmony_ci tristate "Intel 82975x (D82975x)" 14862306a36Sopenharmony_ci depends on PCI && X86 14962306a36Sopenharmony_ci help 15062306a36Sopenharmony_ci Support for error detection and correction on the Intel 15162306a36Sopenharmony_ci DP82975x server chipsets. 15262306a36Sopenharmony_ci 15362306a36Sopenharmony_ciconfig EDAC_I3000 15462306a36Sopenharmony_ci tristate "Intel 3000/3010" 15562306a36Sopenharmony_ci depends on PCI && X86 15662306a36Sopenharmony_ci help 15762306a36Sopenharmony_ci Support for error detection and correction on the Intel 15862306a36Sopenharmony_ci 3000 and 3010 server chipsets. 15962306a36Sopenharmony_ci 16062306a36Sopenharmony_ciconfig EDAC_I3200 16162306a36Sopenharmony_ci tristate "Intel 3200" 16262306a36Sopenharmony_ci depends on PCI && X86 16362306a36Sopenharmony_ci help 16462306a36Sopenharmony_ci Support for error detection and correction on the Intel 16562306a36Sopenharmony_ci 3200 and 3210 server chipsets. 16662306a36Sopenharmony_ci 16762306a36Sopenharmony_ciconfig EDAC_IE31200 16862306a36Sopenharmony_ci tristate "Intel e312xx" 16962306a36Sopenharmony_ci depends on PCI && X86 17062306a36Sopenharmony_ci help 17162306a36Sopenharmony_ci Support for error detection and correction on the Intel 17262306a36Sopenharmony_ci E3-1200 based DRAM controllers. 17362306a36Sopenharmony_ci 17462306a36Sopenharmony_ciconfig EDAC_X38 17562306a36Sopenharmony_ci tristate "Intel X38" 17662306a36Sopenharmony_ci depends on PCI && X86 17762306a36Sopenharmony_ci help 17862306a36Sopenharmony_ci Support for error detection and correction on the Intel 17962306a36Sopenharmony_ci X38 server chipsets. 18062306a36Sopenharmony_ci 18162306a36Sopenharmony_ciconfig EDAC_I5400 18262306a36Sopenharmony_ci tristate "Intel 5400 (Seaburg) chipsets" 18362306a36Sopenharmony_ci depends on PCI && X86 18462306a36Sopenharmony_ci help 18562306a36Sopenharmony_ci Support for error detection and correction the Intel 18662306a36Sopenharmony_ci i5400 MCH chipset (Seaburg). 18762306a36Sopenharmony_ci 18862306a36Sopenharmony_ciconfig EDAC_I7CORE 18962306a36Sopenharmony_ci tristate "Intel i7 Core (Nehalem) processors" 19062306a36Sopenharmony_ci depends on PCI && X86 && X86_MCE_INTEL 19162306a36Sopenharmony_ci help 19262306a36Sopenharmony_ci Support for error detection and correction the Intel 19362306a36Sopenharmony_ci i7 Core (Nehalem) Integrated Memory Controller that exists on 19462306a36Sopenharmony_ci newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 19562306a36Sopenharmony_ci and Xeon 55xx processors. 19662306a36Sopenharmony_ci 19762306a36Sopenharmony_ciconfig EDAC_I82860 19862306a36Sopenharmony_ci tristate "Intel 82860" 19962306a36Sopenharmony_ci depends on PCI && X86_32 20062306a36Sopenharmony_ci help 20162306a36Sopenharmony_ci Support for error detection and correction on the Intel 20262306a36Sopenharmony_ci 82860 chipset. 20362306a36Sopenharmony_ci 20462306a36Sopenharmony_ciconfig EDAC_R82600 20562306a36Sopenharmony_ci tristate "Radisys 82600 embedded chipset" 20662306a36Sopenharmony_ci depends on PCI && X86_32 20762306a36Sopenharmony_ci help 20862306a36Sopenharmony_ci Support for error detection and correction on the Radisys 20962306a36Sopenharmony_ci 82600 embedded chipset. 21062306a36Sopenharmony_ci 21162306a36Sopenharmony_ciconfig EDAC_I5000 21262306a36Sopenharmony_ci tristate "Intel Greencreek/Blackford chipset" 21362306a36Sopenharmony_ci depends on X86 && PCI 21462306a36Sopenharmony_ci depends on BROKEN 21562306a36Sopenharmony_ci help 21662306a36Sopenharmony_ci Support for error detection and correction the Intel 21762306a36Sopenharmony_ci Greekcreek/Blackford chipsets. 21862306a36Sopenharmony_ci 21962306a36Sopenharmony_ciconfig EDAC_I5100 22062306a36Sopenharmony_ci tristate "Intel San Clemente MCH" 22162306a36Sopenharmony_ci depends on X86 && PCI 22262306a36Sopenharmony_ci help 22362306a36Sopenharmony_ci Support for error detection and correction the Intel 22462306a36Sopenharmony_ci San Clemente MCH. 22562306a36Sopenharmony_ci 22662306a36Sopenharmony_ciconfig EDAC_I7300 22762306a36Sopenharmony_ci tristate "Intel Clarksboro MCH" 22862306a36Sopenharmony_ci depends on X86 && PCI 22962306a36Sopenharmony_ci help 23062306a36Sopenharmony_ci Support for error detection and correction the Intel 23162306a36Sopenharmony_ci Clarksboro MCH (Intel 7300 chipset). 23262306a36Sopenharmony_ci 23362306a36Sopenharmony_ciconfig EDAC_SBRIDGE 23462306a36Sopenharmony_ci tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 23562306a36Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 23662306a36Sopenharmony_ci help 23762306a36Sopenharmony_ci Support for error detection and correction the Intel 23862306a36Sopenharmony_ci Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 23962306a36Sopenharmony_ci 24062306a36Sopenharmony_ciconfig EDAC_SKX 24162306a36Sopenharmony_ci tristate "Intel Skylake server Integrated MC" 24262306a36Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 24362306a36Sopenharmony_ci depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 24462306a36Sopenharmony_ci select DMI 24562306a36Sopenharmony_ci select ACPI_ADXL 24662306a36Sopenharmony_ci help 24762306a36Sopenharmony_ci Support for error detection and correction the Intel 24862306a36Sopenharmony_ci Skylake server Integrated Memory Controllers. If your 24962306a36Sopenharmony_ci system has non-volatile DIMMs you should also manually 25062306a36Sopenharmony_ci select CONFIG_ACPI_NFIT. 25162306a36Sopenharmony_ci 25262306a36Sopenharmony_ciconfig EDAC_I10NM 25362306a36Sopenharmony_ci tristate "Intel 10nm server Integrated MC" 25462306a36Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 25562306a36Sopenharmony_ci depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 25662306a36Sopenharmony_ci select DMI 25762306a36Sopenharmony_ci select ACPI_ADXL 25862306a36Sopenharmony_ci help 25962306a36Sopenharmony_ci Support for error detection and correction the Intel 26062306a36Sopenharmony_ci 10nm server Integrated Memory Controllers. If your 26162306a36Sopenharmony_ci system has non-volatile DIMMs you should also manually 26262306a36Sopenharmony_ci select CONFIG_ACPI_NFIT. 26362306a36Sopenharmony_ci 26462306a36Sopenharmony_ciconfig EDAC_PND2 26562306a36Sopenharmony_ci tristate "Intel Pondicherry2" 26662306a36Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL 26762306a36Sopenharmony_ci select P2SB if X86 26862306a36Sopenharmony_ci help 26962306a36Sopenharmony_ci Support for error detection and correction on the Intel 27062306a36Sopenharmony_ci Pondicherry2 Integrated Memory Controller. This SoC IP is 27162306a36Sopenharmony_ci first used on the Apollo Lake platform and Denverton 27262306a36Sopenharmony_ci micro-server but may appear on others in the future. 27362306a36Sopenharmony_ci 27462306a36Sopenharmony_ciconfig EDAC_IGEN6 27562306a36Sopenharmony_ci tristate "Intel client SoC Integrated MC" 27662306a36Sopenharmony_ci depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 27762306a36Sopenharmony_ci depends on X86_64 && X86_MCE_INTEL 27862306a36Sopenharmony_ci help 27962306a36Sopenharmony_ci Support for error detection and correction on the Intel 28062306a36Sopenharmony_ci client SoC Integrated Memory Controller using In-Band ECC IP. 28162306a36Sopenharmony_ci This In-Band ECC is first used on the Elkhart Lake SoC but 28262306a36Sopenharmony_ci may appear on others in the future. 28362306a36Sopenharmony_ci 28462306a36Sopenharmony_ciconfig EDAC_MPC85XX 28562306a36Sopenharmony_ci bool "Freescale MPC83xx / MPC85xx" 28662306a36Sopenharmony_ci depends on FSL_SOC && EDAC=y 28762306a36Sopenharmony_ci help 28862306a36Sopenharmony_ci Support for error detection and correction on the Freescale 28962306a36Sopenharmony_ci MPC8349, MPC8560, MPC8540, MPC8548, T4240 29062306a36Sopenharmony_ci 29162306a36Sopenharmony_ciconfig EDAC_LAYERSCAPE 29262306a36Sopenharmony_ci tristate "Freescale Layerscape DDR" 29362306a36Sopenharmony_ci depends on ARCH_LAYERSCAPE || SOC_LS1021A 29462306a36Sopenharmony_ci help 29562306a36Sopenharmony_ci Support for error detection and correction on Freescale memory 29662306a36Sopenharmony_ci controllers on Layerscape SoCs. 29762306a36Sopenharmony_ci 29862306a36Sopenharmony_ciconfig EDAC_PASEMI 29962306a36Sopenharmony_ci tristate "PA Semi PWRficient" 30062306a36Sopenharmony_ci depends on PPC_PASEMI && PCI 30162306a36Sopenharmony_ci help 30262306a36Sopenharmony_ci Support for error detection and correction on PA Semi 30362306a36Sopenharmony_ci PWRficient. 30462306a36Sopenharmony_ci 30562306a36Sopenharmony_ciconfig EDAC_CELL 30662306a36Sopenharmony_ci tristate "Cell Broadband Engine memory controller" 30762306a36Sopenharmony_ci depends on PPC_CELL_COMMON 30862306a36Sopenharmony_ci help 30962306a36Sopenharmony_ci Support for error detection and correction on the 31062306a36Sopenharmony_ci Cell Broadband Engine internal memory controller 31162306a36Sopenharmony_ci on platform without a hypervisor 31262306a36Sopenharmony_ci 31362306a36Sopenharmony_ciconfig EDAC_PPC4XX 31462306a36Sopenharmony_ci tristate "PPC4xx IBM DDR2 Memory Controller" 31562306a36Sopenharmony_ci depends on 4xx 31662306a36Sopenharmony_ci help 31762306a36Sopenharmony_ci This enables support for EDAC on the ECC memory used 31862306a36Sopenharmony_ci with the IBM DDR2 memory controller found in various 31962306a36Sopenharmony_ci PowerPC 4xx embedded processors such as the 405EX[r], 32062306a36Sopenharmony_ci 440SP, 440SPe, 460EX, 460GT and 460SX. 32162306a36Sopenharmony_ci 32262306a36Sopenharmony_ciconfig EDAC_AMD8131 32362306a36Sopenharmony_ci tristate "AMD8131 HyperTransport PCI-X Tunnel" 32462306a36Sopenharmony_ci depends on PCI && PPC_MAPLE 32562306a36Sopenharmony_ci help 32662306a36Sopenharmony_ci Support for error detection and correction on the 32762306a36Sopenharmony_ci AMD8131 HyperTransport PCI-X Tunnel chip. 32862306a36Sopenharmony_ci Note, add more Kconfig dependency if it's adopted 32962306a36Sopenharmony_ci on some machine other than Maple. 33062306a36Sopenharmony_ci 33162306a36Sopenharmony_ciconfig EDAC_AMD8111 33262306a36Sopenharmony_ci tristate "AMD8111 HyperTransport I/O Hub" 33362306a36Sopenharmony_ci depends on PCI && PPC_MAPLE 33462306a36Sopenharmony_ci help 33562306a36Sopenharmony_ci Support for error detection and correction on the 33662306a36Sopenharmony_ci AMD8111 HyperTransport I/O Hub chip. 33762306a36Sopenharmony_ci Note, add more Kconfig dependency if it's adopted 33862306a36Sopenharmony_ci on some machine other than Maple. 33962306a36Sopenharmony_ci 34062306a36Sopenharmony_ciconfig EDAC_CPC925 34162306a36Sopenharmony_ci tristate "IBM CPC925 Memory Controller (PPC970FX)" 34262306a36Sopenharmony_ci depends on PPC64 34362306a36Sopenharmony_ci help 34462306a36Sopenharmony_ci Support for error detection and correction on the 34562306a36Sopenharmony_ci IBM CPC925 Bridge and Memory Controller, which is 34662306a36Sopenharmony_ci a companion chip to the PowerPC 970 family of 34762306a36Sopenharmony_ci processors. 34862306a36Sopenharmony_ci 34962306a36Sopenharmony_ciconfig EDAC_HIGHBANK_MC 35062306a36Sopenharmony_ci tristate "Highbank Memory Controller" 35162306a36Sopenharmony_ci depends on ARCH_HIGHBANK 35262306a36Sopenharmony_ci help 35362306a36Sopenharmony_ci Support for error detection and correction on the 35462306a36Sopenharmony_ci Calxeda Highbank memory controller. 35562306a36Sopenharmony_ci 35662306a36Sopenharmony_ciconfig EDAC_HIGHBANK_L2 35762306a36Sopenharmony_ci tristate "Highbank L2 Cache" 35862306a36Sopenharmony_ci depends on ARCH_HIGHBANK 35962306a36Sopenharmony_ci help 36062306a36Sopenharmony_ci Support for error detection and correction on the 36162306a36Sopenharmony_ci Calxeda Highbank memory controller. 36262306a36Sopenharmony_ci 36362306a36Sopenharmony_ciconfig EDAC_OCTEON_PC 36462306a36Sopenharmony_ci tristate "Cavium Octeon Primary Caches" 36562306a36Sopenharmony_ci depends on CPU_CAVIUM_OCTEON 36662306a36Sopenharmony_ci help 36762306a36Sopenharmony_ci Support for error detection and correction on the primary caches of 36862306a36Sopenharmony_ci the cnMIPS cores of Cavium Octeon family SOCs. 36962306a36Sopenharmony_ci 37062306a36Sopenharmony_ciconfig EDAC_OCTEON_L2C 37162306a36Sopenharmony_ci tristate "Cavium Octeon Secondary Caches (L2C)" 37262306a36Sopenharmony_ci depends on CAVIUM_OCTEON_SOC 37362306a36Sopenharmony_ci help 37462306a36Sopenharmony_ci Support for error detection and correction on the 37562306a36Sopenharmony_ci Cavium Octeon family of SOCs. 37662306a36Sopenharmony_ci 37762306a36Sopenharmony_ciconfig EDAC_OCTEON_LMC 37862306a36Sopenharmony_ci tristate "Cavium Octeon DRAM Memory Controller (LMC)" 37962306a36Sopenharmony_ci depends on CAVIUM_OCTEON_SOC 38062306a36Sopenharmony_ci help 38162306a36Sopenharmony_ci Support for error detection and correction on the 38262306a36Sopenharmony_ci Cavium Octeon family of SOCs. 38362306a36Sopenharmony_ci 38462306a36Sopenharmony_ciconfig EDAC_OCTEON_PCI 38562306a36Sopenharmony_ci tristate "Cavium Octeon PCI Controller" 38662306a36Sopenharmony_ci depends on PCI && CAVIUM_OCTEON_SOC 38762306a36Sopenharmony_ci help 38862306a36Sopenharmony_ci Support for error detection and correction on the 38962306a36Sopenharmony_ci Cavium Octeon family of SOCs. 39062306a36Sopenharmony_ci 39162306a36Sopenharmony_ciconfig EDAC_THUNDERX 39262306a36Sopenharmony_ci tristate "Cavium ThunderX EDAC" 39362306a36Sopenharmony_ci depends on ARM64 39462306a36Sopenharmony_ci depends on PCI 39562306a36Sopenharmony_ci help 39662306a36Sopenharmony_ci Support for error detection and correction on the 39762306a36Sopenharmony_ci Cavium ThunderX memory controllers (LMC), Cache 39862306a36Sopenharmony_ci Coherent Processor Interconnect (CCPI) and L2 cache 39962306a36Sopenharmony_ci blocks (TAD, CBC, MCI). 40062306a36Sopenharmony_ci 40162306a36Sopenharmony_ciconfig EDAC_ALTERA 40262306a36Sopenharmony_ci bool "Altera SOCFPGA ECC" 40362306a36Sopenharmony_ci depends on EDAC=y && ARCH_INTEL_SOCFPGA 40462306a36Sopenharmony_ci help 40562306a36Sopenharmony_ci Support for error detection and correction on the 40662306a36Sopenharmony_ci Altera SOCs. This is the global enable for the 40762306a36Sopenharmony_ci various Altera peripherals. 40862306a36Sopenharmony_ci 40962306a36Sopenharmony_ciconfig EDAC_ALTERA_SDRAM 41062306a36Sopenharmony_ci bool "Altera SDRAM ECC" 41162306a36Sopenharmony_ci depends on EDAC_ALTERA=y 41262306a36Sopenharmony_ci help 41362306a36Sopenharmony_ci Support for error detection and correction on the 41462306a36Sopenharmony_ci Altera SDRAM Memory for Altera SoCs. Note that the 41562306a36Sopenharmony_ci preloader must initialize the SDRAM before loading 41662306a36Sopenharmony_ci the kernel. 41762306a36Sopenharmony_ci 41862306a36Sopenharmony_ciconfig EDAC_ALTERA_L2C 41962306a36Sopenharmony_ci bool "Altera L2 Cache ECC" 42062306a36Sopenharmony_ci depends on EDAC_ALTERA=y && CACHE_L2X0 42162306a36Sopenharmony_ci help 42262306a36Sopenharmony_ci Support for error detection and correction on the 42362306a36Sopenharmony_ci Altera L2 cache Memory for Altera SoCs. This option 42462306a36Sopenharmony_ci requires L2 cache. 42562306a36Sopenharmony_ci 42662306a36Sopenharmony_ciconfig EDAC_ALTERA_OCRAM 42762306a36Sopenharmony_ci bool "Altera On-Chip RAM ECC" 42862306a36Sopenharmony_ci depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 42962306a36Sopenharmony_ci help 43062306a36Sopenharmony_ci Support for error detection and correction on the 43162306a36Sopenharmony_ci Altera On-Chip RAM Memory for Altera SoCs. 43262306a36Sopenharmony_ci 43362306a36Sopenharmony_ciconfig EDAC_ALTERA_ETHERNET 43462306a36Sopenharmony_ci bool "Altera Ethernet FIFO ECC" 43562306a36Sopenharmony_ci depends on EDAC_ALTERA=y 43662306a36Sopenharmony_ci help 43762306a36Sopenharmony_ci Support for error detection and correction on the 43862306a36Sopenharmony_ci Altera Ethernet FIFO Memory for Altera SoCs. 43962306a36Sopenharmony_ci 44062306a36Sopenharmony_ciconfig EDAC_ALTERA_NAND 44162306a36Sopenharmony_ci bool "Altera NAND FIFO ECC" 44262306a36Sopenharmony_ci depends on EDAC_ALTERA=y && MTD_NAND_DENALI 44362306a36Sopenharmony_ci help 44462306a36Sopenharmony_ci Support for error detection and correction on the 44562306a36Sopenharmony_ci Altera NAND FIFO Memory for Altera SoCs. 44662306a36Sopenharmony_ci 44762306a36Sopenharmony_ciconfig EDAC_ALTERA_DMA 44862306a36Sopenharmony_ci bool "Altera DMA FIFO ECC" 44962306a36Sopenharmony_ci depends on EDAC_ALTERA=y && PL330_DMA=y 45062306a36Sopenharmony_ci help 45162306a36Sopenharmony_ci Support for error detection and correction on the 45262306a36Sopenharmony_ci Altera DMA FIFO Memory for Altera SoCs. 45362306a36Sopenharmony_ci 45462306a36Sopenharmony_ciconfig EDAC_ALTERA_USB 45562306a36Sopenharmony_ci bool "Altera USB FIFO ECC" 45662306a36Sopenharmony_ci depends on EDAC_ALTERA=y && USB_DWC2 45762306a36Sopenharmony_ci help 45862306a36Sopenharmony_ci Support for error detection and correction on the 45962306a36Sopenharmony_ci Altera USB FIFO Memory for Altera SoCs. 46062306a36Sopenharmony_ci 46162306a36Sopenharmony_ciconfig EDAC_ALTERA_QSPI 46262306a36Sopenharmony_ci bool "Altera QSPI FIFO ECC" 46362306a36Sopenharmony_ci depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 46462306a36Sopenharmony_ci help 46562306a36Sopenharmony_ci Support for error detection and correction on the 46662306a36Sopenharmony_ci Altera QSPI FIFO Memory for Altera SoCs. 46762306a36Sopenharmony_ci 46862306a36Sopenharmony_ciconfig EDAC_ALTERA_SDMMC 46962306a36Sopenharmony_ci bool "Altera SDMMC FIFO ECC" 47062306a36Sopenharmony_ci depends on EDAC_ALTERA=y && MMC_DW 47162306a36Sopenharmony_ci help 47262306a36Sopenharmony_ci Support for error detection and correction on the 47362306a36Sopenharmony_ci Altera SDMMC FIFO Memory for Altera SoCs. 47462306a36Sopenharmony_ci 47562306a36Sopenharmony_ciconfig EDAC_SIFIVE 47662306a36Sopenharmony_ci bool "Sifive platform EDAC driver" 47762306a36Sopenharmony_ci depends on EDAC=y && SIFIVE_CCACHE 47862306a36Sopenharmony_ci help 47962306a36Sopenharmony_ci Support for error detection and correction on the SiFive SoCs. 48062306a36Sopenharmony_ci 48162306a36Sopenharmony_ciconfig EDAC_ARMADA_XP 48262306a36Sopenharmony_ci bool "Marvell Armada XP DDR and L2 Cache ECC" 48362306a36Sopenharmony_ci depends on MACH_MVEBU_V7 48462306a36Sopenharmony_ci help 48562306a36Sopenharmony_ci Support for error correction and detection on the Marvell Aramada XP 48662306a36Sopenharmony_ci DDR RAM and L2 cache controllers. 48762306a36Sopenharmony_ci 48862306a36Sopenharmony_ciconfig EDAC_SYNOPSYS 48962306a36Sopenharmony_ci tristate "Synopsys DDR Memory Controller" 49062306a36Sopenharmony_ci depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 49162306a36Sopenharmony_ci help 49262306a36Sopenharmony_ci Support for error detection and correction on the Synopsys DDR 49362306a36Sopenharmony_ci memory controller. 49462306a36Sopenharmony_ci 49562306a36Sopenharmony_ciconfig EDAC_XGENE 49662306a36Sopenharmony_ci tristate "APM X-Gene SoC" 49762306a36Sopenharmony_ci depends on (ARM64 || COMPILE_TEST) 49862306a36Sopenharmony_ci help 49962306a36Sopenharmony_ci Support for error detection and correction on the 50062306a36Sopenharmony_ci APM X-Gene family of SOCs. 50162306a36Sopenharmony_ci 50262306a36Sopenharmony_ciconfig EDAC_TI 50362306a36Sopenharmony_ci tristate "Texas Instruments DDR3 ECC Controller" 50462306a36Sopenharmony_ci depends on ARCH_KEYSTONE || SOC_DRA7XX 50562306a36Sopenharmony_ci help 50662306a36Sopenharmony_ci Support for error detection and correction on the TI SoCs. 50762306a36Sopenharmony_ci 50862306a36Sopenharmony_ciconfig EDAC_QCOM 50962306a36Sopenharmony_ci tristate "QCOM EDAC Controller" 51062306a36Sopenharmony_ci depends on ARCH_QCOM && QCOM_LLCC 51162306a36Sopenharmony_ci help 51262306a36Sopenharmony_ci Support for error detection and correction on the 51362306a36Sopenharmony_ci Qualcomm Technologies, Inc. SoCs. 51462306a36Sopenharmony_ci 51562306a36Sopenharmony_ci This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 51662306a36Sopenharmony_ci As of now, it supports error reporting for Last Level Cache Controller (LLCC) 51762306a36Sopenharmony_ci of Tag RAM and Data RAM. 51862306a36Sopenharmony_ci 51962306a36Sopenharmony_ci For debugging issues having to do with stability and overall system 52062306a36Sopenharmony_ci health, you should probably say 'Y' here. 52162306a36Sopenharmony_ci 52262306a36Sopenharmony_ciconfig EDAC_ASPEED 52362306a36Sopenharmony_ci tristate "Aspeed AST BMC SoC" 52462306a36Sopenharmony_ci depends on ARCH_ASPEED 52562306a36Sopenharmony_ci help 52662306a36Sopenharmony_ci Support for error detection and correction on the Aspeed AST BMC SoC. 52762306a36Sopenharmony_ci 52862306a36Sopenharmony_ci First, ECC must be configured in the bootloader. Then, this driver 52962306a36Sopenharmony_ci will expose error counters via the EDAC kernel framework. 53062306a36Sopenharmony_ci 53162306a36Sopenharmony_ciconfig EDAC_BLUEFIELD 53262306a36Sopenharmony_ci tristate "Mellanox BlueField Memory ECC" 53362306a36Sopenharmony_ci depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 53462306a36Sopenharmony_ci help 53562306a36Sopenharmony_ci Support for error detection and correction on the 53662306a36Sopenharmony_ci Mellanox BlueField SoCs. 53762306a36Sopenharmony_ci 53862306a36Sopenharmony_ciconfig EDAC_DMC520 53962306a36Sopenharmony_ci tristate "ARM DMC-520 ECC" 54062306a36Sopenharmony_ci depends on ARM64 54162306a36Sopenharmony_ci help 54262306a36Sopenharmony_ci Support for error detection and correction on the 54362306a36Sopenharmony_ci SoCs with ARM DMC-520 DRAM controller. 54462306a36Sopenharmony_ci 54562306a36Sopenharmony_ciconfig EDAC_ZYNQMP 54662306a36Sopenharmony_ci tristate "Xilinx ZynqMP OCM Controller" 54762306a36Sopenharmony_ci depends on ARCH_ZYNQMP || COMPILE_TEST 54862306a36Sopenharmony_ci help 54962306a36Sopenharmony_ci This driver supports error detection and correction for the 55062306a36Sopenharmony_ci Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be 55162306a36Sopenharmony_ci built as a module. In that case it will be called zynqmp_edac. 55262306a36Sopenharmony_ci 55362306a36Sopenharmony_ciconfig EDAC_NPCM 55462306a36Sopenharmony_ci tristate "Nuvoton NPCM DDR Memory Controller" 55562306a36Sopenharmony_ci depends on (ARCH_NPCM || COMPILE_TEST) 55662306a36Sopenharmony_ci help 55762306a36Sopenharmony_ci Support for error detection and correction on the Nuvoton NPCM DDR 55862306a36Sopenharmony_ci memory controller. 55962306a36Sopenharmony_ci 56062306a36Sopenharmony_ci The memory controller supports single bit error correction, double bit 56162306a36Sopenharmony_ci error detection (in-line ECC in which a section 1/8th of the memory 56262306a36Sopenharmony_ci device used to store data is used for ECC storage). 56362306a36Sopenharmony_ci 56462306a36Sopenharmony_ciendif # EDAC 565