1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3#include <linux/init.h> 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/io-64-nonatomic-lo-hi.h> 8#include <linux/dmaengine.h> 9#include <linux/irq.h> 10#include <uapi/linux/idxd.h> 11#include "../dmaengine.h" 12#include "idxd.h" 13#include "registers.h" 14 15static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 16 u32 *status); 17static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 18static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 19 20/* Interrupt control bits */ 21void idxd_unmask_error_interrupts(struct idxd_device *idxd) 22{ 23 union genctrl_reg genctrl; 24 25 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 26 genctrl.softerr_int_en = 1; 27 genctrl.halt_int_en = 1; 28 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 29} 30 31void idxd_mask_error_interrupts(struct idxd_device *idxd) 32{ 33 union genctrl_reg genctrl; 34 35 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 36 genctrl.softerr_int_en = 0; 37 genctrl.halt_int_en = 0; 38 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 39} 40 41static void free_hw_descs(struct idxd_wq *wq) 42{ 43 int i; 44 45 for (i = 0; i < wq->num_descs; i++) 46 kfree(wq->hw_descs[i]); 47 48 kfree(wq->hw_descs); 49} 50 51static int alloc_hw_descs(struct idxd_wq *wq, int num) 52{ 53 struct device *dev = &wq->idxd->pdev->dev; 54 int i; 55 int node = dev_to_node(dev); 56 57 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 58 GFP_KERNEL, node); 59 if (!wq->hw_descs) 60 return -ENOMEM; 61 62 for (i = 0; i < num; i++) { 63 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 64 GFP_KERNEL, node); 65 if (!wq->hw_descs[i]) { 66 free_hw_descs(wq); 67 return -ENOMEM; 68 } 69 } 70 71 return 0; 72} 73 74static void free_descs(struct idxd_wq *wq) 75{ 76 int i; 77 78 for (i = 0; i < wq->num_descs; i++) 79 kfree(wq->descs[i]); 80 81 kfree(wq->descs); 82} 83 84static int alloc_descs(struct idxd_wq *wq, int num) 85{ 86 struct device *dev = &wq->idxd->pdev->dev; 87 int i; 88 int node = dev_to_node(dev); 89 90 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 91 GFP_KERNEL, node); 92 if (!wq->descs) 93 return -ENOMEM; 94 95 for (i = 0; i < num; i++) { 96 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 97 GFP_KERNEL, node); 98 if (!wq->descs[i]) { 99 free_descs(wq); 100 return -ENOMEM; 101 } 102 } 103 104 return 0; 105} 106 107/* WQ control bits */ 108int idxd_wq_alloc_resources(struct idxd_wq *wq) 109{ 110 struct idxd_device *idxd = wq->idxd; 111 struct device *dev = &idxd->pdev->dev; 112 int rc, num_descs, i; 113 114 if (wq->type != IDXD_WQT_KERNEL) 115 return 0; 116 117 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold; 118 wq->num_descs = num_descs; 119 120 rc = alloc_hw_descs(wq, num_descs); 121 if (rc < 0) 122 return rc; 123 124 wq->compls_size = num_descs * idxd->data->compl_size; 125 wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL); 126 if (!wq->compls) { 127 rc = -ENOMEM; 128 goto fail_alloc_compls; 129 } 130 131 rc = alloc_descs(wq, num_descs); 132 if (rc < 0) 133 goto fail_alloc_descs; 134 135 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 136 dev_to_node(dev)); 137 if (rc < 0) 138 goto fail_sbitmap_init; 139 140 for (i = 0; i < num_descs; i++) { 141 struct idxd_desc *desc = wq->descs[i]; 142 143 desc->hw = wq->hw_descs[i]; 144 if (idxd->data->type == IDXD_TYPE_DSA) 145 desc->completion = &wq->compls[i]; 146 else if (idxd->data->type == IDXD_TYPE_IAX) 147 desc->iax_completion = &wq->iax_compls[i]; 148 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 149 desc->id = i; 150 desc->wq = wq; 151 desc->cpu = -1; 152 } 153 154 return 0; 155 156 fail_sbitmap_init: 157 free_descs(wq); 158 fail_alloc_descs: 159 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 160 fail_alloc_compls: 161 free_hw_descs(wq); 162 return rc; 163} 164 165void idxd_wq_free_resources(struct idxd_wq *wq) 166{ 167 struct device *dev = &wq->idxd->pdev->dev; 168 169 if (wq->type != IDXD_WQT_KERNEL) 170 return; 171 172 free_hw_descs(wq); 173 free_descs(wq); 174 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 175 sbitmap_queue_free(&wq->sbq); 176} 177 178int idxd_wq_enable(struct idxd_wq *wq) 179{ 180 struct idxd_device *idxd = wq->idxd; 181 struct device *dev = &idxd->pdev->dev; 182 u32 status; 183 184 if (wq->state == IDXD_WQ_ENABLED) { 185 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 186 return 0; 187 } 188 189 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 190 191 if (status != IDXD_CMDSTS_SUCCESS && 192 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 193 dev_dbg(dev, "WQ enable failed: %#x\n", status); 194 return -ENXIO; 195 } 196 197 wq->state = IDXD_WQ_ENABLED; 198 set_bit(wq->id, idxd->wq_enable_map); 199 dev_dbg(dev, "WQ %d enabled\n", wq->id); 200 return 0; 201} 202 203int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 204{ 205 struct idxd_device *idxd = wq->idxd; 206 struct device *dev = &idxd->pdev->dev; 207 u32 status, operand; 208 209 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 210 211 if (wq->state != IDXD_WQ_ENABLED) { 212 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 213 return 0; 214 } 215 216 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 217 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 218 219 if (status != IDXD_CMDSTS_SUCCESS) { 220 dev_dbg(dev, "WQ disable failed: %#x\n", status); 221 return -ENXIO; 222 } 223 224 if (reset_config) 225 idxd_wq_disable_cleanup(wq); 226 clear_bit(wq->id, idxd->wq_enable_map); 227 wq->state = IDXD_WQ_DISABLED; 228 dev_dbg(dev, "WQ %d disabled\n", wq->id); 229 return 0; 230} 231 232void idxd_wq_drain(struct idxd_wq *wq) 233{ 234 struct idxd_device *idxd = wq->idxd; 235 struct device *dev = &idxd->pdev->dev; 236 u32 operand; 237 238 if (wq->state != IDXD_WQ_ENABLED) { 239 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 240 return; 241 } 242 243 dev_dbg(dev, "Draining WQ %d\n", wq->id); 244 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 245 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 246} 247 248void idxd_wq_reset(struct idxd_wq *wq) 249{ 250 struct idxd_device *idxd = wq->idxd; 251 struct device *dev = &idxd->pdev->dev; 252 u32 operand; 253 254 if (wq->state != IDXD_WQ_ENABLED) { 255 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 256 return; 257 } 258 259 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 260 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 261 idxd_wq_disable_cleanup(wq); 262} 263 264int idxd_wq_map_portal(struct idxd_wq *wq) 265{ 266 struct idxd_device *idxd = wq->idxd; 267 struct pci_dev *pdev = idxd->pdev; 268 struct device *dev = &pdev->dev; 269 resource_size_t start; 270 271 start = pci_resource_start(pdev, IDXD_WQ_BAR); 272 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 273 274 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 275 if (!wq->portal) 276 return -ENOMEM; 277 278 return 0; 279} 280 281void idxd_wq_unmap_portal(struct idxd_wq *wq) 282{ 283 struct device *dev = &wq->idxd->pdev->dev; 284 285 devm_iounmap(dev, wq->portal); 286 wq->portal = NULL; 287 wq->portal_offset = 0; 288} 289 290void idxd_wqs_unmap_portal(struct idxd_device *idxd) 291{ 292 int i; 293 294 for (i = 0; i < idxd->max_wqs; i++) { 295 struct idxd_wq *wq = idxd->wqs[i]; 296 297 if (wq->portal) 298 idxd_wq_unmap_portal(wq); 299 } 300} 301 302static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid) 303{ 304 struct idxd_device *idxd = wq->idxd; 305 union wqcfg wqcfg; 306 unsigned int offset; 307 308 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 309 spin_lock(&idxd->dev_lock); 310 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 311 wqcfg.pasid_en = 1; 312 wqcfg.pasid = pasid; 313 wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX]; 314 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 315 spin_unlock(&idxd->dev_lock); 316} 317 318int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 319{ 320 int rc; 321 322 rc = idxd_wq_disable(wq, false); 323 if (rc < 0) 324 return rc; 325 326 __idxd_wq_set_pasid_locked(wq, pasid); 327 328 rc = idxd_wq_enable(wq); 329 if (rc < 0) 330 return rc; 331 332 return 0; 333} 334 335int idxd_wq_disable_pasid(struct idxd_wq *wq) 336{ 337 struct idxd_device *idxd = wq->idxd; 338 int rc; 339 union wqcfg wqcfg; 340 unsigned int offset; 341 342 rc = idxd_wq_disable(wq, false); 343 if (rc < 0) 344 return rc; 345 346 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 347 spin_lock(&idxd->dev_lock); 348 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 349 wqcfg.pasid_en = 0; 350 wqcfg.pasid = 0; 351 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 352 spin_unlock(&idxd->dev_lock); 353 354 rc = idxd_wq_enable(wq); 355 if (rc < 0) 356 return rc; 357 358 return 0; 359} 360 361static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 362{ 363 struct idxd_device *idxd = wq->idxd; 364 365 lockdep_assert_held(&wq->wq_lock); 366 wq->state = IDXD_WQ_DISABLED; 367 memset(wq->wqcfg, 0, idxd->wqcfg_size); 368 wq->type = IDXD_WQT_NONE; 369 wq->threshold = 0; 370 wq->priority = 0; 371 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 372 wq->flags = 0; 373 memset(wq->name, 0, WQ_NAME_SIZE); 374 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 375 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 376 if (wq->opcap_bmap) 377 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 378} 379 380static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq) 381{ 382 lockdep_assert_held(&wq->wq_lock); 383 384 wq->size = 0; 385 wq->group = NULL; 386} 387 388static void idxd_wq_ref_release(struct percpu_ref *ref) 389{ 390 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 391 392 complete(&wq->wq_dead); 393} 394 395int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 396{ 397 int rc; 398 399 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 400 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 401 PERCPU_REF_ALLOW_REINIT, GFP_KERNEL); 402 if (rc < 0) 403 return rc; 404 reinit_completion(&wq->wq_dead); 405 reinit_completion(&wq->wq_resurrect); 406 return 0; 407} 408 409void __idxd_wq_quiesce(struct idxd_wq *wq) 410{ 411 lockdep_assert_held(&wq->wq_lock); 412 reinit_completion(&wq->wq_resurrect); 413 percpu_ref_kill(&wq->wq_active); 414 complete_all(&wq->wq_resurrect); 415 wait_for_completion(&wq->wq_dead); 416} 417 418void idxd_wq_quiesce(struct idxd_wq *wq) 419{ 420 mutex_lock(&wq->wq_lock); 421 __idxd_wq_quiesce(wq); 422 mutex_unlock(&wq->wq_lock); 423} 424 425/* Device control bits */ 426static inline bool idxd_is_enabled(struct idxd_device *idxd) 427{ 428 union gensts_reg gensts; 429 430 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 431 432 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 433 return true; 434 return false; 435} 436 437static inline bool idxd_device_is_halted(struct idxd_device *idxd) 438{ 439 union gensts_reg gensts; 440 441 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 442 443 return (gensts.state == IDXD_DEVICE_STATE_HALT); 444} 445 446/* 447 * This is function is only used for reset during probe and will 448 * poll for completion. Once the device is setup with interrupts, 449 * all commands will be done via interrupt completion. 450 */ 451int idxd_device_init_reset(struct idxd_device *idxd) 452{ 453 struct device *dev = &idxd->pdev->dev; 454 union idxd_command_reg cmd; 455 456 if (idxd_device_is_halted(idxd)) { 457 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 458 return -ENXIO; 459 } 460 461 memset(&cmd, 0, sizeof(cmd)); 462 cmd.cmd = IDXD_CMD_RESET_DEVICE; 463 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 464 spin_lock(&idxd->cmd_lock); 465 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 466 467 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 468 IDXD_CMDSTS_ACTIVE) 469 cpu_relax(); 470 spin_unlock(&idxd->cmd_lock); 471 return 0; 472} 473 474static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 475 u32 *status) 476{ 477 union idxd_command_reg cmd; 478 DECLARE_COMPLETION_ONSTACK(done); 479 u32 stat; 480 unsigned long flags; 481 482 if (idxd_device_is_halted(idxd)) { 483 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 484 if (status) 485 *status = IDXD_CMDSTS_HW_ERR; 486 return; 487 } 488 489 memset(&cmd, 0, sizeof(cmd)); 490 cmd.cmd = cmd_code; 491 cmd.operand = operand; 492 cmd.int_req = 1; 493 494 spin_lock_irqsave(&idxd->cmd_lock, flags); 495 wait_event_lock_irq(idxd->cmd_waitq, 496 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 497 idxd->cmd_lock); 498 499 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 500 __func__, cmd_code, operand); 501 502 idxd->cmd_status = 0; 503 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 504 idxd->cmd_done = &done; 505 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 506 507 /* 508 * After command submitted, release lock and go to sleep until 509 * the command completes via interrupt. 510 */ 511 spin_unlock_irqrestore(&idxd->cmd_lock, flags); 512 wait_for_completion(&done); 513 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 514 spin_lock(&idxd->cmd_lock); 515 if (status) 516 *status = stat; 517 idxd->cmd_status = stat & GENMASK(7, 0); 518 519 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 520 /* Wake up other pending commands */ 521 wake_up(&idxd->cmd_waitq); 522 spin_unlock(&idxd->cmd_lock); 523} 524 525int idxd_device_enable(struct idxd_device *idxd) 526{ 527 struct device *dev = &idxd->pdev->dev; 528 u32 status; 529 530 if (idxd_is_enabled(idxd)) { 531 dev_dbg(dev, "Device already enabled\n"); 532 return -ENXIO; 533 } 534 535 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 536 537 /* If the command is successful or if the device was enabled */ 538 if (status != IDXD_CMDSTS_SUCCESS && 539 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 540 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 541 return -ENXIO; 542 } 543 544 idxd->state = IDXD_DEV_ENABLED; 545 return 0; 546} 547 548int idxd_device_disable(struct idxd_device *idxd) 549{ 550 struct device *dev = &idxd->pdev->dev; 551 u32 status; 552 553 if (!idxd_is_enabled(idxd)) { 554 dev_dbg(dev, "Device is not enabled\n"); 555 return 0; 556 } 557 558 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 559 560 /* If the command is successful or if the device was disabled */ 561 if (status != IDXD_CMDSTS_SUCCESS && 562 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 563 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 564 return -ENXIO; 565 } 566 567 idxd_device_clear_state(idxd); 568 return 0; 569} 570 571void idxd_device_reset(struct idxd_device *idxd) 572{ 573 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 574 idxd_device_clear_state(idxd); 575 spin_lock(&idxd->dev_lock); 576 idxd_unmask_error_interrupts(idxd); 577 spin_unlock(&idxd->dev_lock); 578} 579 580void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 581{ 582 struct device *dev = &idxd->pdev->dev; 583 u32 operand; 584 585 operand = pasid; 586 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 587 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 588 dev_dbg(dev, "pasid %d drained\n", pasid); 589} 590 591int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 592 enum idxd_interrupt_type irq_type) 593{ 594 struct device *dev = &idxd->pdev->dev; 595 u32 operand, status; 596 597 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 598 return -EOPNOTSUPP; 599 600 dev_dbg(dev, "get int handle, idx %d\n", idx); 601 602 operand = idx & GENMASK(15, 0); 603 if (irq_type == IDXD_IRQ_IMS) 604 operand |= CMD_INT_HANDLE_IMS; 605 606 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 607 608 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 609 610 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 611 dev_dbg(dev, "request int handle failed: %#x\n", status); 612 return -ENXIO; 613 } 614 615 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 616 617 dev_dbg(dev, "int handle acquired: %u\n", *handle); 618 return 0; 619} 620 621int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 622 enum idxd_interrupt_type irq_type) 623{ 624 struct device *dev = &idxd->pdev->dev; 625 u32 operand, status; 626 union idxd_command_reg cmd; 627 628 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 629 return -EOPNOTSUPP; 630 631 dev_dbg(dev, "release int handle, handle %d\n", handle); 632 633 memset(&cmd, 0, sizeof(cmd)); 634 operand = handle & GENMASK(15, 0); 635 636 if (irq_type == IDXD_IRQ_IMS) 637 operand |= CMD_INT_HANDLE_IMS; 638 639 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 640 cmd.operand = operand; 641 642 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 643 644 spin_lock(&idxd->cmd_lock); 645 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 646 647 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 648 cpu_relax(); 649 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 650 spin_unlock(&idxd->cmd_lock); 651 652 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 653 dev_dbg(dev, "release int handle failed: %#x\n", status); 654 return -ENXIO; 655 } 656 657 dev_dbg(dev, "int handle released.\n"); 658 return 0; 659} 660 661/* Device configuration bits */ 662static void idxd_engines_clear_state(struct idxd_device *idxd) 663{ 664 struct idxd_engine *engine; 665 int i; 666 667 lockdep_assert_held(&idxd->dev_lock); 668 for (i = 0; i < idxd->max_engines; i++) { 669 engine = idxd->engines[i]; 670 engine->group = NULL; 671 } 672} 673 674static void idxd_groups_clear_state(struct idxd_device *idxd) 675{ 676 struct idxd_group *group; 677 int i; 678 679 lockdep_assert_held(&idxd->dev_lock); 680 for (i = 0; i < idxd->max_groups; i++) { 681 group = idxd->groups[i]; 682 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 683 group->num_engines = 0; 684 group->num_wqs = 0; 685 group->use_rdbuf_limit = false; 686 /* 687 * The default value is the same as the value of 688 * total read buffers in GRPCAP. 689 */ 690 group->rdbufs_allowed = idxd->max_rdbufs; 691 group->rdbufs_reserved = 0; 692 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 693 group->tc_a = 1; 694 group->tc_b = 1; 695 } else { 696 group->tc_a = -1; 697 group->tc_b = -1; 698 } 699 group->desc_progress_limit = 0; 700 group->batch_progress_limit = 0; 701 } 702} 703 704static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 705{ 706 int i; 707 708 for (i = 0; i < idxd->max_wqs; i++) { 709 struct idxd_wq *wq = idxd->wqs[i]; 710 711 mutex_lock(&wq->wq_lock); 712 idxd_wq_disable_cleanup(wq); 713 idxd_wq_device_reset_cleanup(wq); 714 mutex_unlock(&wq->wq_lock); 715 } 716} 717 718void idxd_device_clear_state(struct idxd_device *idxd) 719{ 720 /* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */ 721 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 722 /* 723 * Clearing wq state is protected by wq lock. 724 * So no need to be protected by device lock. 725 */ 726 idxd_device_wqs_clear_state(idxd); 727 728 spin_lock(&idxd->dev_lock); 729 idxd_groups_clear_state(idxd); 730 idxd_engines_clear_state(idxd); 731 } else { 732 spin_lock(&idxd->dev_lock); 733 } 734 735 idxd->state = IDXD_DEV_DISABLED; 736 spin_unlock(&idxd->dev_lock); 737} 738 739static int idxd_device_evl_setup(struct idxd_device *idxd) 740{ 741 union gencfg_reg gencfg; 742 union evlcfg_reg evlcfg; 743 union genctrl_reg genctrl; 744 struct device *dev = &idxd->pdev->dev; 745 void *addr; 746 dma_addr_t dma_addr; 747 int size; 748 struct idxd_evl *evl = idxd->evl; 749 unsigned long *bmap; 750 int rc; 751 752 if (!evl) 753 return 0; 754 755 size = evl_size(idxd); 756 757 bmap = bitmap_zalloc(size, GFP_KERNEL); 758 if (!bmap) { 759 rc = -ENOMEM; 760 goto err_bmap; 761 } 762 763 /* 764 * Address needs to be page aligned. However, dma_alloc_coherent() provides 765 * at minimal page size aligned address. No manual alignment required. 766 */ 767 addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 768 if (!addr) { 769 rc = -ENOMEM; 770 goto err_alloc; 771 } 772 773 spin_lock(&evl->lock); 774 evl->log = addr; 775 evl->dma = dma_addr; 776 evl->log_size = size; 777 evl->bmap = bmap; 778 779 memset(&evlcfg, 0, sizeof(evlcfg)); 780 evlcfg.bits[0] = dma_addr & GENMASK(63, 12); 781 evlcfg.size = evl->size; 782 783 iowrite64(evlcfg.bits[0], idxd->reg_base + IDXD_EVLCFG_OFFSET); 784 iowrite64(evlcfg.bits[1], idxd->reg_base + IDXD_EVLCFG_OFFSET + 8); 785 786 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 787 genctrl.evl_int_en = 1; 788 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 789 790 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 791 gencfg.evl_en = 1; 792 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 793 794 spin_unlock(&evl->lock); 795 return 0; 796 797err_alloc: 798 bitmap_free(bmap); 799err_bmap: 800 return rc; 801} 802 803static void idxd_device_evl_free(struct idxd_device *idxd) 804{ 805 void *evl_log; 806 unsigned int evl_log_size; 807 dma_addr_t evl_dma; 808 union gencfg_reg gencfg; 809 union genctrl_reg genctrl; 810 struct device *dev = &idxd->pdev->dev; 811 struct idxd_evl *evl = idxd->evl; 812 813 gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 814 if (!gencfg.evl_en) 815 return; 816 817 spin_lock(&evl->lock); 818 gencfg.evl_en = 0; 819 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 820 821 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 822 genctrl.evl_int_en = 0; 823 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 824 825 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET); 826 iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8); 827 828 bitmap_free(evl->bmap); 829 evl_log = evl->log; 830 evl_log_size = evl->log_size; 831 evl_dma = evl->dma; 832 evl->log = NULL; 833 evl->size = IDXD_EVL_SIZE_MIN; 834 spin_unlock(&evl->lock); 835 836 dma_free_coherent(dev, evl_log_size, evl_log, evl_dma); 837} 838 839static void idxd_group_config_write(struct idxd_group *group) 840{ 841 struct idxd_device *idxd = group->idxd; 842 struct device *dev = &idxd->pdev->dev; 843 int i; 844 u32 grpcfg_offset; 845 846 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 847 848 /* setup GRPWQCFG */ 849 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 850 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 851 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 852 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 853 group->id, i, grpcfg_offset, 854 ioread64(idxd->reg_base + grpcfg_offset)); 855 } 856 857 /* setup GRPENGCFG */ 858 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 859 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 860 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 861 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 862 863 /* setup GRPFLAGS */ 864 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 865 iowrite64(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 866 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n", 867 group->id, grpcfg_offset, 868 ioread64(idxd->reg_base + grpcfg_offset)); 869} 870 871static int idxd_groups_config_write(struct idxd_device *idxd) 872 873{ 874 union gencfg_reg reg; 875 int i; 876 struct device *dev = &idxd->pdev->dev; 877 878 /* Setup bandwidth rdbuf limit */ 879 if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) { 880 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 881 reg.rdbuf_limit = idxd->rdbuf_limit; 882 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 883 } 884 885 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 886 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 887 888 for (i = 0; i < idxd->max_groups; i++) { 889 struct idxd_group *group = idxd->groups[i]; 890 891 idxd_group_config_write(group); 892 } 893 894 return 0; 895} 896 897static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd) 898{ 899 struct pci_dev *pdev = idxd->pdev; 900 901 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV)) 902 return true; 903 return false; 904} 905 906static int idxd_wq_config_write(struct idxd_wq *wq) 907{ 908 struct idxd_device *idxd = wq->idxd; 909 struct device *dev = &idxd->pdev->dev; 910 u32 wq_offset; 911 int i, n; 912 913 if (!wq->group) 914 return 0; 915 916 /* 917 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 918 * wq reset. This will copy back the sticky values that are present on some devices. 919 */ 920 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 921 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 922 wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset); 923 } 924 925 if (wq->size == 0 && wq->type != IDXD_WQT_NONE) 926 wq->size = WQ_DEFAULT_QUEUE_DEPTH; 927 928 /* byte 0-3 */ 929 wq->wqcfg->wq_size = wq->size; 930 931 /* bytes 4-7 */ 932 wq->wqcfg->wq_thresh = wq->threshold; 933 934 /* byte 8-11 */ 935 if (wq_dedicated(wq)) 936 wq->wqcfg->mode = 1; 937 938 /* 939 * The WQ priv bit is set depending on the WQ type. priv = 1 if the 940 * WQ type is kernel to indicate privileged access. This setting only 941 * matters for dedicated WQ. According to the DSA spec: 942 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the 943 * Privileged Mode Enable field of the PCI Express PASID capability 944 * is 0, this field must be 0. 945 * 946 * In the case of a dedicated kernel WQ that is not able to support 947 * the PASID cap, then the configuration will be rejected. 948 */ 949 if (wq_dedicated(wq) && wq->wqcfg->pasid_en && 950 !idxd_device_pasid_priv_enabled(idxd) && 951 wq->type == IDXD_WQT_KERNEL) { 952 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV; 953 return -EOPNOTSUPP; 954 } 955 956 wq->wqcfg->priority = wq->priority; 957 958 if (idxd->hw.gen_cap.block_on_fault && 959 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags) && 960 !test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags)) 961 wq->wqcfg->bof = 1; 962 963 if (idxd->hw.wq_cap.wq_ats_support) 964 wq->wqcfg->wq_ats_disable = test_bit(WQ_FLAG_ATS_DISABLE, &wq->flags); 965 966 if (idxd->hw.wq_cap.wq_prs_support) 967 wq->wqcfg->wq_prs_disable = test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags); 968 969 /* bytes 12-15 */ 970 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 971 idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size)); 972 973 /* bytes 32-63 */ 974 if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { 975 memset(wq->wqcfg->op_config, 0, IDXD_MAX_OPCAP_BITS / 8); 976 for_each_set_bit(n, wq->opcap_bmap, IDXD_MAX_OPCAP_BITS) { 977 int pos = n % BITS_PER_LONG_LONG; 978 int idx = n / BITS_PER_LONG_LONG; 979 980 wq->wqcfg->op_config[idx] |= BIT(pos); 981 } 982 } 983 984 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 985 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 986 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 987 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 988 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 989 wq->id, i, wq_offset, 990 ioread32(idxd->reg_base + wq_offset)); 991 } 992 993 return 0; 994} 995 996static int idxd_wqs_config_write(struct idxd_device *idxd) 997{ 998 int i, rc; 999 1000 for (i = 0; i < idxd->max_wqs; i++) { 1001 struct idxd_wq *wq = idxd->wqs[i]; 1002 1003 rc = idxd_wq_config_write(wq); 1004 if (rc < 0) 1005 return rc; 1006 } 1007 1008 return 0; 1009} 1010 1011static void idxd_group_flags_setup(struct idxd_device *idxd) 1012{ 1013 int i; 1014 1015 /* TC-A 0 and TC-B 1 should be defaults */ 1016 for (i = 0; i < idxd->max_groups; i++) { 1017 struct idxd_group *group = idxd->groups[i]; 1018 1019 if (group->tc_a == -1) 1020 group->tc_a = group->grpcfg.flags.tc_a = 0; 1021 else 1022 group->grpcfg.flags.tc_a = group->tc_a; 1023 if (group->tc_b == -1) 1024 group->tc_b = group->grpcfg.flags.tc_b = 1; 1025 else 1026 group->grpcfg.flags.tc_b = group->tc_b; 1027 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit; 1028 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved; 1029 group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed; 1030 group->grpcfg.flags.desc_progress_limit = group->desc_progress_limit; 1031 group->grpcfg.flags.batch_progress_limit = group->batch_progress_limit; 1032 } 1033} 1034 1035static int idxd_engines_setup(struct idxd_device *idxd) 1036{ 1037 int i, engines = 0; 1038 struct idxd_engine *eng; 1039 struct idxd_group *group; 1040 1041 for (i = 0; i < idxd->max_groups; i++) { 1042 group = idxd->groups[i]; 1043 group->grpcfg.engines = 0; 1044 } 1045 1046 for (i = 0; i < idxd->max_engines; i++) { 1047 eng = idxd->engines[i]; 1048 group = eng->group; 1049 1050 if (!group) 1051 continue; 1052 1053 group->grpcfg.engines |= BIT(eng->id); 1054 engines++; 1055 } 1056 1057 if (!engines) 1058 return -EINVAL; 1059 1060 return 0; 1061} 1062 1063static int idxd_wqs_setup(struct idxd_device *idxd) 1064{ 1065 struct idxd_wq *wq; 1066 struct idxd_group *group; 1067 int i, j, configured = 0; 1068 struct device *dev = &idxd->pdev->dev; 1069 1070 for (i = 0; i < idxd->max_groups; i++) { 1071 group = idxd->groups[i]; 1072 for (j = 0; j < 4; j++) 1073 group->grpcfg.wqs[j] = 0; 1074 } 1075 1076 for (i = 0; i < idxd->max_wqs; i++) { 1077 wq = idxd->wqs[i]; 1078 group = wq->group; 1079 1080 if (!wq->group) 1081 continue; 1082 1083 if (wq_shared(wq) && !wq_shared_supported(wq)) { 1084 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT; 1085 dev_warn(dev, "No shared wq support but configured.\n"); 1086 return -EINVAL; 1087 } 1088 1089 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 1090 configured++; 1091 } 1092 1093 if (configured == 0) { 1094 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED; 1095 return -EINVAL; 1096 } 1097 1098 return 0; 1099} 1100 1101int idxd_device_config(struct idxd_device *idxd) 1102{ 1103 int rc; 1104 1105 lockdep_assert_held(&idxd->dev_lock); 1106 rc = idxd_wqs_setup(idxd); 1107 if (rc < 0) 1108 return rc; 1109 1110 rc = idxd_engines_setup(idxd); 1111 if (rc < 0) 1112 return rc; 1113 1114 idxd_group_flags_setup(idxd); 1115 1116 rc = idxd_wqs_config_write(idxd); 1117 if (rc < 0) 1118 return rc; 1119 1120 rc = idxd_groups_config_write(idxd); 1121 if (rc < 0) 1122 return rc; 1123 1124 return 0; 1125} 1126 1127static int idxd_wq_load_config(struct idxd_wq *wq) 1128{ 1129 struct idxd_device *idxd = wq->idxd; 1130 struct device *dev = &idxd->pdev->dev; 1131 int wqcfg_offset; 1132 int i; 1133 1134 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1135 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1136 1137 wq->size = wq->wqcfg->wq_size; 1138 wq->threshold = wq->wqcfg->wq_thresh; 1139 1140 /* The driver does not support shared WQ mode in read-only config yet */ 1141 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1142 return -EOPNOTSUPP; 1143 1144 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1145 1146 wq->priority = wq->wqcfg->priority; 1147 1148 wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift; 1149 idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift); 1150 1151 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1152 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1153 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1154 } 1155 1156 return 0; 1157} 1158 1159static void idxd_group_load_config(struct idxd_group *group) 1160{ 1161 struct idxd_device *idxd = group->idxd; 1162 struct device *dev = &idxd->pdev->dev; 1163 int i, j, grpcfg_offset; 1164 1165 /* 1166 * Load WQS bit fields 1167 * Iterate through all 256 bits 64 bits at a time 1168 */ 1169 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1170 struct idxd_wq *wq; 1171 1172 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1173 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1174 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1175 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1176 1177 if (i * 64 >= idxd->max_wqs) 1178 break; 1179 1180 /* Iterate through all 64 bits and check for wq set */ 1181 for (j = 0; j < 64; j++) { 1182 int id = i * 64 + j; 1183 1184 /* No need to check beyond max wqs */ 1185 if (id >= idxd->max_wqs) 1186 break; 1187 1188 /* Set group assignment for wq if wq bit is set */ 1189 if (group->grpcfg.wqs[i] & BIT(j)) { 1190 wq = idxd->wqs[id]; 1191 wq->group = group; 1192 } 1193 } 1194 } 1195 1196 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1197 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1198 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1199 grpcfg_offset, group->grpcfg.engines); 1200 1201 /* Iterate through all 64 bits to check engines set */ 1202 for (i = 0; i < 64; i++) { 1203 if (i >= idxd->max_engines) 1204 break; 1205 1206 if (group->grpcfg.engines & BIT(i)) { 1207 struct idxd_engine *engine = idxd->engines[i]; 1208 1209 engine->group = group; 1210 } 1211 } 1212 1213 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1214 group->grpcfg.flags.bits = ioread64(idxd->reg_base + grpcfg_offset); 1215 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n", 1216 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1217} 1218 1219int idxd_device_load_config(struct idxd_device *idxd) 1220{ 1221 union gencfg_reg reg; 1222 int i, rc; 1223 1224 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1225 idxd->rdbuf_limit = reg.rdbuf_limit; 1226 1227 for (i = 0; i < idxd->max_groups; i++) { 1228 struct idxd_group *group = idxd->groups[i]; 1229 1230 idxd_group_load_config(group); 1231 } 1232 1233 for (i = 0; i < idxd->max_wqs; i++) { 1234 struct idxd_wq *wq = idxd->wqs[i]; 1235 1236 rc = idxd_wq_load_config(wq); 1237 if (rc < 0) 1238 return rc; 1239 } 1240 1241 return 0; 1242} 1243 1244static void idxd_flush_pending_descs(struct idxd_irq_entry *ie) 1245{ 1246 struct idxd_desc *desc, *itr; 1247 struct llist_node *head; 1248 LIST_HEAD(flist); 1249 enum idxd_complete_type ctype; 1250 1251 spin_lock(&ie->list_lock); 1252 head = llist_del_all(&ie->pending_llist); 1253 if (head) { 1254 llist_for_each_entry_safe(desc, itr, head, llnode) 1255 list_add_tail(&desc->list, &ie->work_list); 1256 } 1257 1258 list_for_each_entry_safe(desc, itr, &ie->work_list, list) 1259 list_move_tail(&desc->list, &flist); 1260 spin_unlock(&ie->list_lock); 1261 1262 list_for_each_entry_safe(desc, itr, &flist, list) { 1263 struct dma_async_tx_descriptor *tx; 1264 1265 list_del(&desc->list); 1266 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT; 1267 /* 1268 * wq is being disabled. Any remaining descriptors are 1269 * likely to be stuck and can be dropped. callback could 1270 * point to code that is no longer accessible, for example 1271 * if dmatest module has been unloaded. 1272 */ 1273 tx = &desc->txd; 1274 tx->callback = NULL; 1275 tx->callback_result = NULL; 1276 idxd_dma_complete_txd(desc, ctype, true); 1277 } 1278} 1279 1280static void idxd_device_set_perm_entry(struct idxd_device *idxd, 1281 struct idxd_irq_entry *ie) 1282{ 1283 union msix_perm mperm; 1284 1285 if (ie->pasid == IOMMU_PASID_INVALID) 1286 return; 1287 1288 mperm.bits = 0; 1289 mperm.pasid = ie->pasid; 1290 mperm.pasid_en = 1; 1291 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1292} 1293 1294static void idxd_device_clear_perm_entry(struct idxd_device *idxd, 1295 struct idxd_irq_entry *ie) 1296{ 1297 iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1298} 1299 1300void idxd_wq_free_irq(struct idxd_wq *wq) 1301{ 1302 struct idxd_device *idxd = wq->idxd; 1303 struct idxd_irq_entry *ie = &wq->ie; 1304 1305 if (wq->type != IDXD_WQT_KERNEL) 1306 return; 1307 1308 free_irq(ie->vector, ie); 1309 idxd_flush_pending_descs(ie); 1310 if (idxd->request_int_handles) 1311 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX); 1312 idxd_device_clear_perm_entry(idxd, ie); 1313 ie->vector = -1; 1314 ie->int_handle = INVALID_INT_HANDLE; 1315 ie->pasid = IOMMU_PASID_INVALID; 1316} 1317 1318int idxd_wq_request_irq(struct idxd_wq *wq) 1319{ 1320 struct idxd_device *idxd = wq->idxd; 1321 struct pci_dev *pdev = idxd->pdev; 1322 struct device *dev = &pdev->dev; 1323 struct idxd_irq_entry *ie; 1324 int rc; 1325 1326 if (wq->type != IDXD_WQT_KERNEL) 1327 return 0; 1328 1329 ie = &wq->ie; 1330 ie->vector = pci_irq_vector(pdev, ie->id); 1331 ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : IOMMU_PASID_INVALID; 1332 idxd_device_set_perm_entry(idxd, ie); 1333 1334 rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie); 1335 if (rc < 0) { 1336 dev_err(dev, "Failed to request irq %d.\n", ie->vector); 1337 goto err_irq; 1338 } 1339 1340 if (idxd->request_int_handles) { 1341 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle, 1342 IDXD_IRQ_MSIX); 1343 if (rc < 0) 1344 goto err_int_handle; 1345 } else { 1346 ie->int_handle = ie->id; 1347 } 1348 1349 return 0; 1350 1351err_int_handle: 1352 ie->int_handle = INVALID_INT_HANDLE; 1353 free_irq(ie->vector, ie); 1354err_irq: 1355 idxd_device_clear_perm_entry(idxd, ie); 1356 ie->pasid = IOMMU_PASID_INVALID; 1357 return rc; 1358} 1359 1360int drv_enable_wq(struct idxd_wq *wq) 1361{ 1362 struct idxd_device *idxd = wq->idxd; 1363 struct device *dev = &idxd->pdev->dev; 1364 int rc = -ENXIO; 1365 1366 lockdep_assert_held(&wq->wq_lock); 1367 1368 if (idxd->state != IDXD_DEV_ENABLED) { 1369 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED; 1370 goto err; 1371 } 1372 1373 if (wq->state != IDXD_WQ_DISABLED) { 1374 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1375 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED; 1376 rc = -EBUSY; 1377 goto err; 1378 } 1379 1380 if (!wq->group) { 1381 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1382 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP; 1383 goto err; 1384 } 1385 1386 if (strlen(wq->name) == 0) { 1387 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME; 1388 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1389 goto err; 1390 } 1391 1392 /* Shared WQ checks */ 1393 if (wq_shared(wq)) { 1394 if (!wq_shared_supported(wq)) { 1395 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM; 1396 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1397 goto err; 1398 } 1399 /* 1400 * Shared wq with the threshold set to 0 means the user 1401 * did not set the threshold or transitioned from a 1402 * dedicated wq but did not set threshold. A value 1403 * of 0 would effectively disable the shared wq. The 1404 * driver does not allow a value of 0 to be set for 1405 * threshold via sysfs. 1406 */ 1407 if (wq->threshold == 0) { 1408 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH; 1409 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1410 goto err; 1411 } 1412 } 1413 1414 /* 1415 * In the event that the WQ is configurable for pasid, the driver 1416 * should setup the pasid, pasid_en bit. This is true for both kernel 1417 * and user shared workqueues. There is no need to setup priv bit in 1418 * that in-kernel DMA will also do user privileged requests. 1419 * A dedicated wq that is not 'kernel' type will configure pasid and 1420 * pasid_en later on so there is no need to setup. 1421 */ 1422 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 1423 if (wq_pasid_enabled(wq)) { 1424 if (is_idxd_wq_kernel(wq) || wq_shared(wq)) { 1425 u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0; 1426 1427 __idxd_wq_set_pasid_locked(wq, pasid); 1428 } 1429 } 1430 } 1431 1432 rc = 0; 1433 spin_lock(&idxd->dev_lock); 1434 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1435 rc = idxd_device_config(idxd); 1436 spin_unlock(&idxd->dev_lock); 1437 if (rc < 0) { 1438 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1439 goto err; 1440 } 1441 1442 rc = idxd_wq_enable(wq); 1443 if (rc < 0) { 1444 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1445 goto err; 1446 } 1447 1448 rc = idxd_wq_map_portal(wq); 1449 if (rc < 0) { 1450 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR; 1451 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1452 goto err_map_portal; 1453 } 1454 1455 wq->client_count = 0; 1456 1457 rc = idxd_wq_request_irq(wq); 1458 if (rc < 0) { 1459 idxd->cmd_status = IDXD_SCMD_WQ_IRQ_ERR; 1460 dev_dbg(dev, "WQ %d irq setup failed: %d\n", wq->id, rc); 1461 goto err_irq; 1462 } 1463 1464 rc = idxd_wq_alloc_resources(wq); 1465 if (rc < 0) { 1466 idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR; 1467 dev_dbg(dev, "WQ resource alloc failed\n"); 1468 goto err_res_alloc; 1469 } 1470 1471 rc = idxd_wq_init_percpu_ref(wq); 1472 if (rc < 0) { 1473 idxd->cmd_status = IDXD_SCMD_PERCPU_ERR; 1474 dev_dbg(dev, "percpu_ref setup failed\n"); 1475 goto err_ref; 1476 } 1477 1478 return 0; 1479 1480err_ref: 1481 idxd_wq_free_resources(wq); 1482err_res_alloc: 1483 idxd_wq_free_irq(wq); 1484err_irq: 1485 idxd_wq_unmap_portal(wq); 1486err_map_portal: 1487 if (idxd_wq_disable(wq, false)) 1488 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1489err: 1490 return rc; 1491} 1492 1493void drv_disable_wq(struct idxd_wq *wq) 1494{ 1495 struct idxd_device *idxd = wq->idxd; 1496 struct device *dev = &idxd->pdev->dev; 1497 1498 lockdep_assert_held(&wq->wq_lock); 1499 1500 if (idxd_wq_refcount(wq)) 1501 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1502 wq->id, idxd_wq_refcount(wq)); 1503 1504 idxd_wq_unmap_portal(wq); 1505 idxd_wq_drain(wq); 1506 idxd_wq_free_irq(wq); 1507 idxd_wq_reset(wq); 1508 idxd_wq_free_resources(wq); 1509 percpu_ref_exit(&wq->wq_active); 1510 wq->type = IDXD_WQT_NONE; 1511 wq->client_count = 0; 1512} 1513 1514int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1515{ 1516 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1517 int rc = 0; 1518 1519 /* 1520 * Device should be in disabled state for the idxd_drv to load. If it's in 1521 * enabled state, then the device was altered outside of driver's control. 1522 * If the state is in halted state, then we don't want to proceed. 1523 */ 1524 if (idxd->state != IDXD_DEV_DISABLED) { 1525 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED; 1526 return -ENXIO; 1527 } 1528 1529 /* Device configuration */ 1530 spin_lock(&idxd->dev_lock); 1531 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1532 rc = idxd_device_config(idxd); 1533 spin_unlock(&idxd->dev_lock); 1534 if (rc < 0) 1535 return -ENXIO; 1536 1537 /* 1538 * System PASID is preserved across device disable/enable cycle, but 1539 * genconfig register content gets cleared during device reset. We 1540 * need to re-enable user interrupts for kernel work queue completion 1541 * IRQ to function. 1542 */ 1543 if (idxd->pasid != IOMMU_PASID_INVALID) 1544 idxd_set_user_intr(idxd, 1); 1545 1546 rc = idxd_device_evl_setup(idxd); 1547 if (rc < 0) { 1548 idxd->cmd_status = IDXD_SCMD_DEV_EVL_ERR; 1549 return rc; 1550 } 1551 1552 /* Start device */ 1553 rc = idxd_device_enable(idxd); 1554 if (rc < 0) { 1555 idxd_device_evl_free(idxd); 1556 return rc; 1557 } 1558 1559 /* Setup DMA device without channels */ 1560 rc = idxd_register_dma_device(idxd); 1561 if (rc < 0) { 1562 idxd_device_disable(idxd); 1563 idxd_device_evl_free(idxd); 1564 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR; 1565 return rc; 1566 } 1567 1568 idxd->cmd_status = 0; 1569 return 0; 1570} 1571 1572void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1573{ 1574 struct device *dev = &idxd_dev->conf_dev; 1575 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1576 int i; 1577 1578 for (i = 0; i < idxd->max_wqs; i++) { 1579 struct idxd_wq *wq = idxd->wqs[i]; 1580 struct device *wq_dev = wq_confdev(wq); 1581 1582 if (wq->state == IDXD_WQ_DISABLED) 1583 continue; 1584 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1585 device_release_driver(wq_dev); 1586 } 1587 1588 idxd_unregister_dma_device(idxd); 1589 idxd_device_disable(idxd); 1590 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1591 idxd_device_reset(idxd); 1592 idxd_device_evl_free(idxd); 1593} 1594 1595static enum idxd_dev_type dev_types[] = { 1596 IDXD_DEV_DSA, 1597 IDXD_DEV_IAX, 1598 IDXD_DEV_NONE, 1599}; 1600 1601struct idxd_device_driver idxd_drv = { 1602 .type = dev_types, 1603 .probe = idxd_device_drv_probe, 1604 .remove = idxd_device_drv_remove, 1605 .name = "idxd", 1606}; 1607EXPORT_SYMBOL_GPL(idxd_drv); 1608