1// SPDX-License-Identifier: GPL-2.0 2// (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) 3 4/* 5 * Synopsys DesignWare AXI DMA Controller driver. 6 * 7 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 8 */ 9 10#include <linux/bitops.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/dmaengine.h> 14#include <linux/dmapool.h> 15#include <linux/dma-mapping.h> 16#include <linux/err.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/iopoll.h> 20#include <linux/io-64-nonatomic-lo-hi.h> 21#include <linux/kernel.h> 22#include <linux/module.h> 23#include <linux/of.h> 24#include <linux/of_dma.h> 25#include <linux/platform_device.h> 26#include <linux/pm_runtime.h> 27#include <linux/property.h> 28#include <linux/reset.h> 29#include <linux/slab.h> 30#include <linux/types.h> 31 32#include "dw-axi-dmac.h" 33#include "../dmaengine.h" 34#include "../virt-dma.h" 35 36/* 37 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports 38 * master data bus width up to 512 bits (for both AXI master interfaces), but 39 * it depends on IP block configuration. 40 */ 41#define AXI_DMA_BUSWIDTHS \ 42 (DMA_SLAVE_BUSWIDTH_1_BYTE | \ 43 DMA_SLAVE_BUSWIDTH_2_BYTES | \ 44 DMA_SLAVE_BUSWIDTH_4_BYTES | \ 45 DMA_SLAVE_BUSWIDTH_8_BYTES | \ 46 DMA_SLAVE_BUSWIDTH_16_BYTES | \ 47 DMA_SLAVE_BUSWIDTH_32_BYTES | \ 48 DMA_SLAVE_BUSWIDTH_64_BYTES) 49 50#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0) 51#define AXI_DMA_FLAG_HAS_RESETS BIT(1) 52#define AXI_DMA_FLAG_USE_CFG2 BIT(2) 53 54static inline void 55axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) 56{ 57 iowrite32(val, chip->regs + reg); 58} 59 60static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg) 61{ 62 return ioread32(chip->regs + reg); 63} 64 65static inline void 66axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) 67{ 68 iowrite32(val, chan->chan_regs + reg); 69} 70 71static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) 72{ 73 return ioread32(chan->chan_regs + reg); 74} 75 76static inline void 77axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) 78{ 79 /* 80 * We split one 64 bit write for two 32 bit write as some HW doesn't 81 * support 64 bit access. 82 */ 83 iowrite32(lower_32_bits(val), chan->chan_regs + reg); 84 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); 85} 86 87static inline void axi_chan_config_write(struct axi_dma_chan *chan, 88 struct axi_dma_chan_config *config) 89{ 90 u32 cfg_lo, cfg_hi; 91 92 cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | 93 config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); 94 if (chan->chip->dw->hdata->reg_map_8_channels && 95 !chan->chip->dw->hdata->use_cfg2) { 96 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | 97 config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | 98 config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | 99 config->src_per << CH_CFG_H_SRC_PER_POS | 100 config->dst_per << CH_CFG_H_DST_PER_POS | 101 config->prior << CH_CFG_H_PRIORITY_POS; 102 } else { 103 cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS | 104 config->dst_per << CH_CFG2_L_DST_PER_POS; 105 cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS | 106 config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS | 107 config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS | 108 config->prior << CH_CFG2_H_PRIORITY_POS; 109 } 110 axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo); 111 axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi); 112} 113 114static inline void axi_dma_disable(struct axi_dma_chip *chip) 115{ 116 u32 val; 117 118 val = axi_dma_ioread32(chip, DMAC_CFG); 119 val &= ~DMAC_EN_MASK; 120 axi_dma_iowrite32(chip, DMAC_CFG, val); 121} 122 123static inline void axi_dma_enable(struct axi_dma_chip *chip) 124{ 125 u32 val; 126 127 val = axi_dma_ioread32(chip, DMAC_CFG); 128 val |= DMAC_EN_MASK; 129 axi_dma_iowrite32(chip, DMAC_CFG, val); 130} 131 132static inline void axi_dma_irq_disable(struct axi_dma_chip *chip) 133{ 134 u32 val; 135 136 val = axi_dma_ioread32(chip, DMAC_CFG); 137 val &= ~INT_EN_MASK; 138 axi_dma_iowrite32(chip, DMAC_CFG, val); 139} 140 141static inline void axi_dma_irq_enable(struct axi_dma_chip *chip) 142{ 143 u32 val; 144 145 val = axi_dma_ioread32(chip, DMAC_CFG); 146 val |= INT_EN_MASK; 147 axi_dma_iowrite32(chip, DMAC_CFG, val); 148} 149 150static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask) 151{ 152 u32 val; 153 154 if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) { 155 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE); 156 } else { 157 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA); 158 val &= ~irq_mask; 159 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val); 160 } 161} 162 163static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask) 164{ 165 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask); 166} 167 168static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask) 169{ 170 axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask); 171} 172 173static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask) 174{ 175 axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask); 176} 177 178static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan) 179{ 180 return axi_chan_ioread32(chan, CH_INTSTATUS); 181} 182 183static inline void axi_chan_disable(struct axi_dma_chan *chan) 184{ 185 u32 val; 186 187 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 188 val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); 189 if (chan->chip->dw->hdata->reg_map_8_channels) 190 val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 191 else 192 val |= BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; 193 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 194} 195 196static inline void axi_chan_enable(struct axi_dma_chan *chan) 197{ 198 u32 val; 199 200 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 201 if (chan->chip->dw->hdata->reg_map_8_channels) 202 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 203 BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 204 else 205 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 206 BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; 207 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 208} 209 210static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan) 211{ 212 u32 val; 213 214 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 215 216 return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT)); 217} 218 219static void axi_dma_hw_init(struct axi_dma_chip *chip) 220{ 221 int ret; 222 u32 i; 223 224 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { 225 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 226 axi_chan_disable(&chip->dw->chan[i]); 227 } 228 ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64)); 229 if (ret) 230 dev_warn(chip->dev, "Unable to set coherent mask\n"); 231} 232 233static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src, 234 dma_addr_t dst, size_t len) 235{ 236 u32 max_width = chan->chip->dw->hdata->m_data_width; 237 238 return __ffs(src | dst | len | BIT(max_width)); 239} 240 241static inline const char *axi_chan_name(struct axi_dma_chan *chan) 242{ 243 return dma_chan_name(&chan->vc.chan); 244} 245 246static struct axi_dma_desc *axi_desc_alloc(u32 num) 247{ 248 struct axi_dma_desc *desc; 249 250 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 251 if (!desc) 252 return NULL; 253 254 desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT); 255 if (!desc->hw_desc) { 256 kfree(desc); 257 return NULL; 258 } 259 260 return desc; 261} 262 263static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, 264 dma_addr_t *addr) 265{ 266 struct axi_dma_lli *lli; 267 dma_addr_t phys; 268 269 lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); 270 if (unlikely(!lli)) { 271 dev_err(chan2dev(chan), "%s: not enough descriptors available\n", 272 axi_chan_name(chan)); 273 return NULL; 274 } 275 276 atomic_inc(&chan->descs_allocated); 277 *addr = phys; 278 279 return lli; 280} 281 282static void axi_desc_put(struct axi_dma_desc *desc) 283{ 284 struct axi_dma_chan *chan = desc->chan; 285 int count = atomic_read(&chan->descs_allocated); 286 struct axi_dma_hw_desc *hw_desc; 287 int descs_put; 288 289 for (descs_put = 0; descs_put < count; descs_put++) { 290 hw_desc = &desc->hw_desc[descs_put]; 291 dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp); 292 } 293 294 kfree(desc->hw_desc); 295 kfree(desc); 296 atomic_sub(descs_put, &chan->descs_allocated); 297 dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", 298 axi_chan_name(chan), descs_put, 299 atomic_read(&chan->descs_allocated)); 300} 301 302static void vchan_desc_put(struct virt_dma_desc *vdesc) 303{ 304 axi_desc_put(vd_to_axi_desc(vdesc)); 305} 306 307static enum dma_status 308dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, 309 struct dma_tx_state *txstate) 310{ 311 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 312 struct virt_dma_desc *vdesc; 313 enum dma_status status; 314 u32 completed_length; 315 unsigned long flags; 316 u32 completed_blocks; 317 size_t bytes = 0; 318 u32 length; 319 u32 len; 320 321 status = dma_cookie_status(dchan, cookie, txstate); 322 if (status == DMA_COMPLETE || !txstate) 323 return status; 324 325 spin_lock_irqsave(&chan->vc.lock, flags); 326 327 vdesc = vchan_find_desc(&chan->vc, cookie); 328 if (vdesc) { 329 length = vd_to_axi_desc(vdesc)->length; 330 completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks; 331 len = vd_to_axi_desc(vdesc)->hw_desc[0].len; 332 completed_length = completed_blocks * len; 333 bytes = length - completed_length; 334 } 335 336 spin_unlock_irqrestore(&chan->vc.lock, flags); 337 dma_set_residue(txstate, bytes); 338 339 return status; 340} 341 342static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr) 343{ 344 desc->lli->llp = cpu_to_le64(adr); 345} 346 347static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr) 348{ 349 axi_chan_iowrite64(chan, CH_LLP, adr); 350} 351 352static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set) 353{ 354 u32 offset = DMAC_APB_BYTE_WR_CH_EN; 355 u32 reg_width, val; 356 357 if (!chan->chip->apb_regs) { 358 dev_dbg(chan->chip->dev, "apb_regs not initialized\n"); 359 return; 360 } 361 362 reg_width = __ffs(chan->config.dst_addr_width); 363 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) 364 offset = DMAC_APB_HALFWORD_WR_CH_EN; 365 366 val = ioread32(chan->chip->apb_regs + offset); 367 368 if (set) 369 val |= BIT(chan->id); 370 else 371 val &= ~BIT(chan->id); 372 373 iowrite32(val, chan->chip->apb_regs + offset); 374} 375/* Called in chan locked context */ 376static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, 377 struct axi_dma_desc *first) 378{ 379 u32 priority = chan->chip->dw->hdata->priority[chan->id]; 380 struct axi_dma_chan_config config = {}; 381 u32 irq_mask; 382 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 383 384 if (unlikely(axi_chan_is_hw_enable(chan))) { 385 dev_err(chan2dev(chan), "%s is non-idle!\n", 386 axi_chan_name(chan)); 387 388 return; 389 } 390 391 axi_dma_enable(chan->chip); 392 393 config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; 394 config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; 395 config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC; 396 config.prior = priority; 397 config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW; 398 config.hs_sel_src = DWAXIDMAC_HS_SEL_HW; 399 switch (chan->direction) { 400 case DMA_MEM_TO_DEV: 401 dw_axi_dma_set_byte_halfword(chan, true); 402 config.tt_fc = chan->config.device_fc ? 403 DWAXIDMAC_TT_FC_MEM_TO_PER_DST : 404 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC; 405 if (chan->chip->apb_regs) 406 config.dst_per = chan->id; 407 else 408 config.dst_per = chan->hw_handshake_num; 409 break; 410 case DMA_DEV_TO_MEM: 411 config.tt_fc = chan->config.device_fc ? 412 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC : 413 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC; 414 if (chan->chip->apb_regs) 415 config.src_per = chan->id; 416 else 417 config.src_per = chan->hw_handshake_num; 418 break; 419 default: 420 break; 421 } 422 axi_chan_config_write(chan, &config); 423 424 write_chan_llp(chan, first->hw_desc[0].llp | lms); 425 426 irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR; 427 axi_chan_irq_sig_set(chan, irq_mask); 428 429 /* Generate 'suspend' status but don't generate interrupt */ 430 irq_mask |= DWAXIDMAC_IRQ_SUSPENDED; 431 axi_chan_irq_set(chan, irq_mask); 432 433 axi_chan_enable(chan); 434} 435 436static void axi_chan_start_first_queued(struct axi_dma_chan *chan) 437{ 438 struct axi_dma_desc *desc; 439 struct virt_dma_desc *vd; 440 441 vd = vchan_next_desc(&chan->vc); 442 if (!vd) 443 return; 444 445 desc = vd_to_axi_desc(vd); 446 dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan), 447 vd->tx.cookie); 448 axi_chan_block_xfer_start(chan, desc); 449} 450 451static void dma_chan_issue_pending(struct dma_chan *dchan) 452{ 453 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 454 unsigned long flags; 455 456 spin_lock_irqsave(&chan->vc.lock, flags); 457 if (vchan_issue_pending(&chan->vc)) 458 axi_chan_start_first_queued(chan); 459 spin_unlock_irqrestore(&chan->vc.lock, flags); 460} 461 462static void dw_axi_dma_synchronize(struct dma_chan *dchan) 463{ 464 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 465 466 vchan_synchronize(&chan->vc); 467} 468 469static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) 470{ 471 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 472 473 /* ASSERT: channel is idle */ 474 if (axi_chan_is_hw_enable(chan)) { 475 dev_err(chan2dev(chan), "%s is non-idle!\n", 476 axi_chan_name(chan)); 477 return -EBUSY; 478 } 479 480 /* LLI address must be aligned to a 64-byte boundary */ 481 chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)), 482 chan->chip->dev, 483 sizeof(struct axi_dma_lli), 484 64, 0); 485 if (!chan->desc_pool) { 486 dev_err(chan2dev(chan), "No memory for descriptors\n"); 487 return -ENOMEM; 488 } 489 dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan)); 490 491 pm_runtime_get(chan->chip->dev); 492 493 return 0; 494} 495 496static void dma_chan_free_chan_resources(struct dma_chan *dchan) 497{ 498 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 499 500 /* ASSERT: channel is idle */ 501 if (axi_chan_is_hw_enable(chan)) 502 dev_err(dchan2dev(dchan), "%s is non-idle!\n", 503 axi_chan_name(chan)); 504 505 axi_chan_disable(chan); 506 axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL); 507 508 vchan_free_chan_resources(&chan->vc); 509 510 dma_pool_destroy(chan->desc_pool); 511 chan->desc_pool = NULL; 512 dev_vdbg(dchan2dev(dchan), 513 "%s: free resources, descriptor still allocated: %u\n", 514 axi_chan_name(chan), atomic_read(&chan->descs_allocated)); 515 516 pm_runtime_put(chan->chip->dev); 517} 518 519static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set) 520{ 521 struct axi_dma_chip *chip = chan->chip; 522 unsigned long reg_value, val; 523 524 if (!chip->apb_regs) { 525 dev_err(chip->dev, "apb_regs not initialized\n"); 526 return; 527 } 528 529 /* 530 * An unused DMA channel has a default value of 0x3F. 531 * Lock the DMA channel by assign a handshake number to the channel. 532 * Unlock the DMA channel by assign 0x3F to the channel. 533 */ 534 if (set) 535 val = chan->hw_handshake_num; 536 else 537 val = UNUSED_CHANNEL; 538 539 reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 540 541 /* Channel is already allocated, set handshake as per channel ID */ 542 /* 64 bit write should handle for 8 channels */ 543 544 reg_value &= ~(DMA_APB_HS_SEL_MASK << 545 (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 546 reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 547 lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 548 549 return; 550} 551 552/* 553 * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI 554 * as 1, it understands that the current block is the final block in the 555 * transfer and completes the DMA transfer operation at the end of current 556 * block transfer. 557 */ 558static void set_desc_last(struct axi_dma_hw_desc *desc) 559{ 560 u32 val; 561 562 val = le32_to_cpu(desc->lli->ctl_hi); 563 val |= CH_CTL_H_LLI_LAST; 564 desc->lli->ctl_hi = cpu_to_le32(val); 565} 566 567static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr) 568{ 569 desc->lli->sar = cpu_to_le64(adr); 570} 571 572static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr) 573{ 574 desc->lli->dar = cpu_to_le64(adr); 575} 576 577static void set_desc_src_master(struct axi_dma_hw_desc *desc) 578{ 579 u32 val; 580 581 /* Select AXI0 for source master */ 582 val = le32_to_cpu(desc->lli->ctl_lo); 583 val &= ~CH_CTL_L_SRC_MAST; 584 desc->lli->ctl_lo = cpu_to_le32(val); 585} 586 587static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc, 588 struct axi_dma_desc *desc) 589{ 590 u32 val; 591 592 /* Select AXI1 for source master if available */ 593 val = le32_to_cpu(hw_desc->lli->ctl_lo); 594 if (desc->chan->chip->dw->hdata->nr_masters > 1) 595 val |= CH_CTL_L_DST_MAST; 596 else 597 val &= ~CH_CTL_L_DST_MAST; 598 599 hw_desc->lli->ctl_lo = cpu_to_le32(val); 600} 601 602static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, 603 struct axi_dma_hw_desc *hw_desc, 604 dma_addr_t mem_addr, size_t len) 605{ 606 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); 607 unsigned int reg_width; 608 unsigned int mem_width; 609 dma_addr_t device_addr; 610 size_t axi_block_ts; 611 size_t block_ts; 612 u32 ctllo, ctlhi; 613 u32 burst_len; 614 615 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 616 617 mem_width = __ffs(data_width | mem_addr | len); 618 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 619 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 620 621 if (!IS_ALIGNED(mem_addr, 4)) { 622 dev_err(chan->chip->dev, "invalid buffer alignment\n"); 623 return -EINVAL; 624 } 625 626 switch (chan->direction) { 627 case DMA_MEM_TO_DEV: 628 reg_width = __ffs(chan->config.dst_addr_width); 629 device_addr = chan->config.dst_addr; 630 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | 631 mem_width << CH_CTL_L_SRC_WIDTH_POS | 632 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | 633 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; 634 block_ts = len >> mem_width; 635 break; 636 case DMA_DEV_TO_MEM: 637 reg_width = __ffs(chan->config.src_addr_width); 638 device_addr = chan->config.src_addr; 639 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | 640 mem_width << CH_CTL_L_DST_WIDTH_POS | 641 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 642 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; 643 block_ts = len >> reg_width; 644 break; 645 default: 646 return -EINVAL; 647 } 648 649 if (block_ts > axi_block_ts) 650 return -EINVAL; 651 652 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); 653 if (unlikely(!hw_desc->lli)) 654 return -ENOMEM; 655 656 ctlhi = CH_CTL_H_LLI_VALID; 657 658 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 659 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 660 ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN | 661 burst_len << CH_CTL_H_ARLEN_POS | 662 burst_len << CH_CTL_H_AWLEN_POS; 663 } 664 665 hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi); 666 667 if (chan->direction == DMA_MEM_TO_DEV) { 668 write_desc_sar(hw_desc, mem_addr); 669 write_desc_dar(hw_desc, device_addr); 670 } else { 671 write_desc_sar(hw_desc, device_addr); 672 write_desc_dar(hw_desc, mem_addr); 673 } 674 675 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); 676 677 ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 678 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS; 679 hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); 680 681 set_desc_src_master(hw_desc); 682 683 hw_desc->len = len; 684 return 0; 685} 686 687static size_t calculate_block_len(struct axi_dma_chan *chan, 688 dma_addr_t dma_addr, size_t buf_len, 689 enum dma_transfer_direction direction) 690{ 691 u32 data_width, reg_width, mem_width; 692 size_t axi_block_ts, block_len; 693 694 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 695 696 switch (direction) { 697 case DMA_MEM_TO_DEV: 698 data_width = BIT(chan->chip->dw->hdata->m_data_width); 699 mem_width = __ffs(data_width | dma_addr | buf_len); 700 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 701 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 702 703 block_len = axi_block_ts << mem_width; 704 break; 705 case DMA_DEV_TO_MEM: 706 reg_width = __ffs(chan->config.src_addr_width); 707 block_len = axi_block_ts << reg_width; 708 break; 709 default: 710 block_len = 0; 711 } 712 713 return block_len; 714} 715 716static struct dma_async_tx_descriptor * 717dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr, 718 size_t buf_len, size_t period_len, 719 enum dma_transfer_direction direction, 720 unsigned long flags) 721{ 722 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 723 struct axi_dma_hw_desc *hw_desc = NULL; 724 struct axi_dma_desc *desc = NULL; 725 dma_addr_t src_addr = dma_addr; 726 u32 num_periods, num_segments; 727 size_t axi_block_len; 728 u32 total_segments; 729 u32 segment_len; 730 unsigned int i; 731 int status; 732 u64 llp = 0; 733 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 734 735 num_periods = buf_len / period_len; 736 737 axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction); 738 if (axi_block_len == 0) 739 return NULL; 740 741 num_segments = DIV_ROUND_UP(period_len, axi_block_len); 742 segment_len = DIV_ROUND_UP(period_len, num_segments); 743 744 total_segments = num_periods * num_segments; 745 746 desc = axi_desc_alloc(total_segments); 747 if (unlikely(!desc)) 748 goto err_desc_get; 749 750 chan->direction = direction; 751 desc->chan = chan; 752 chan->cyclic = true; 753 desc->length = 0; 754 desc->period_len = period_len; 755 756 for (i = 0; i < total_segments; i++) { 757 hw_desc = &desc->hw_desc[i]; 758 759 status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr, 760 segment_len); 761 if (status < 0) 762 goto err_desc_get; 763 764 desc->length += hw_desc->len; 765 /* Set end-of-link to the linked descriptor, so that cyclic 766 * callback function can be triggered during interrupt. 767 */ 768 set_desc_last(hw_desc); 769 770 src_addr += segment_len; 771 } 772 773 llp = desc->hw_desc[0].llp; 774 775 /* Managed transfer list */ 776 do { 777 hw_desc = &desc->hw_desc[--total_segments]; 778 write_desc_llp(hw_desc, llp | lms); 779 llp = hw_desc->llp; 780 } while (total_segments); 781 782 dw_axi_dma_set_hw_channel(chan, true); 783 784 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 785 786err_desc_get: 787 if (desc) 788 axi_desc_put(desc); 789 790 return NULL; 791} 792 793static struct dma_async_tx_descriptor * 794dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 795 unsigned int sg_len, 796 enum dma_transfer_direction direction, 797 unsigned long flags, void *context) 798{ 799 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 800 struct axi_dma_hw_desc *hw_desc = NULL; 801 struct axi_dma_desc *desc = NULL; 802 u32 num_segments, segment_len; 803 unsigned int loop = 0; 804 struct scatterlist *sg; 805 size_t axi_block_len; 806 u32 len, num_sgs = 0; 807 unsigned int i; 808 dma_addr_t mem; 809 int status; 810 u64 llp = 0; 811 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 812 813 if (unlikely(!is_slave_direction(direction) || !sg_len)) 814 return NULL; 815 816 mem = sg_dma_address(sgl); 817 len = sg_dma_len(sgl); 818 819 axi_block_len = calculate_block_len(chan, mem, len, direction); 820 if (axi_block_len == 0) 821 return NULL; 822 823 for_each_sg(sgl, sg, sg_len, i) 824 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); 825 826 desc = axi_desc_alloc(num_sgs); 827 if (unlikely(!desc)) 828 goto err_desc_get; 829 830 desc->chan = chan; 831 desc->length = 0; 832 chan->direction = direction; 833 834 for_each_sg(sgl, sg, sg_len, i) { 835 mem = sg_dma_address(sg); 836 len = sg_dma_len(sg); 837 num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); 838 segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments); 839 840 do { 841 hw_desc = &desc->hw_desc[loop++]; 842 status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len); 843 if (status < 0) 844 goto err_desc_get; 845 846 desc->length += hw_desc->len; 847 len -= segment_len; 848 mem += segment_len; 849 } while (len >= segment_len); 850 } 851 852 /* Set end-of-link to the last link descriptor of list */ 853 set_desc_last(&desc->hw_desc[num_sgs - 1]); 854 855 /* Managed transfer list */ 856 do { 857 hw_desc = &desc->hw_desc[--num_sgs]; 858 write_desc_llp(hw_desc, llp | lms); 859 llp = hw_desc->llp; 860 } while (num_sgs); 861 862 dw_axi_dma_set_hw_channel(chan, true); 863 864 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 865 866err_desc_get: 867 if (desc) 868 axi_desc_put(desc); 869 870 return NULL; 871} 872 873static struct dma_async_tx_descriptor * 874dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, 875 dma_addr_t src_adr, size_t len, unsigned long flags) 876{ 877 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 878 size_t block_ts, max_block_ts, xfer_len; 879 struct axi_dma_hw_desc *hw_desc = NULL; 880 struct axi_dma_desc *desc = NULL; 881 u32 xfer_width, reg, num; 882 u64 llp = 0; 883 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 884 885 dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", 886 axi_chan_name(chan), &src_adr, &dst_adr, len, flags); 887 888 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 889 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len); 890 num = DIV_ROUND_UP(len, max_block_ts << xfer_width); 891 desc = axi_desc_alloc(num); 892 if (unlikely(!desc)) 893 goto err_desc_get; 894 895 desc->chan = chan; 896 num = 0; 897 desc->length = 0; 898 while (len) { 899 xfer_len = len; 900 901 hw_desc = &desc->hw_desc[num]; 902 /* 903 * Take care for the alignment. 904 * Actually source and destination widths can be different, but 905 * make them same to be simpler. 906 */ 907 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len); 908 909 /* 910 * block_ts indicates the total number of data of width 911 * to be transferred in a DMA block transfer. 912 * BLOCK_TS register should be set to block_ts - 1 913 */ 914 block_ts = xfer_len >> xfer_width; 915 if (block_ts > max_block_ts) { 916 block_ts = max_block_ts; 917 xfer_len = max_block_ts << xfer_width; 918 } 919 920 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); 921 if (unlikely(!hw_desc->lli)) 922 goto err_desc_get; 923 924 write_desc_sar(hw_desc, src_adr); 925 write_desc_dar(hw_desc, dst_adr); 926 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); 927 928 reg = CH_CTL_H_LLI_VALID; 929 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 930 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 931 932 reg |= (CH_CTL_H_ARLEN_EN | 933 burst_len << CH_CTL_H_ARLEN_POS | 934 CH_CTL_H_AWLEN_EN | 935 burst_len << CH_CTL_H_AWLEN_POS); 936 } 937 hw_desc->lli->ctl_hi = cpu_to_le32(reg); 938 939 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 940 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | 941 xfer_width << CH_CTL_L_DST_WIDTH_POS | 942 xfer_width << CH_CTL_L_SRC_WIDTH_POS | 943 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 944 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS); 945 hw_desc->lli->ctl_lo = cpu_to_le32(reg); 946 947 set_desc_src_master(hw_desc); 948 set_desc_dest_master(hw_desc, desc); 949 950 hw_desc->len = xfer_len; 951 desc->length += hw_desc->len; 952 /* update the length and addresses for the next loop cycle */ 953 len -= xfer_len; 954 dst_adr += xfer_len; 955 src_adr += xfer_len; 956 num++; 957 } 958 959 /* Set end-of-link to the last link descriptor of list */ 960 set_desc_last(&desc->hw_desc[num - 1]); 961 /* Managed transfer list */ 962 do { 963 hw_desc = &desc->hw_desc[--num]; 964 write_desc_llp(hw_desc, llp | lms); 965 llp = hw_desc->llp; 966 } while (num); 967 968 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 969 970err_desc_get: 971 if (desc) 972 axi_desc_put(desc); 973 return NULL; 974} 975 976static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan, 977 struct dma_slave_config *config) 978{ 979 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 980 981 memcpy(&chan->config, config, sizeof(*config)); 982 983 return 0; 984} 985 986static void axi_chan_dump_lli(struct axi_dma_chan *chan, 987 struct axi_dma_hw_desc *desc) 988{ 989 if (!desc->lli) { 990 dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n"); 991 return; 992 } 993 994 dev_err(dchan2dev(&chan->vc.chan), 995 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x", 996 le64_to_cpu(desc->lli->sar), 997 le64_to_cpu(desc->lli->dar), 998 le64_to_cpu(desc->lli->llp), 999 le32_to_cpu(desc->lli->block_ts_lo), 1000 le32_to_cpu(desc->lli->ctl_hi), 1001 le32_to_cpu(desc->lli->ctl_lo)); 1002} 1003 1004static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, 1005 struct axi_dma_desc *desc_head) 1006{ 1007 int count = atomic_read(&chan->descs_allocated); 1008 int i; 1009 1010 for (i = 0; i < count; i++) 1011 axi_chan_dump_lli(chan, &desc_head->hw_desc[i]); 1012} 1013 1014static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) 1015{ 1016 struct virt_dma_desc *vd; 1017 unsigned long flags; 1018 1019 spin_lock_irqsave(&chan->vc.lock, flags); 1020 1021 axi_chan_disable(chan); 1022 1023 /* The bad descriptor currently is in the head of vc list */ 1024 vd = vchan_next_desc(&chan->vc); 1025 if (!vd) { 1026 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", 1027 axi_chan_name(chan)); 1028 goto out; 1029 } 1030 /* Remove the completed descriptor from issued list */ 1031 list_del(&vd->node); 1032 1033 /* WARN about bad descriptor */ 1034 dev_err(chan2dev(chan), 1035 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n", 1036 axi_chan_name(chan), vd->tx.cookie, status); 1037 axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd)); 1038 1039 vchan_cookie_complete(vd); 1040 1041 /* Try to restart the controller */ 1042 axi_chan_start_first_queued(chan); 1043 1044out: 1045 spin_unlock_irqrestore(&chan->vc.lock, flags); 1046} 1047 1048static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) 1049{ 1050 int count = atomic_read(&chan->descs_allocated); 1051 struct axi_dma_hw_desc *hw_desc; 1052 struct axi_dma_desc *desc; 1053 struct virt_dma_desc *vd; 1054 unsigned long flags; 1055 u64 llp; 1056 int i; 1057 1058 spin_lock_irqsave(&chan->vc.lock, flags); 1059 if (unlikely(axi_chan_is_hw_enable(chan))) { 1060 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n", 1061 axi_chan_name(chan)); 1062 axi_chan_disable(chan); 1063 } 1064 1065 /* The completed descriptor currently is in the head of vc list */ 1066 vd = vchan_next_desc(&chan->vc); 1067 if (!vd) { 1068 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", 1069 axi_chan_name(chan)); 1070 goto out; 1071 } 1072 1073 if (chan->cyclic) { 1074 desc = vd_to_axi_desc(vd); 1075 if (desc) { 1076 llp = lo_hi_readq(chan->chan_regs + CH_LLP); 1077 for (i = 0; i < count; i++) { 1078 hw_desc = &desc->hw_desc[i]; 1079 if (hw_desc->llp == llp) { 1080 axi_chan_irq_clear(chan, hw_desc->lli->status_lo); 1081 hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID; 1082 desc->completed_blocks = i; 1083 1084 if (((hw_desc->len * (i + 1)) % desc->period_len) == 0) 1085 vchan_cyclic_callback(vd); 1086 break; 1087 } 1088 } 1089 1090 axi_chan_enable(chan); 1091 } 1092 } else { 1093 /* Remove the completed descriptor from issued list before completing */ 1094 list_del(&vd->node); 1095 vchan_cookie_complete(vd); 1096 1097 /* Submit queued descriptors after processing the completed ones */ 1098 axi_chan_start_first_queued(chan); 1099 } 1100 1101out: 1102 spin_unlock_irqrestore(&chan->vc.lock, flags); 1103} 1104 1105static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id) 1106{ 1107 struct axi_dma_chip *chip = dev_id; 1108 struct dw_axi_dma *dw = chip->dw; 1109 struct axi_dma_chan *chan; 1110 1111 u32 status, i; 1112 1113 /* Disable DMAC interrupts. We'll enable them after processing channels */ 1114 axi_dma_irq_disable(chip); 1115 1116 /* Poll, clear and process every channel interrupt status */ 1117 for (i = 0; i < dw->hdata->nr_channels; i++) { 1118 chan = &dw->chan[i]; 1119 status = axi_chan_irq_read(chan); 1120 axi_chan_irq_clear(chan, status); 1121 1122 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n", 1123 axi_chan_name(chan), i, status); 1124 1125 if (status & DWAXIDMAC_IRQ_ALL_ERR) 1126 axi_chan_handle_err(chan, status); 1127 else if (status & DWAXIDMAC_IRQ_DMA_TRF) 1128 axi_chan_block_xfer_complete(chan); 1129 } 1130 1131 /* Re-enable interrupts */ 1132 axi_dma_irq_enable(chip); 1133 1134 return IRQ_HANDLED; 1135} 1136 1137static int dma_chan_terminate_all(struct dma_chan *dchan) 1138{ 1139 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1140 u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT; 1141 unsigned long flags; 1142 u32 val; 1143 int ret; 1144 LIST_HEAD(head); 1145 1146 axi_chan_disable(chan); 1147 1148 ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, 1149 !(val & chan_active), 1000, 50000); 1150 if (ret == -ETIMEDOUT) 1151 dev_warn(dchan2dev(dchan), 1152 "%s failed to stop\n", axi_chan_name(chan)); 1153 1154 if (chan->direction != DMA_MEM_TO_MEM) 1155 dw_axi_dma_set_hw_channel(chan, false); 1156 if (chan->direction == DMA_MEM_TO_DEV) 1157 dw_axi_dma_set_byte_halfword(chan, false); 1158 1159 spin_lock_irqsave(&chan->vc.lock, flags); 1160 1161 vchan_get_all_descriptors(&chan->vc, &head); 1162 1163 chan->cyclic = false; 1164 spin_unlock_irqrestore(&chan->vc.lock, flags); 1165 1166 vchan_dma_desc_free_list(&chan->vc, &head); 1167 1168 dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan)); 1169 1170 return 0; 1171} 1172 1173static int dma_chan_pause(struct dma_chan *dchan) 1174{ 1175 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1176 unsigned long flags; 1177 unsigned int timeout = 20; /* timeout iterations */ 1178 u32 val; 1179 1180 spin_lock_irqsave(&chan->vc.lock, flags); 1181 1182 if (chan->chip->dw->hdata->reg_map_8_channels) { 1183 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 1184 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | 1185 BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; 1186 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 1187 } else { 1188 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); 1189 val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | 1190 BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; 1191 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); 1192 } 1193 1194 do { 1195 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED) 1196 break; 1197 1198 udelay(2); 1199 } while (--timeout); 1200 1201 axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED); 1202 1203 chan->is_paused = true; 1204 1205 spin_unlock_irqrestore(&chan->vc.lock, flags); 1206 1207 return timeout ? 0 : -EAGAIN; 1208} 1209 1210/* Called in chan locked context */ 1211static inline void axi_chan_resume(struct axi_dma_chan *chan) 1212{ 1213 u32 val; 1214 1215 if (chan->chip->dw->hdata->reg_map_8_channels) { 1216 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 1217 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); 1218 val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); 1219 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 1220 } else { 1221 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); 1222 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); 1223 val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); 1224 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); 1225 } 1226 1227 chan->is_paused = false; 1228} 1229 1230static int dma_chan_resume(struct dma_chan *dchan) 1231{ 1232 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1233 unsigned long flags; 1234 1235 spin_lock_irqsave(&chan->vc.lock, flags); 1236 1237 if (chan->is_paused) 1238 axi_chan_resume(chan); 1239 1240 spin_unlock_irqrestore(&chan->vc.lock, flags); 1241 1242 return 0; 1243} 1244 1245static int axi_dma_suspend(struct axi_dma_chip *chip) 1246{ 1247 axi_dma_irq_disable(chip); 1248 axi_dma_disable(chip); 1249 1250 clk_disable_unprepare(chip->core_clk); 1251 clk_disable_unprepare(chip->cfgr_clk); 1252 1253 return 0; 1254} 1255 1256static int axi_dma_resume(struct axi_dma_chip *chip) 1257{ 1258 int ret; 1259 1260 ret = clk_prepare_enable(chip->cfgr_clk); 1261 if (ret < 0) 1262 return ret; 1263 1264 ret = clk_prepare_enable(chip->core_clk); 1265 if (ret < 0) 1266 return ret; 1267 1268 axi_dma_enable(chip); 1269 axi_dma_irq_enable(chip); 1270 1271 return 0; 1272} 1273 1274static int __maybe_unused axi_dma_runtime_suspend(struct device *dev) 1275{ 1276 struct axi_dma_chip *chip = dev_get_drvdata(dev); 1277 1278 return axi_dma_suspend(chip); 1279} 1280 1281static int __maybe_unused axi_dma_runtime_resume(struct device *dev) 1282{ 1283 struct axi_dma_chip *chip = dev_get_drvdata(dev); 1284 1285 return axi_dma_resume(chip); 1286} 1287 1288static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec, 1289 struct of_dma *ofdma) 1290{ 1291 struct dw_axi_dma *dw = ofdma->of_dma_data; 1292 struct axi_dma_chan *chan; 1293 struct dma_chan *dchan; 1294 1295 dchan = dma_get_any_slave_channel(&dw->dma); 1296 if (!dchan) 1297 return NULL; 1298 1299 chan = dchan_to_axi_dma_chan(dchan); 1300 chan->hw_handshake_num = dma_spec->args[0]; 1301 return dchan; 1302} 1303 1304static int parse_device_properties(struct axi_dma_chip *chip) 1305{ 1306 struct device *dev = chip->dev; 1307 u32 tmp, carr[DMAC_MAX_CHANNELS]; 1308 int ret; 1309 1310 ret = device_property_read_u32(dev, "dma-channels", &tmp); 1311 if (ret) 1312 return ret; 1313 if (tmp == 0 || tmp > DMAC_MAX_CHANNELS) 1314 return -EINVAL; 1315 1316 chip->dw->hdata->nr_channels = tmp; 1317 if (tmp <= DMA_REG_MAP_CH_REF) 1318 chip->dw->hdata->reg_map_8_channels = true; 1319 1320 ret = device_property_read_u32(dev, "snps,dma-masters", &tmp); 1321 if (ret) 1322 return ret; 1323 if (tmp == 0 || tmp > DMAC_MAX_MASTERS) 1324 return -EINVAL; 1325 1326 chip->dw->hdata->nr_masters = tmp; 1327 1328 ret = device_property_read_u32(dev, "snps,data-width", &tmp); 1329 if (ret) 1330 return ret; 1331 if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX) 1332 return -EINVAL; 1333 1334 chip->dw->hdata->m_data_width = tmp; 1335 1336 ret = device_property_read_u32_array(dev, "snps,block-size", carr, 1337 chip->dw->hdata->nr_channels); 1338 if (ret) 1339 return ret; 1340 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 1341 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE) 1342 return -EINVAL; 1343 1344 chip->dw->hdata->block_size[tmp] = carr[tmp]; 1345 } 1346 1347 ret = device_property_read_u32_array(dev, "snps,priority", carr, 1348 chip->dw->hdata->nr_channels); 1349 if (ret) 1350 return ret; 1351 /* Priority value must be programmed within [0:nr_channels-1] range */ 1352 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 1353 if (carr[tmp] >= chip->dw->hdata->nr_channels) 1354 return -EINVAL; 1355 1356 chip->dw->hdata->priority[tmp] = carr[tmp]; 1357 } 1358 1359 /* axi-max-burst-len is optional property */ 1360 ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp); 1361 if (!ret) { 1362 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1) 1363 return -EINVAL; 1364 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1) 1365 return -EINVAL; 1366 1367 chip->dw->hdata->restrict_axi_burst_len = true; 1368 chip->dw->hdata->axi_rw_burst_len = tmp; 1369 } 1370 1371 return 0; 1372} 1373 1374static int dw_probe(struct platform_device *pdev) 1375{ 1376 struct axi_dma_chip *chip; 1377 struct dw_axi_dma *dw; 1378 struct dw_axi_dma_hcfg *hdata; 1379 struct reset_control *resets; 1380 unsigned int flags; 1381 u32 i; 1382 int ret; 1383 1384 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1385 if (!chip) 1386 return -ENOMEM; 1387 1388 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); 1389 if (!dw) 1390 return -ENOMEM; 1391 1392 hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL); 1393 if (!hdata) 1394 return -ENOMEM; 1395 1396 chip->dw = dw; 1397 chip->dev = &pdev->dev; 1398 chip->dw->hdata = hdata; 1399 1400 chip->irq = platform_get_irq(pdev, 0); 1401 if (chip->irq < 0) 1402 return chip->irq; 1403 1404 chip->regs = devm_platform_ioremap_resource(pdev, 0); 1405 if (IS_ERR(chip->regs)) 1406 return PTR_ERR(chip->regs); 1407 1408 flags = (uintptr_t)of_device_get_match_data(&pdev->dev); 1409 if (flags & AXI_DMA_FLAG_HAS_APB_REGS) { 1410 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); 1411 if (IS_ERR(chip->apb_regs)) 1412 return PTR_ERR(chip->apb_regs); 1413 } 1414 1415 if (flags & AXI_DMA_FLAG_HAS_RESETS) { 1416 resets = devm_reset_control_array_get_exclusive(&pdev->dev); 1417 if (IS_ERR(resets)) 1418 return PTR_ERR(resets); 1419 1420 ret = reset_control_deassert(resets); 1421 if (ret) 1422 return ret; 1423 } 1424 1425 chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2); 1426 1427 chip->core_clk = devm_clk_get(chip->dev, "core-clk"); 1428 if (IS_ERR(chip->core_clk)) 1429 return PTR_ERR(chip->core_clk); 1430 1431 chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk"); 1432 if (IS_ERR(chip->cfgr_clk)) 1433 return PTR_ERR(chip->cfgr_clk); 1434 1435 ret = parse_device_properties(chip); 1436 if (ret) 1437 return ret; 1438 1439 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels, 1440 sizeof(*dw->chan), GFP_KERNEL); 1441 if (!dw->chan) 1442 return -ENOMEM; 1443 1444 ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt, 1445 IRQF_SHARED, KBUILD_MODNAME, chip); 1446 if (ret) 1447 return ret; 1448 1449 INIT_LIST_HEAD(&dw->dma.channels); 1450 for (i = 0; i < hdata->nr_channels; i++) { 1451 struct axi_dma_chan *chan = &dw->chan[i]; 1452 1453 chan->chip = chip; 1454 chan->id = i; 1455 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN; 1456 atomic_set(&chan->descs_allocated, 0); 1457 1458 chan->vc.desc_free = vchan_desc_put; 1459 vchan_init(&chan->vc, &dw->dma); 1460 } 1461 1462 /* Set capabilities */ 1463 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1464 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1465 dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask); 1466 1467 /* DMA capabilities */ 1468 dw->dma.max_burst = hdata->axi_rw_burst_len; 1469 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS; 1470 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS; 1471 dw->dma.directions = BIT(DMA_MEM_TO_MEM); 1472 dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 1473 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1474 1475 dw->dma.dev = chip->dev; 1476 dw->dma.device_tx_status = dma_chan_tx_status; 1477 dw->dma.device_issue_pending = dma_chan_issue_pending; 1478 dw->dma.device_terminate_all = dma_chan_terminate_all; 1479 dw->dma.device_pause = dma_chan_pause; 1480 dw->dma.device_resume = dma_chan_resume; 1481 1482 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources; 1483 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; 1484 1485 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; 1486 dw->dma.device_synchronize = dw_axi_dma_synchronize; 1487 dw->dma.device_config = dw_axi_dma_chan_slave_config; 1488 dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; 1489 dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; 1490 1491 /* 1492 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum 1493 * supported blocks is 1024. Device register width is 4 bytes. 1494 * Therefore, set constraint to 1024 * 4. 1495 */ 1496 dw->dma.dev->dma_parms = &dw->dma_parms; 1497 dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE); 1498 platform_set_drvdata(pdev, chip); 1499 1500 pm_runtime_enable(chip->dev); 1501 1502 /* 1503 * We can't just call pm_runtime_get here instead of 1504 * pm_runtime_get_noresume + axi_dma_resume because we need 1505 * driver to work also without Runtime PM. 1506 */ 1507 pm_runtime_get_noresume(chip->dev); 1508 ret = axi_dma_resume(chip); 1509 if (ret < 0) 1510 goto err_pm_disable; 1511 1512 axi_dma_hw_init(chip); 1513 1514 pm_runtime_put(chip->dev); 1515 1516 ret = dmaenginem_async_device_register(&dw->dma); 1517 if (ret) 1518 goto err_pm_disable; 1519 1520 /* Register with OF helpers for DMA lookups */ 1521 ret = of_dma_controller_register(pdev->dev.of_node, 1522 dw_axi_dma_of_xlate, dw); 1523 if (ret < 0) 1524 dev_warn(&pdev->dev, 1525 "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n"); 1526 1527 dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n", 1528 dw->hdata->nr_channels); 1529 1530 return 0; 1531 1532err_pm_disable: 1533 pm_runtime_disable(chip->dev); 1534 1535 return ret; 1536} 1537 1538static int dw_remove(struct platform_device *pdev) 1539{ 1540 struct axi_dma_chip *chip = platform_get_drvdata(pdev); 1541 struct dw_axi_dma *dw = chip->dw; 1542 struct axi_dma_chan *chan, *_chan; 1543 u32 i; 1544 1545 /* Enable clk before accessing to registers */ 1546 clk_prepare_enable(chip->cfgr_clk); 1547 clk_prepare_enable(chip->core_clk); 1548 axi_dma_irq_disable(chip); 1549 for (i = 0; i < dw->hdata->nr_channels; i++) { 1550 axi_chan_disable(&chip->dw->chan[i]); 1551 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 1552 } 1553 axi_dma_disable(chip); 1554 1555 pm_runtime_disable(chip->dev); 1556 axi_dma_suspend(chip); 1557 1558 devm_free_irq(chip->dev, chip->irq, chip); 1559 1560 of_dma_controller_free(chip->dev->of_node); 1561 1562 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, 1563 vc.chan.device_node) { 1564 list_del(&chan->vc.chan.device_node); 1565 tasklet_kill(&chan->vc.task); 1566 } 1567 1568 return 0; 1569} 1570 1571static const struct dev_pm_ops dw_axi_dma_pm_ops = { 1572 SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL) 1573}; 1574 1575static const struct of_device_id dw_dma_of_id_table[] = { 1576 { 1577 .compatible = "snps,axi-dma-1.01a" 1578 }, { 1579 .compatible = "intel,kmb-axi-dma", 1580 .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS, 1581 }, { 1582 .compatible = "starfive,jh7110-axi-dma", 1583 .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2), 1584 }, 1585 {} 1586}; 1587MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); 1588 1589static struct platform_driver dw_driver = { 1590 .probe = dw_probe, 1591 .remove = dw_remove, 1592 .driver = { 1593 .name = KBUILD_MODNAME, 1594 .of_match_table = dw_dma_of_id_table, 1595 .pm = &dw_axi_dma_pm_ops, 1596 }, 1597}; 1598module_platform_driver(dw_driver); 1599 1600MODULE_LICENSE("GPL v2"); 1601MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver"); 1602MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>"); 1603