1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright(c) 2021 Intel Corporation. All rights reserved. */ 3#include <linux/platform_device.h> 4#include <linux/module.h> 5#include <linux/device.h> 6#include <linux/kernel.h> 7#include <linux/acpi.h> 8#include <linux/pci.h> 9#include <asm/div64.h> 10#include "cxlpci.h" 11#include "cxl.h" 12 13#define CXL_RCRB_SIZE SZ_8K 14 15struct cxl_cxims_data { 16 int nr_maps; 17 u64 xormaps[] __counted_by(nr_maps); 18}; 19 20/* 21 * Find a targets entry (n) in the host bridge interleave list. 22 * CXL Specification 3.0 Table 9-22 23 */ 24static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw, 25 int ig) 26{ 27 int i = 0, n = 0; 28 u8 eiw; 29 30 /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */ 31 if (iw != 3) { 32 for (i = 0; i < cximsd->nr_maps; i++) 33 n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i; 34 } 35 /* IW: 3,6,12 add a modulo calculation to 'n' */ 36 if (!is_power_of_2(iw)) { 37 if (ways_to_eiw(iw, &eiw)) 38 return -1; 39 hpa &= GENMASK_ULL(51, eiw + ig); 40 n |= do_div(hpa, 3) << i; 41 } 42 return n; 43} 44 45static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos) 46{ 47 struct cxl_cxims_data *cximsd = cxlrd->platform_data; 48 struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd; 49 struct cxl_decoder *cxld = &cxlsd->cxld; 50 int ig = cxld->interleave_granularity; 51 int iw = cxld->interleave_ways; 52 int n = 0; 53 u64 hpa; 54 55 if (dev_WARN_ONCE(&cxld->dev, 56 cxld->interleave_ways != cxlsd->nr_targets, 57 "misconfigured root decoder\n")) 58 return NULL; 59 60 hpa = cxlrd->res->start + pos * ig; 61 62 /* Entry (n) is 0 for no interleave (iw == 1) */ 63 if (iw != 1) 64 n = cxl_xor_calc_n(hpa, cximsd, iw, ig); 65 66 if (n < 0) 67 return NULL; 68 69 return cxlrd->cxlsd.target[n]; 70} 71 72struct cxl_cxims_context { 73 struct device *dev; 74 struct cxl_root_decoder *cxlrd; 75}; 76 77static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg, 78 const unsigned long end) 79{ 80 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header; 81 struct cxl_cxims_context *ctx = arg; 82 struct cxl_root_decoder *cxlrd = ctx->cxlrd; 83 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld; 84 struct device *dev = ctx->dev; 85 struct cxl_cxims_data *cximsd; 86 unsigned int hbig, nr_maps; 87 int rc; 88 89 rc = eig_to_granularity(cxims->hbig, &hbig); 90 if (rc) 91 return rc; 92 93 /* Does this CXIMS entry apply to the given CXL Window? */ 94 if (hbig != cxld->interleave_granularity) 95 return 0; 96 97 /* IW 1,3 do not use xormaps and skip this parsing entirely */ 98 if (is_power_of_2(cxld->interleave_ways)) 99 /* 2, 4, 8, 16 way */ 100 nr_maps = ilog2(cxld->interleave_ways); 101 else 102 /* 6, 12 way */ 103 nr_maps = ilog2(cxld->interleave_ways / 3); 104 105 if (cxims->nr_xormaps < nr_maps) { 106 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n", 107 cxims->nr_xormaps, nr_maps); 108 return -ENXIO; 109 } 110 111 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps), 112 GFP_KERNEL); 113 if (!cximsd) 114 return -ENOMEM; 115 cximsd->nr_maps = nr_maps; 116 memcpy(cximsd->xormaps, cxims->xormap_list, 117 nr_maps * sizeof(*cximsd->xormaps)); 118 cxlrd->platform_data = cximsd; 119 120 return 0; 121} 122 123static unsigned long cfmws_to_decoder_flags(int restrictions) 124{ 125 unsigned long flags = CXL_DECODER_F_ENABLE; 126 127 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) 128 flags |= CXL_DECODER_F_TYPE2; 129 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) 130 flags |= CXL_DECODER_F_TYPE3; 131 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) 132 flags |= CXL_DECODER_F_RAM; 133 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) 134 flags |= CXL_DECODER_F_PMEM; 135 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) 136 flags |= CXL_DECODER_F_LOCK; 137 138 return flags; 139} 140 141static int cxl_acpi_cfmws_verify(struct device *dev, 142 struct acpi_cedt_cfmws *cfmws) 143{ 144 int rc, expected_len; 145 unsigned int ways; 146 147 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO && 148 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) { 149 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n", 150 cfmws->interleave_arithmetic); 151 return -EINVAL; 152 } 153 154 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { 155 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); 156 return -EINVAL; 157 } 158 159 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { 160 dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); 161 return -EINVAL; 162 } 163 164 rc = eiw_to_ways(cfmws->interleave_ways, &ways); 165 if (rc) { 166 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n", 167 cfmws->interleave_ways); 168 return -EINVAL; 169 } 170 171 expected_len = struct_size(cfmws, interleave_targets, ways); 172 173 if (cfmws->header.length < expected_len) { 174 dev_err(dev, "CFMWS length %d less than expected %d\n", 175 cfmws->header.length, expected_len); 176 return -EINVAL; 177 } 178 179 if (cfmws->header.length > expected_len) 180 dev_dbg(dev, "CFMWS length %d greater than expected %d\n", 181 cfmws->header.length, expected_len); 182 183 return 0; 184} 185 186/* 187 * Note, @dev must be the first member, see 'struct cxl_chbs_context' 188 * and mock_acpi_table_parse_cedt() 189 */ 190struct cxl_cfmws_context { 191 struct device *dev; 192 struct cxl_port *root_port; 193 struct resource *cxl_res; 194 int id; 195}; 196 197static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, 198 struct cxl_cfmws_context *ctx) 199{ 200 int target_map[CXL_DECODER_MAX_INTERLEAVE]; 201 struct cxl_port *root_port = ctx->root_port; 202 struct resource *cxl_res = ctx->cxl_res; 203 struct cxl_cxims_context cxims_ctx; 204 struct cxl_root_decoder *cxlrd; 205 struct device *dev = ctx->dev; 206 cxl_calc_hb_fn cxl_calc_hb; 207 struct cxl_decoder *cxld; 208 unsigned int ways, i, ig; 209 struct resource *res; 210 int rc; 211 212 rc = cxl_acpi_cfmws_verify(dev, cfmws); 213 if (rc) { 214 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", 215 cfmws->base_hpa, 216 cfmws->base_hpa + cfmws->window_size - 1); 217 return rc; 218 } 219 220 rc = eiw_to_ways(cfmws->interleave_ways, &ways); 221 if (rc) 222 return rc; 223 rc = eig_to_granularity(cfmws->granularity, &ig); 224 if (rc) 225 return rc; 226 for (i = 0; i < ways; i++) 227 target_map[i] = cfmws->interleave_targets[i]; 228 229 res = kzalloc(sizeof(*res), GFP_KERNEL); 230 if (!res) 231 return -ENOMEM; 232 233 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++); 234 if (!res->name) 235 goto err_name; 236 237 res->start = cfmws->base_hpa; 238 res->end = cfmws->base_hpa + cfmws->window_size - 1; 239 res->flags = IORESOURCE_MEM; 240 241 /* add to the local resource tracking to establish a sort order */ 242 rc = insert_resource(cxl_res, res); 243 if (rc) 244 goto err_insert; 245 246 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) 247 cxl_calc_hb = cxl_hb_modulo; 248 else 249 cxl_calc_hb = cxl_hb_xor; 250 251 cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb); 252 if (IS_ERR(cxlrd)) 253 return PTR_ERR(cxlrd); 254 255 cxld = &cxlrd->cxlsd.cxld; 256 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions); 257 cxld->target_type = CXL_DECODER_HOSTONLYMEM; 258 cxld->hpa_range = (struct range) { 259 .start = res->start, 260 .end = res->end, 261 }; 262 cxld->interleave_ways = ways; 263 /* 264 * Minimize the x1 granularity to advertise support for any 265 * valid region granularity 266 */ 267 if (ways == 1) 268 ig = CXL_DECODER_MIN_GRANULARITY; 269 cxld->interleave_granularity = ig; 270 271 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) { 272 if (ways != 1 && ways != 3) { 273 cxims_ctx = (struct cxl_cxims_context) { 274 .dev = dev, 275 .cxlrd = cxlrd, 276 }; 277 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS, 278 cxl_parse_cxims, &cxims_ctx); 279 if (rc < 0) 280 goto err_xormap; 281 if (!cxlrd->platform_data) { 282 dev_err(dev, "No CXIMS for HBIG %u\n", ig); 283 rc = -EINVAL; 284 goto err_xormap; 285 } 286 } 287 } 288 rc = cxl_decoder_add(cxld, target_map); 289err_xormap: 290 if (rc) 291 put_device(&cxld->dev); 292 else 293 rc = cxl_decoder_autoremove(dev, cxld); 294 return rc; 295 296err_insert: 297 kfree(res->name); 298err_name: 299 kfree(res); 300 return -ENOMEM; 301} 302 303static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, 304 const unsigned long end) 305{ 306 struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header; 307 struct cxl_cfmws_context *ctx = arg; 308 struct device *dev = ctx->dev; 309 int rc; 310 311 rc = __cxl_parse_cfmws(cfmws, ctx); 312 if (rc) 313 dev_err(dev, 314 "Failed to add decode range: [%#llx - %#llx] (%d)\n", 315 cfmws->base_hpa, 316 cfmws->base_hpa + cfmws->window_size - 1, rc); 317 else 318 dev_dbg(dev, "decode range: node: %d range [%#llx - %#llx]\n", 319 phys_to_target_node(cfmws->base_hpa), cfmws->base_hpa, 320 cfmws->base_hpa + cfmws->window_size - 1); 321 322 /* never fail cxl_acpi load for a single window failure */ 323 return 0; 324} 325 326__mock struct acpi_device *to_cxl_host_bridge(struct device *host, 327 struct device *dev) 328{ 329 struct acpi_device *adev = to_acpi_device(dev); 330 331 if (!acpi_pci_find_root(adev->handle)) 332 return NULL; 333 334 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0) 335 return adev; 336 return NULL; 337} 338 339/* Note, @dev is used by mock_acpi_table_parse_cedt() */ 340struct cxl_chbs_context { 341 struct device *dev; 342 unsigned long long uid; 343 resource_size_t base; 344 u32 cxl_version; 345}; 346 347static int cxl_get_chbs_iter(union acpi_subtable_headers *header, void *arg, 348 const unsigned long end) 349{ 350 struct cxl_chbs_context *ctx = arg; 351 struct acpi_cedt_chbs *chbs; 352 353 if (ctx->base != CXL_RESOURCE_NONE) 354 return 0; 355 356 chbs = (struct acpi_cedt_chbs *) header; 357 358 if (ctx->uid != chbs->uid) 359 return 0; 360 361 ctx->cxl_version = chbs->cxl_version; 362 if (!chbs->base) 363 return 0; 364 365 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 && 366 chbs->length != CXL_RCRB_SIZE) 367 return 0; 368 369 ctx->base = chbs->base; 370 371 return 0; 372} 373 374static int cxl_get_chbs(struct device *dev, struct acpi_device *hb, 375 struct cxl_chbs_context *ctx) 376{ 377 unsigned long long uid; 378 int rc; 379 380 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid); 381 if (rc != AE_OK) { 382 dev_err(dev, "unable to retrieve _UID\n"); 383 return -ENOENT; 384 } 385 386 dev_dbg(dev, "UID found: %lld\n", uid); 387 *ctx = (struct cxl_chbs_context) { 388 .dev = dev, 389 .uid = uid, 390 .base = CXL_RESOURCE_NONE, 391 .cxl_version = UINT_MAX, 392 }; 393 394 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs_iter, ctx); 395 396 return 0; 397} 398 399static int add_host_bridge_dport(struct device *match, void *arg) 400{ 401 acpi_status rc; 402 struct device *bridge; 403 struct cxl_dport *dport; 404 struct cxl_chbs_context ctx; 405 struct acpi_pci_root *pci_root; 406 struct cxl_port *root_port = arg; 407 struct device *host = root_port->dev.parent; 408 struct acpi_device *hb = to_cxl_host_bridge(host, match); 409 410 if (!hb) 411 return 0; 412 413 rc = cxl_get_chbs(match, hb, &ctx); 414 if (rc) 415 return rc; 416 417 if (ctx.cxl_version == UINT_MAX) { 418 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n", 419 ctx.uid); 420 return 0; 421 } 422 423 if (ctx.base == CXL_RESOURCE_NONE) { 424 dev_warn(match, "CHBS invalid for Host Bridge (UID %lld)\n", 425 ctx.uid); 426 return 0; 427 } 428 429 pci_root = acpi_pci_find_root(hb->handle); 430 bridge = pci_root->bus->bridge; 431 432 /* 433 * In RCH mode, bind the component regs base to the dport. In 434 * VH mode it will be bound to the CXL host bridge's port 435 * object later in add_host_bridge_uport(). 436 */ 437 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) { 438 dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid, 439 &ctx.base); 440 dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid, 441 ctx.base); 442 } else { 443 dport = devm_cxl_add_dport(root_port, bridge, ctx.uid, 444 CXL_RESOURCE_NONE); 445 } 446 447 if (IS_ERR(dport)) 448 return PTR_ERR(dport); 449 450 return 0; 451} 452 453/* 454 * A host bridge is a dport to a CFMWS decode and it is a uport to the 455 * dport (PCIe Root Ports) in the host bridge. 456 */ 457static int add_host_bridge_uport(struct device *match, void *arg) 458{ 459 struct cxl_port *root_port = arg; 460 struct device *host = root_port->dev.parent; 461 struct acpi_device *hb = to_cxl_host_bridge(host, match); 462 struct acpi_pci_root *pci_root; 463 struct cxl_dport *dport; 464 struct cxl_port *port; 465 struct device *bridge; 466 struct cxl_chbs_context ctx; 467 resource_size_t component_reg_phys; 468 int rc; 469 470 if (!hb) 471 return 0; 472 473 pci_root = acpi_pci_find_root(hb->handle); 474 bridge = pci_root->bus->bridge; 475 dport = cxl_find_dport_by_dev(root_port, bridge); 476 if (!dport) { 477 dev_dbg(host, "host bridge expected and not found\n"); 478 return 0; 479 } 480 481 if (dport->rch) { 482 dev_info(bridge, "host supports CXL (restricted)\n"); 483 return 0; 484 } 485 486 rc = cxl_get_chbs(match, hb, &ctx); 487 if (rc) 488 return rc; 489 490 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) { 491 dev_warn(bridge, 492 "CXL CHBS version mismatch, skip port registration\n"); 493 return 0; 494 } 495 496 component_reg_phys = ctx.base; 497 if (component_reg_phys != CXL_RESOURCE_NONE) 498 dev_dbg(match, "CHBCR found for UID %lld: %pa\n", 499 ctx.uid, &component_reg_phys); 500 501 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus); 502 if (rc) 503 return rc; 504 505 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport); 506 if (IS_ERR(port)) 507 return PTR_ERR(port); 508 509 dev_info(bridge, "host supports CXL\n"); 510 511 return 0; 512} 513 514static int add_root_nvdimm_bridge(struct device *match, void *data) 515{ 516 struct cxl_decoder *cxld; 517 struct cxl_port *root_port = data; 518 struct cxl_nvdimm_bridge *cxl_nvb; 519 struct device *host = root_port->dev.parent; 520 521 if (!is_root_decoder(match)) 522 return 0; 523 524 cxld = to_cxl_decoder(match); 525 if (!(cxld->flags & CXL_DECODER_F_PMEM)) 526 return 0; 527 528 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port); 529 if (IS_ERR(cxl_nvb)) { 530 dev_dbg(host, "failed to register pmem\n"); 531 return PTR_ERR(cxl_nvb); 532 } 533 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev), 534 dev_name(&cxl_nvb->dev)); 535 return 1; 536} 537 538static struct lock_class_key cxl_root_key; 539 540static void cxl_acpi_lock_reset_class(void *dev) 541{ 542 device_lock_reset_class(dev); 543} 544 545static void del_cxl_resource(struct resource *res) 546{ 547 kfree(res->name); 548 kfree(res); 549} 550 551static void cxl_set_public_resource(struct resource *priv, struct resource *pub) 552{ 553 priv->desc = (unsigned long) pub; 554} 555 556static struct resource *cxl_get_public_resource(struct resource *priv) 557{ 558 return (struct resource *) priv->desc; 559} 560 561static void remove_cxl_resources(void *data) 562{ 563 struct resource *res, *next, *cxl = data; 564 565 for (res = cxl->child; res; res = next) { 566 struct resource *victim = cxl_get_public_resource(res); 567 568 next = res->sibling; 569 remove_resource(res); 570 571 if (victim) { 572 remove_resource(victim); 573 kfree(victim); 574 } 575 576 del_cxl_resource(res); 577 } 578} 579 580/** 581 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource 582 * @cxl_res: A standalone resource tree where each CXL window is a sibling 583 * 584 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially 585 * expanding its boundaries to ensure that any conflicting resources become 586 * children. If a window is expanded it may then conflict with a another window 587 * entry and require the window to be truncated or trimmed. Consider this 588 * situation: 589 * 590 * |-- "CXL Window 0" --||----- "CXL Window 1" -----| 591 * |--------------- "System RAM" -------------| 592 * 593 * ...where platform firmware has established as System RAM resource across 2 594 * windows, but has left some portion of window 1 for dynamic CXL region 595 * provisioning. In this case "Window 0" will span the entirety of the "System 596 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end 597 * of that "System RAM" resource. 598 */ 599static int add_cxl_resources(struct resource *cxl_res) 600{ 601 struct resource *res, *new, *next; 602 603 for (res = cxl_res->child; res; res = next) { 604 new = kzalloc(sizeof(*new), GFP_KERNEL); 605 if (!new) 606 return -ENOMEM; 607 new->name = res->name; 608 new->start = res->start; 609 new->end = res->end; 610 new->flags = IORESOURCE_MEM; 611 new->desc = IORES_DESC_CXL; 612 613 /* 614 * Record the public resource in the private cxl_res tree for 615 * later removal. 616 */ 617 cxl_set_public_resource(res, new); 618 619 insert_resource_expand_to_fit(&iomem_resource, new); 620 621 next = res->sibling; 622 while (next && resource_overlaps(new, next)) { 623 if (resource_contains(new, next)) { 624 struct resource *_next = next->sibling; 625 626 remove_resource(next); 627 del_cxl_resource(next); 628 next = _next; 629 } else 630 next->start = new->end + 1; 631 } 632 } 633 return 0; 634} 635 636static int pair_cxl_resource(struct device *dev, void *data) 637{ 638 struct resource *cxl_res = data; 639 struct resource *p; 640 641 if (!is_root_decoder(dev)) 642 return 0; 643 644 for (p = cxl_res->child; p; p = p->sibling) { 645 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev); 646 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld; 647 struct resource res = { 648 .start = cxld->hpa_range.start, 649 .end = cxld->hpa_range.end, 650 .flags = IORESOURCE_MEM, 651 }; 652 653 if (resource_contains(p, &res)) { 654 cxlrd->res = cxl_get_public_resource(p); 655 break; 656 } 657 } 658 659 return 0; 660} 661 662static int cxl_acpi_probe(struct platform_device *pdev) 663{ 664 int rc; 665 struct resource *cxl_res; 666 struct cxl_port *root_port; 667 struct device *host = &pdev->dev; 668 struct acpi_device *adev = ACPI_COMPANION(host); 669 struct cxl_cfmws_context ctx; 670 671 device_lock_set_class(&pdev->dev, &cxl_root_key); 672 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class, 673 &pdev->dev); 674 if (rc) 675 return rc; 676 677 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL); 678 if (!cxl_res) 679 return -ENOMEM; 680 cxl_res->name = "CXL mem"; 681 cxl_res->start = 0; 682 cxl_res->end = -1; 683 cxl_res->flags = IORESOURCE_MEM; 684 685 root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); 686 if (IS_ERR(root_port)) 687 return PTR_ERR(root_port); 688 689 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, 690 add_host_bridge_dport); 691 if (rc < 0) 692 return rc; 693 694 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res); 695 if (rc) 696 return rc; 697 698 ctx = (struct cxl_cfmws_context) { 699 .dev = host, 700 .root_port = root_port, 701 .cxl_res = cxl_res, 702 }; 703 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx); 704 if (rc < 0) 705 return -ENXIO; 706 707 rc = add_cxl_resources(cxl_res); 708 if (rc) 709 return rc; 710 711 /* 712 * Populate the root decoders with their related iomem resource, 713 * if present 714 */ 715 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource); 716 717 /* 718 * Root level scanned with host-bridge as dports, now scan host-bridges 719 * for their role as CXL uports to their CXL-capable PCIe Root Ports. 720 */ 721 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, 722 add_host_bridge_uport); 723 if (rc < 0) 724 return rc; 725 726 if (IS_ENABLED(CONFIG_CXL_PMEM)) 727 rc = device_for_each_child(&root_port->dev, root_port, 728 add_root_nvdimm_bridge); 729 if (rc < 0) 730 return rc; 731 732 /* In case PCI is scanned before ACPI re-trigger memdev attach */ 733 cxl_bus_rescan(); 734 return 0; 735} 736 737static const struct acpi_device_id cxl_acpi_ids[] = { 738 { "ACPI0017" }, 739 { }, 740}; 741MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids); 742 743static const struct platform_device_id cxl_test_ids[] = { 744 { "cxl_acpi" }, 745 { }, 746}; 747MODULE_DEVICE_TABLE(platform, cxl_test_ids); 748 749static struct platform_driver cxl_acpi_driver = { 750 .probe = cxl_acpi_probe, 751 .driver = { 752 .name = KBUILD_MODNAME, 753 .acpi_match_table = cxl_acpi_ids, 754 }, 755 .id_table = cxl_test_ids, 756}; 757 758static int __init cxl_acpi_init(void) 759{ 760 return platform_driver_register(&cxl_acpi_driver); 761} 762 763static void __exit cxl_acpi_exit(void) 764{ 765 platform_driver_unregister(&cxl_acpi_driver); 766 cxl_bus_drain(); 767} 768 769/* load before dax_hmem sees 'Soft Reserved' CXL ranges */ 770subsys_initcall(cxl_acpi_init); 771module_exit(cxl_acpi_exit); 772MODULE_LICENSE("GPL v2"); 773MODULE_IMPORT_NS(CXL); 774MODULE_IMPORT_NS(ACPI); 775