1// SPDX-License-Identifier: GPL-2.0 2// 3// Cryptographic API. 4// 5// Support for Samsung S5PV210 and Exynos HW acceleration. 6// 7// Copyright (C) 2011 NetUP Inc. All rights reserved. 8// Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved. 9// 10// Hash part based on omap-sham.c driver. 11 12#include <linux/clk.h> 13#include <linux/crypto.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/errno.h> 17#include <linux/init.h> 18#include <linux/interrupt.h> 19#include <linux/io.h> 20#include <linux/kernel.h> 21#include <linux/module.h> 22#include <linux/of.h> 23#include <linux/platform_device.h> 24#include <linux/scatterlist.h> 25 26#include <crypto/ctr.h> 27#include <crypto/aes.h> 28#include <crypto/algapi.h> 29#include <crypto/scatterwalk.h> 30 31#include <crypto/hash.h> 32#include <crypto/md5.h> 33#include <crypto/sha1.h> 34#include <crypto/sha2.h> 35#include <crypto/internal/hash.h> 36 37#define _SBF(s, v) ((v) << (s)) 38 39/* Feed control registers */ 40#define SSS_REG_FCINTSTAT 0x0000 41#define SSS_FCINTSTAT_HPARTINT BIT(7) 42#define SSS_FCINTSTAT_HDONEINT BIT(5) 43#define SSS_FCINTSTAT_BRDMAINT BIT(3) 44#define SSS_FCINTSTAT_BTDMAINT BIT(2) 45#define SSS_FCINTSTAT_HRDMAINT BIT(1) 46#define SSS_FCINTSTAT_PKDMAINT BIT(0) 47 48#define SSS_REG_FCINTENSET 0x0004 49#define SSS_FCINTENSET_HPARTINTENSET BIT(7) 50#define SSS_FCINTENSET_HDONEINTENSET BIT(5) 51#define SSS_FCINTENSET_BRDMAINTENSET BIT(3) 52#define SSS_FCINTENSET_BTDMAINTENSET BIT(2) 53#define SSS_FCINTENSET_HRDMAINTENSET BIT(1) 54#define SSS_FCINTENSET_PKDMAINTENSET BIT(0) 55 56#define SSS_REG_FCINTENCLR 0x0008 57#define SSS_FCINTENCLR_HPARTINTENCLR BIT(7) 58#define SSS_FCINTENCLR_HDONEINTENCLR BIT(5) 59#define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) 60#define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) 61#define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) 62#define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) 63 64#define SSS_REG_FCINTPEND 0x000C 65#define SSS_FCINTPEND_HPARTINTP BIT(7) 66#define SSS_FCINTPEND_HDONEINTP BIT(5) 67#define SSS_FCINTPEND_BRDMAINTP BIT(3) 68#define SSS_FCINTPEND_BTDMAINTP BIT(2) 69#define SSS_FCINTPEND_HRDMAINTP BIT(1) 70#define SSS_FCINTPEND_PKDMAINTP BIT(0) 71 72#define SSS_REG_FCFIFOSTAT 0x0010 73#define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) 74#define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) 75#define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) 76#define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) 77#define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) 78#define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) 79#define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) 80#define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) 81 82#define SSS_REG_FCFIFOCTRL 0x0014 83#define SSS_FCFIFOCTRL_DESSEL BIT(2) 84#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) 85#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) 86#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) 87#define SSS_HASHIN_MASK _SBF(0, 0x03) 88 89#define SSS_REG_FCBRDMAS 0x0020 90#define SSS_REG_FCBRDMAL 0x0024 91#define SSS_REG_FCBRDMAC 0x0028 92#define SSS_FCBRDMAC_BYTESWAP BIT(1) 93#define SSS_FCBRDMAC_FLUSH BIT(0) 94 95#define SSS_REG_FCBTDMAS 0x0030 96#define SSS_REG_FCBTDMAL 0x0034 97#define SSS_REG_FCBTDMAC 0x0038 98#define SSS_FCBTDMAC_BYTESWAP BIT(1) 99#define SSS_FCBTDMAC_FLUSH BIT(0) 100 101#define SSS_REG_FCHRDMAS 0x0040 102#define SSS_REG_FCHRDMAL 0x0044 103#define SSS_REG_FCHRDMAC 0x0048 104#define SSS_FCHRDMAC_BYTESWAP BIT(1) 105#define SSS_FCHRDMAC_FLUSH BIT(0) 106 107#define SSS_REG_FCPKDMAS 0x0050 108#define SSS_REG_FCPKDMAL 0x0054 109#define SSS_REG_FCPKDMAC 0x0058 110#define SSS_FCPKDMAC_BYTESWAP BIT(3) 111#define SSS_FCPKDMAC_DESCEND BIT(2) 112#define SSS_FCPKDMAC_TRANSMIT BIT(1) 113#define SSS_FCPKDMAC_FLUSH BIT(0) 114 115#define SSS_REG_FCPKDMAO 0x005C 116 117/* AES registers */ 118#define SSS_REG_AES_CONTROL 0x00 119#define SSS_AES_BYTESWAP_DI BIT(11) 120#define SSS_AES_BYTESWAP_DO BIT(10) 121#define SSS_AES_BYTESWAP_IV BIT(9) 122#define SSS_AES_BYTESWAP_CNT BIT(8) 123#define SSS_AES_BYTESWAP_KEY BIT(7) 124#define SSS_AES_KEY_CHANGE_MODE BIT(6) 125#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) 126#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) 127#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) 128#define SSS_AES_FIFO_MODE BIT(3) 129#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) 130#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) 131#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) 132#define SSS_AES_MODE_DECRYPT BIT(0) 133 134#define SSS_REG_AES_STATUS 0x04 135#define SSS_AES_BUSY BIT(2) 136#define SSS_AES_INPUT_READY BIT(1) 137#define SSS_AES_OUTPUT_READY BIT(0) 138 139#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) 140#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) 141#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2)) 142#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) 143#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) 144 145#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) 146#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) 147#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) 148 149#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) 150#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ 151 SSS_AES_REG(dev, reg)) 152 153/* HW engine modes */ 154#define FLAGS_AES_DECRYPT BIT(0) 155#define FLAGS_AES_MODE_MASK _SBF(1, 0x03) 156#define FLAGS_AES_CBC _SBF(1, 0x01) 157#define FLAGS_AES_CTR _SBF(1, 0x02) 158 159#define AES_KEY_LEN 16 160#define CRYPTO_QUEUE_LEN 1 161 162/* HASH registers */ 163#define SSS_REG_HASH_CTRL 0x00 164 165#define SSS_HASH_USER_IV_EN BIT(5) 166#define SSS_HASH_INIT_BIT BIT(4) 167#define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00) 168#define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01) 169#define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02) 170 171#define SSS_HASH_ENGINE_MASK _SBF(1, 0x03) 172 173#define SSS_REG_HASH_CTRL_PAUSE 0x04 174 175#define SSS_HASH_PAUSE BIT(0) 176 177#define SSS_REG_HASH_CTRL_FIFO 0x08 178 179#define SSS_HASH_FIFO_MODE_DMA BIT(0) 180#define SSS_HASH_FIFO_MODE_CPU 0 181 182#define SSS_REG_HASH_CTRL_SWAP 0x0C 183 184#define SSS_HASH_BYTESWAP_DI BIT(3) 185#define SSS_HASH_BYTESWAP_DO BIT(2) 186#define SSS_HASH_BYTESWAP_IV BIT(1) 187#define SSS_HASH_BYTESWAP_KEY BIT(0) 188 189#define SSS_REG_HASH_STATUS 0x10 190 191#define SSS_HASH_STATUS_MSG_DONE BIT(6) 192#define SSS_HASH_STATUS_PARTIAL_DONE BIT(4) 193#define SSS_HASH_STATUS_BUFFER_READY BIT(0) 194 195#define SSS_REG_HASH_MSG_SIZE_LOW 0x20 196#define SSS_REG_HASH_MSG_SIZE_HIGH 0x24 197 198#define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28 199#define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C 200 201#define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2)) 202#define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2)) 203 204#define HASH_BLOCK_SIZE 64 205#define HASH_REG_SIZEOF 4 206#define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF) 207#define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF) 208#define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF) 209 210/* 211 * HASH bit numbers, used by device, setting in dev->hash_flags with 212 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(), 213 * to keep HASH state BUSY or FREE, or to signal state from irq_handler 214 * to hash_tasklet. SGS keep track of allocated memory for scatterlist 215 */ 216#define HASH_FLAGS_BUSY 0 217#define HASH_FLAGS_FINAL 1 218#define HASH_FLAGS_DMA_ACTIVE 2 219#define HASH_FLAGS_OUTPUT_READY 3 220#define HASH_FLAGS_DMA_READY 4 221#define HASH_FLAGS_SGS_COPIED 5 222#define HASH_FLAGS_SGS_ALLOCED 6 223 224/* HASH HW constants */ 225#define BUFLEN HASH_BLOCK_SIZE 226 227#define SSS_HASH_DMA_LEN_ALIGN 8 228#define SSS_HASH_DMA_ALIGN_MASK (SSS_HASH_DMA_LEN_ALIGN - 1) 229 230#define SSS_HASH_QUEUE_LENGTH 10 231 232/** 233 * struct samsung_aes_variant - platform specific SSS driver data 234 * @aes_offset: AES register offset from SSS module's base. 235 * @hash_offset: HASH register offset from SSS module's base. 236 * @clk_names: names of clocks needed to run SSS IP 237 * 238 * Specifies platform specific configuration of SSS module. 239 * Note: A structure for driver specific platform data is used for future 240 * expansion of its usage. 241 */ 242struct samsung_aes_variant { 243 unsigned int aes_offset; 244 unsigned int hash_offset; 245 const char *clk_names[2]; 246}; 247 248struct s5p_aes_reqctx { 249 unsigned long mode; 250}; 251 252struct s5p_aes_ctx { 253 struct s5p_aes_dev *dev; 254 255 u8 aes_key[AES_MAX_KEY_SIZE]; 256 u8 nonce[CTR_RFC3686_NONCE_SIZE]; 257 int keylen; 258}; 259 260/** 261 * struct s5p_aes_dev - Crypto device state container 262 * @dev: Associated device 263 * @clk: Clock for accessing hardware 264 * @pclk: APB bus clock necessary to access the hardware 265 * @ioaddr: Mapped IO memory region 266 * @aes_ioaddr: Per-varian offset for AES block IO memory 267 * @irq_fc: Feed control interrupt line 268 * @req: Crypto request currently handled by the device 269 * @ctx: Configuration for currently handled crypto request 270 * @sg_src: Scatter list with source data for currently handled block 271 * in device. This is DMA-mapped into device. 272 * @sg_dst: Scatter list with destination data for currently handled block 273 * in device. This is DMA-mapped into device. 274 * @sg_src_cpy: In case of unaligned access, copied scatter list 275 * with source data. 276 * @sg_dst_cpy: In case of unaligned access, copied scatter list 277 * with destination data. 278 * @tasklet: New request scheduling jib 279 * @queue: Crypto queue 280 * @busy: Indicates whether the device is currently handling some request 281 * thus it uses some of the fields from this state, like: 282 * req, ctx, sg_src/dst (and copies). This essentially 283 * protects against concurrent access to these fields. 284 * @lock: Lock for protecting both access to device hardware registers 285 * and fields related to current request (including the busy field). 286 * @res: Resources for hash. 287 * @io_hash_base: Per-variant offset for HASH block IO memory. 288 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags 289 * variable. 290 * @hash_flags: Flags for current HASH op. 291 * @hash_queue: Async hash queue. 292 * @hash_tasklet: New HASH request scheduling job. 293 * @xmit_buf: Buffer for current HASH request transfer into SSS block. 294 * @hash_req: Current request sending to SSS HASH block. 295 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block. 296 * @hash_sg_cnt: Counter for hash_sg_iter. 297 * 298 * @use_hash: true if HASH algs enabled 299 */ 300struct s5p_aes_dev { 301 struct device *dev; 302 struct clk *clk; 303 struct clk *pclk; 304 void __iomem *ioaddr; 305 void __iomem *aes_ioaddr; 306 int irq_fc; 307 308 struct skcipher_request *req; 309 struct s5p_aes_ctx *ctx; 310 struct scatterlist *sg_src; 311 struct scatterlist *sg_dst; 312 313 struct scatterlist *sg_src_cpy; 314 struct scatterlist *sg_dst_cpy; 315 316 struct tasklet_struct tasklet; 317 struct crypto_queue queue; 318 bool busy; 319 spinlock_t lock; 320 321 struct resource *res; 322 void __iomem *io_hash_base; 323 324 spinlock_t hash_lock; /* protect hash_ vars */ 325 unsigned long hash_flags; 326 struct crypto_queue hash_queue; 327 struct tasklet_struct hash_tasklet; 328 329 u8 xmit_buf[BUFLEN]; 330 struct ahash_request *hash_req; 331 struct scatterlist *hash_sg_iter; 332 unsigned int hash_sg_cnt; 333 334 bool use_hash; 335}; 336 337/** 338 * struct s5p_hash_reqctx - HASH request context 339 * @dd: Associated device 340 * @op_update: Current request operation (OP_UPDATE or OP_FINAL) 341 * @digcnt: Number of bytes processed by HW (without buffer[] ones) 342 * @digest: Digest message or IV for partial result 343 * @nregs: Number of HW registers for digest or IV read/write 344 * @engine: Bits for selecting type of HASH in SSS block 345 * @sg: sg for DMA transfer 346 * @sg_len: Length of sg for DMA transfer 347 * @sgl: sg for joining buffer and req->src scatterlist 348 * @skip: Skip offset in req->src for current op 349 * @total: Total number of bytes for current request 350 * @finup: Keep state for finup or final. 351 * @error: Keep track of error. 352 * @bufcnt: Number of bytes holded in buffer[] 353 * @buffer: For byte(s) from end of req->src in UPDATE op 354 */ 355struct s5p_hash_reqctx { 356 struct s5p_aes_dev *dd; 357 bool op_update; 358 359 u64 digcnt; 360 u8 digest[SHA256_DIGEST_SIZE]; 361 362 unsigned int nregs; /* digest_size / sizeof(reg) */ 363 u32 engine; 364 365 struct scatterlist *sg; 366 unsigned int sg_len; 367 struct scatterlist sgl[2]; 368 unsigned int skip; 369 unsigned int total; 370 bool finup; 371 bool error; 372 373 u32 bufcnt; 374 u8 buffer[]; 375}; 376 377/** 378 * struct s5p_hash_ctx - HASH transformation context 379 * @dd: Associated device 380 * @flags: Bits for algorithm HASH. 381 * @fallback: Software transformation for zero message or size < BUFLEN. 382 */ 383struct s5p_hash_ctx { 384 struct s5p_aes_dev *dd; 385 unsigned long flags; 386 struct crypto_shash *fallback; 387}; 388 389static const struct samsung_aes_variant s5p_aes_data = { 390 .aes_offset = 0x4000, 391 .hash_offset = 0x6000, 392 .clk_names = { "secss", }, 393}; 394 395static const struct samsung_aes_variant exynos_aes_data = { 396 .aes_offset = 0x200, 397 .hash_offset = 0x400, 398 .clk_names = { "secss", }, 399}; 400 401static const struct samsung_aes_variant exynos5433_slim_aes_data = { 402 .aes_offset = 0x400, 403 .hash_offset = 0x800, 404 .clk_names = { "aclk", "pclk", }, 405}; 406 407static const struct of_device_id s5p_sss_dt_match[] = { 408 { 409 .compatible = "samsung,s5pv210-secss", 410 .data = &s5p_aes_data, 411 }, 412 { 413 .compatible = "samsung,exynos4210-secss", 414 .data = &exynos_aes_data, 415 }, 416 { 417 .compatible = "samsung,exynos5433-slim-sss", 418 .data = &exynos5433_slim_aes_data, 419 }, 420 { }, 421}; 422MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); 423 424static inline const struct samsung_aes_variant *find_s5p_sss_version 425 (const struct platform_device *pdev) 426{ 427 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) 428 return of_device_get_match_data(&pdev->dev); 429 430 return (const struct samsung_aes_variant *) 431 platform_get_device_id(pdev)->driver_data; 432} 433 434static struct s5p_aes_dev *s5p_dev; 435 436static void s5p_set_dma_indata(struct s5p_aes_dev *dev, 437 const struct scatterlist *sg) 438{ 439 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); 440 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); 441} 442 443static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, 444 const struct scatterlist *sg) 445{ 446 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); 447 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); 448} 449 450static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg) 451{ 452 int len; 453 454 if (!*sg) 455 return; 456 457 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 458 free_pages((unsigned long)sg_virt(*sg), get_order(len)); 459 460 kfree(*sg); 461 *sg = NULL; 462} 463 464static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg, 465 unsigned int nbytes, int out) 466{ 467 struct scatter_walk walk; 468 469 if (!nbytes) 470 return; 471 472 scatterwalk_start(&walk, sg); 473 scatterwalk_copychunks(buf, &walk, nbytes, out); 474 scatterwalk_done(&walk, out, 0); 475} 476 477static void s5p_sg_done(struct s5p_aes_dev *dev) 478{ 479 struct skcipher_request *req = dev->req; 480 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 481 482 if (dev->sg_dst_cpy) { 483 dev_dbg(dev->dev, 484 "Copying %d bytes of output data back to original place\n", 485 dev->req->cryptlen); 486 s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst, 487 dev->req->cryptlen, 1); 488 } 489 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 490 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 491 if (reqctx->mode & FLAGS_AES_CBC) 492 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), AES_BLOCK_SIZE); 493 494 else if (reqctx->mode & FLAGS_AES_CTR) 495 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), AES_BLOCK_SIZE); 496} 497 498/* Calls the completion. Cannot be called with dev->lock hold. */ 499static void s5p_aes_complete(struct skcipher_request *req, int err) 500{ 501 skcipher_request_complete(req, err); 502} 503 504static void s5p_unset_outdata(struct s5p_aes_dev *dev) 505{ 506 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); 507} 508 509static void s5p_unset_indata(struct s5p_aes_dev *dev) 510{ 511 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); 512} 513 514static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src, 515 struct scatterlist **dst) 516{ 517 void *pages; 518 int len; 519 520 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC); 521 if (!*dst) 522 return -ENOMEM; 523 524 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 525 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len)); 526 if (!pages) { 527 kfree(*dst); 528 *dst = NULL; 529 return -ENOMEM; 530 } 531 532 s5p_sg_copy_buf(pages, src, dev->req->cryptlen, 0); 533 534 sg_init_table(*dst, 1); 535 sg_set_buf(*dst, pages, len); 536 537 return 0; 538} 539 540static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) 541{ 542 if (!sg->length) 543 return -EINVAL; 544 545 if (!dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE)) 546 return -ENOMEM; 547 548 dev->sg_dst = sg; 549 550 return 0; 551} 552 553static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) 554{ 555 if (!sg->length) 556 return -EINVAL; 557 558 if (!dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE)) 559 return -ENOMEM; 560 561 dev->sg_src = sg; 562 563 return 0; 564} 565 566/* 567 * Returns -ERRNO on error (mapping of new data failed). 568 * On success returns: 569 * - 0 if there is no more data, 570 * - 1 if new transmitting (output) data is ready and its address+length 571 * have to be written to device (by calling s5p_set_dma_outdata()). 572 */ 573static int s5p_aes_tx(struct s5p_aes_dev *dev) 574{ 575 int ret = 0; 576 577 s5p_unset_outdata(dev); 578 579 if (!sg_is_last(dev->sg_dst)) { 580 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst)); 581 if (!ret) 582 ret = 1; 583 } 584 585 return ret; 586} 587 588/* 589 * Returns -ERRNO on error (mapping of new data failed). 590 * On success returns: 591 * - 0 if there is no more data, 592 * - 1 if new receiving (input) data is ready and its address+length 593 * have to be written to device (by calling s5p_set_dma_indata()). 594 */ 595static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/) 596{ 597 int ret = 0; 598 599 s5p_unset_indata(dev); 600 601 if (!sg_is_last(dev->sg_src)) { 602 ret = s5p_set_indata(dev, sg_next(dev->sg_src)); 603 if (!ret) 604 ret = 1; 605 } 606 607 return ret; 608} 609 610static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset) 611{ 612 return __raw_readl(dd->io_hash_base + offset); 613} 614 615static inline void s5p_hash_write(struct s5p_aes_dev *dd, 616 u32 offset, u32 value) 617{ 618 __raw_writel(value, dd->io_hash_base + offset); 619} 620 621/** 622 * s5p_set_dma_hashdata() - start DMA with sg 623 * @dev: device 624 * @sg: scatterlist ready to DMA transmit 625 */ 626static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev, 627 const struct scatterlist *sg) 628{ 629 dev->hash_sg_cnt--; 630 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg)); 631 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */ 632} 633 634/** 635 * s5p_hash_rx() - get next hash_sg_iter 636 * @dev: device 637 * 638 * Return: 639 * 2 if there is no more data and it is UPDATE op 640 * 1 if new receiving (input) data is ready and can be written to device 641 * 0 if there is no more data and it is FINAL op 642 */ 643static int s5p_hash_rx(struct s5p_aes_dev *dev) 644{ 645 if (dev->hash_sg_cnt > 0) { 646 dev->hash_sg_iter = sg_next(dev->hash_sg_iter); 647 return 1; 648 } 649 650 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags); 651 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags)) 652 return 0; 653 654 return 2; 655} 656 657static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) 658{ 659 struct platform_device *pdev = dev_id; 660 struct s5p_aes_dev *dev = platform_get_drvdata(pdev); 661 struct skcipher_request *req; 662 int err_dma_tx = 0; 663 int err_dma_rx = 0; 664 int err_dma_hx = 0; 665 bool tx_end = false; 666 bool hx_end = false; 667 unsigned long flags; 668 u32 status, st_bits; 669 int err; 670 671 spin_lock_irqsave(&dev->lock, flags); 672 673 /* 674 * Handle rx or tx interrupt. If there is still data (scatterlist did not 675 * reach end), then map next scatterlist entry. 676 * In case of such mapping error, s5p_aes_complete() should be called. 677 * 678 * If there is no more data in tx scatter list, call s5p_aes_complete() 679 * and schedule new tasklet. 680 * 681 * Handle hx interrupt. If there is still data map next entry. 682 */ 683 status = SSS_READ(dev, FCINTSTAT); 684 if (status & SSS_FCINTSTAT_BRDMAINT) 685 err_dma_rx = s5p_aes_rx(dev); 686 687 if (status & SSS_FCINTSTAT_BTDMAINT) { 688 if (sg_is_last(dev->sg_dst)) 689 tx_end = true; 690 err_dma_tx = s5p_aes_tx(dev); 691 } 692 693 if (status & SSS_FCINTSTAT_HRDMAINT) 694 err_dma_hx = s5p_hash_rx(dev); 695 696 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT | 697 SSS_FCINTSTAT_HRDMAINT); 698 /* clear DMA bits */ 699 SSS_WRITE(dev, FCINTPEND, st_bits); 700 701 /* clear HASH irq bits */ 702 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) { 703 /* cannot have both HPART and HDONE */ 704 if (status & SSS_FCINTSTAT_HPARTINT) 705 st_bits = SSS_HASH_STATUS_PARTIAL_DONE; 706 707 if (status & SSS_FCINTSTAT_HDONEINT) 708 st_bits = SSS_HASH_STATUS_MSG_DONE; 709 710 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags); 711 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits); 712 hx_end = true; 713 /* when DONE or PART, do not handle HASH DMA */ 714 err_dma_hx = 0; 715 } 716 717 if (err_dma_rx < 0) { 718 err = err_dma_rx; 719 goto error; 720 } 721 if (err_dma_tx < 0) { 722 err = err_dma_tx; 723 goto error; 724 } 725 726 if (tx_end) { 727 s5p_sg_done(dev); 728 if (err_dma_hx == 1) 729 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 730 731 spin_unlock_irqrestore(&dev->lock, flags); 732 733 s5p_aes_complete(dev->req, 0); 734 /* Device is still busy */ 735 tasklet_schedule(&dev->tasklet); 736 } else { 737 /* 738 * Writing length of DMA block (either receiving or 739 * transmitting) will start the operation immediately, so this 740 * should be done at the end (even after clearing pending 741 * interrupts to not miss the interrupt). 742 */ 743 if (err_dma_tx == 1) 744 s5p_set_dma_outdata(dev, dev->sg_dst); 745 if (err_dma_rx == 1) 746 s5p_set_dma_indata(dev, dev->sg_src); 747 if (err_dma_hx == 1) 748 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 749 750 spin_unlock_irqrestore(&dev->lock, flags); 751 } 752 753 goto hash_irq_end; 754 755error: 756 s5p_sg_done(dev); 757 dev->busy = false; 758 req = dev->req; 759 if (err_dma_hx == 1) 760 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 761 762 spin_unlock_irqrestore(&dev->lock, flags); 763 s5p_aes_complete(req, err); 764 765hash_irq_end: 766 /* 767 * Note about else if: 768 * when hash_sg_iter reaches end and its UPDATE op, 769 * issue SSS_HASH_PAUSE and wait for HPART irq 770 */ 771 if (hx_end) 772 tasklet_schedule(&dev->hash_tasklet); 773 else if (err_dma_hx == 2) 774 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE, 775 SSS_HASH_PAUSE); 776 777 return IRQ_HANDLED; 778} 779 780/** 781 * s5p_hash_read_msg() - read message or IV from HW 782 * @req: AHASH request 783 */ 784static void s5p_hash_read_msg(struct ahash_request *req) 785{ 786 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 787 struct s5p_aes_dev *dd = ctx->dd; 788 u32 *hash = (u32 *)ctx->digest; 789 unsigned int i; 790 791 for (i = 0; i < ctx->nregs; i++) 792 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i)); 793} 794 795/** 796 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op. 797 * @dd: device 798 * @ctx: request context 799 */ 800static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd, 801 const struct s5p_hash_reqctx *ctx) 802{ 803 const u32 *hash = (const u32 *)ctx->digest; 804 unsigned int i; 805 806 for (i = 0; i < ctx->nregs; i++) 807 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]); 808} 809 810/** 811 * s5p_hash_write_iv() - write IV for next partial/finup op. 812 * @req: AHASH request 813 */ 814static void s5p_hash_write_iv(struct ahash_request *req) 815{ 816 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 817 818 s5p_hash_write_ctx_iv(ctx->dd, ctx); 819} 820 821/** 822 * s5p_hash_copy_result() - copy digest into req->result 823 * @req: AHASH request 824 */ 825static void s5p_hash_copy_result(struct ahash_request *req) 826{ 827 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 828 829 if (!req->result) 830 return; 831 832 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF); 833} 834 835/** 836 * s5p_hash_dma_flush() - flush HASH DMA 837 * @dev: secss device 838 */ 839static void s5p_hash_dma_flush(struct s5p_aes_dev *dev) 840{ 841 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH); 842} 843 844/** 845 * s5p_hash_dma_enable() - enable DMA mode for HASH 846 * @dev: secss device 847 * 848 * enable DMA mode for HASH 849 */ 850static void s5p_hash_dma_enable(struct s5p_aes_dev *dev) 851{ 852 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA); 853} 854 855/** 856 * s5p_hash_irq_disable() - disable irq HASH signals 857 * @dev: secss device 858 * @flags: bitfield with irq's to be disabled 859 */ 860static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags) 861{ 862 SSS_WRITE(dev, FCINTENCLR, flags); 863} 864 865/** 866 * s5p_hash_irq_enable() - enable irq signals 867 * @dev: secss device 868 * @flags: bitfield with irq's to be enabled 869 */ 870static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags) 871{ 872 SSS_WRITE(dev, FCINTENSET, flags); 873} 874 875/** 876 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH 877 * @dev: secss device 878 * @hashflow: HASH stream flow with/without crypto AES/DES 879 */ 880static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow) 881{ 882 unsigned long flags; 883 u32 flow; 884 885 spin_lock_irqsave(&dev->lock, flags); 886 887 flow = SSS_READ(dev, FCFIFOCTRL); 888 flow &= ~SSS_HASHIN_MASK; 889 flow |= hashflow; 890 SSS_WRITE(dev, FCFIFOCTRL, flow); 891 892 spin_unlock_irqrestore(&dev->lock, flags); 893} 894 895/** 896 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS 897 * @dev: secss device 898 * @hashflow: HASH stream flow with/without AES/DES 899 * 900 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW, 901 * enable HASH irq's HRDMA, HDONE, HPART 902 */ 903static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow) 904{ 905 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR | 906 SSS_FCINTENCLR_HDONEINTENCLR | 907 SSS_FCINTENCLR_HPARTINTENCLR); 908 s5p_hash_dma_flush(dev); 909 910 s5p_hash_dma_enable(dev); 911 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK); 912 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET | 913 SSS_FCINTENSET_HDONEINTENSET | 914 SSS_FCINTENSET_HPARTINTENSET); 915} 916 917/** 918 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing 919 * @dd: secss device 920 * @length: length for request 921 * @final: true if final op 922 * 923 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called 924 * after previous updates, fill up IV words. For final, calculate and set 925 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH 926 * length as 2^63 so it will be never reached and set to zero prelow and 927 * prehigh. 928 * 929 * This function does not start DMA transfer. 930 */ 931static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length, 932 bool final) 933{ 934 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 935 u32 prelow, prehigh, low, high; 936 u32 configflags, swapflags; 937 u64 tmplen; 938 939 configflags = ctx->engine | SSS_HASH_INIT_BIT; 940 941 if (likely(ctx->digcnt)) { 942 s5p_hash_write_ctx_iv(dd, ctx); 943 configflags |= SSS_HASH_USER_IV_EN; 944 } 945 946 if (final) { 947 /* number of bytes for last part */ 948 low = length; 949 high = 0; 950 /* total number of bits prev hashed */ 951 tmplen = ctx->digcnt * 8; 952 prelow = (u32)tmplen; 953 prehigh = (u32)(tmplen >> 32); 954 } else { 955 prelow = 0; 956 prehigh = 0; 957 low = 0; 958 high = BIT(31); 959 } 960 961 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO | 962 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY; 963 964 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low); 965 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high); 966 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow); 967 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh); 968 969 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags); 970 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags); 971} 972 973/** 974 * s5p_hash_xmit_dma() - start DMA hash processing 975 * @dd: secss device 976 * @length: length for request 977 * @final: true if final op 978 * 979 * Update digcnt here, as it is needed for finup/final op. 980 */ 981static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length, 982 bool final) 983{ 984 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 985 unsigned int cnt; 986 987 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 988 if (!cnt) { 989 dev_err(dd->dev, "dma_map_sg error\n"); 990 ctx->error = true; 991 return -EINVAL; 992 } 993 994 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 995 dd->hash_sg_iter = ctx->sg; 996 dd->hash_sg_cnt = cnt; 997 s5p_hash_write_ctrl(dd, length, final); 998 ctx->digcnt += length; 999 ctx->total -= length; 1000 1001 /* catch last interrupt */ 1002 if (final) 1003 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags); 1004 1005 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */ 1006 1007 return -EINPROGRESS; 1008} 1009 1010/** 1011 * s5p_hash_copy_sgs() - copy request's bytes into new buffer 1012 * @ctx: request context 1013 * @sg: source scatterlist request 1014 * @new_len: number of bytes to process from sg 1015 * 1016 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf 1017 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0] 1018 * with allocated buffer. 1019 * 1020 * Set bit in dd->hash_flag so we can free it after irq ends processing. 1021 */ 1022static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx, 1023 struct scatterlist *sg, unsigned int new_len) 1024{ 1025 unsigned int pages, len; 1026 void *buf; 1027 1028 len = new_len + ctx->bufcnt; 1029 pages = get_order(len); 1030 1031 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 1032 if (!buf) { 1033 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n"); 1034 ctx->error = true; 1035 return -ENOMEM; 1036 } 1037 1038 if (ctx->bufcnt) 1039 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 1040 1041 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->skip, 1042 new_len, 0); 1043 sg_init_table(ctx->sgl, 1); 1044 sg_set_buf(ctx->sgl, buf, len); 1045 ctx->sg = ctx->sgl; 1046 ctx->sg_len = 1; 1047 ctx->bufcnt = 0; 1048 ctx->skip = 0; 1049 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags); 1050 1051 return 0; 1052} 1053 1054/** 1055 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy 1056 * @ctx: request context 1057 * @sg: source scatterlist request 1058 * @new_len: number of bytes to process from sg 1059 * 1060 * Allocate new scatterlist table, copy data for HASH into it. If there was 1061 * xmit_buf filled, prepare it first, then copy page, length and offset from 1062 * source sg into it, adjusting begin and/or end for skip offset and 1063 * hash_later value. 1064 * 1065 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free 1066 * it after irq ends processing. 1067 */ 1068static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx, 1069 struct scatterlist *sg, unsigned int new_len) 1070{ 1071 unsigned int skip = ctx->skip, n = sg_nents(sg); 1072 struct scatterlist *tmp; 1073 unsigned int len; 1074 1075 if (ctx->bufcnt) 1076 n++; 1077 1078 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 1079 if (!ctx->sg) { 1080 ctx->error = true; 1081 return -ENOMEM; 1082 } 1083 1084 sg_init_table(ctx->sg, n); 1085 1086 tmp = ctx->sg; 1087 1088 ctx->sg_len = 0; 1089 1090 if (ctx->bufcnt) { 1091 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 1092 tmp = sg_next(tmp); 1093 ctx->sg_len++; 1094 } 1095 1096 while (sg && skip >= sg->length) { 1097 skip -= sg->length; 1098 sg = sg_next(sg); 1099 } 1100 1101 while (sg && new_len) { 1102 len = sg->length - skip; 1103 if (new_len < len) 1104 len = new_len; 1105 1106 new_len -= len; 1107 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip); 1108 skip = 0; 1109 if (new_len <= 0) 1110 sg_mark_end(tmp); 1111 1112 tmp = sg_next(tmp); 1113 ctx->sg_len++; 1114 sg = sg_next(sg); 1115 } 1116 1117 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags); 1118 1119 return 0; 1120} 1121 1122/** 1123 * s5p_hash_prepare_sgs() - prepare sg for processing 1124 * @ctx: request context 1125 * @sg: source scatterlist request 1126 * @new_len: number of bytes to process from sg 1127 * @final: final flag 1128 * 1129 * Check two conditions: (1) if buffers in sg have len aligned data, and (2) 1130 * sg table have good aligned elements (list_ok). If one of this checks fails, 1131 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy 1132 * data into this buffer and prepare request in sgl, or (2) allocates new sg 1133 * table and prepare sg elements. 1134 * 1135 * For digest or finup all conditions can be good, and we may not need any 1136 * fixes. 1137 */ 1138static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx, 1139 struct scatterlist *sg, 1140 unsigned int new_len, bool final) 1141{ 1142 unsigned int skip = ctx->skip, nbytes = new_len, n = 0; 1143 bool aligned = true, list_ok = true; 1144 struct scatterlist *sg_tmp = sg; 1145 1146 if (!sg || !sg->length || !new_len) 1147 return 0; 1148 1149 if (skip || !final) 1150 list_ok = false; 1151 1152 while (nbytes > 0 && sg_tmp) { 1153 n++; 1154 if (skip >= sg_tmp->length) { 1155 skip -= sg_tmp->length; 1156 if (!sg_tmp->length) { 1157 aligned = false; 1158 break; 1159 } 1160 } else { 1161 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) { 1162 aligned = false; 1163 break; 1164 } 1165 1166 if (nbytes < sg_tmp->length - skip) { 1167 list_ok = false; 1168 break; 1169 } 1170 1171 nbytes -= sg_tmp->length - skip; 1172 skip = 0; 1173 } 1174 1175 sg_tmp = sg_next(sg_tmp); 1176 } 1177 1178 if (!aligned) 1179 return s5p_hash_copy_sgs(ctx, sg, new_len); 1180 else if (!list_ok) 1181 return s5p_hash_copy_sg_lists(ctx, sg, new_len); 1182 1183 /* 1184 * Have aligned data from previous operation and/or current 1185 * Note: will enter here only if (digest or finup) and aligned 1186 */ 1187 if (ctx->bufcnt) { 1188 ctx->sg_len = n; 1189 sg_init_table(ctx->sgl, 2); 1190 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt); 1191 sg_chain(ctx->sgl, 2, sg); 1192 ctx->sg = ctx->sgl; 1193 ctx->sg_len++; 1194 } else { 1195 ctx->sg = sg; 1196 ctx->sg_len = n; 1197 } 1198 1199 return 0; 1200} 1201 1202/** 1203 * s5p_hash_prepare_request() - prepare request for processing 1204 * @req: AHASH request 1205 * @update: true if UPDATE op 1206 * 1207 * Note 1: we can have update flag _and_ final flag at the same time. 1208 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or 1209 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or 1210 * we have final op 1211 */ 1212static int s5p_hash_prepare_request(struct ahash_request *req, bool update) 1213{ 1214 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1215 bool final = ctx->finup; 1216 int xmit_len, hash_later, nbytes; 1217 int ret; 1218 1219 if (update) 1220 nbytes = req->nbytes; 1221 else 1222 nbytes = 0; 1223 1224 ctx->total = nbytes + ctx->bufcnt; 1225 if (!ctx->total) 1226 return 0; 1227 1228 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) { 1229 /* bytes left from previous request, so fill up to BUFLEN */ 1230 int len = BUFLEN - ctx->bufcnt % BUFLEN; 1231 1232 if (len > nbytes) 1233 len = nbytes; 1234 1235 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1236 0, len, 0); 1237 ctx->bufcnt += len; 1238 nbytes -= len; 1239 ctx->skip = len; 1240 } else { 1241 ctx->skip = 0; 1242 } 1243 1244 if (ctx->bufcnt) 1245 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt); 1246 1247 xmit_len = ctx->total; 1248 if (final) { 1249 hash_later = 0; 1250 } else { 1251 if (IS_ALIGNED(xmit_len, BUFLEN)) 1252 xmit_len -= BUFLEN; 1253 else 1254 xmit_len -= xmit_len & (BUFLEN - 1); 1255 1256 hash_later = ctx->total - xmit_len; 1257 /* copy hash_later bytes from end of req->src */ 1258 /* previous bytes are in xmit_buf, so no overwrite */ 1259 scatterwalk_map_and_copy(ctx->buffer, req->src, 1260 req->nbytes - hash_later, 1261 hash_later, 0); 1262 } 1263 1264 if (xmit_len > BUFLEN) { 1265 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later, 1266 final); 1267 if (ret) 1268 return ret; 1269 } else { 1270 /* have buffered data only */ 1271 if (unlikely(!ctx->bufcnt)) { 1272 /* first update didn't fill up buffer */ 1273 scatterwalk_map_and_copy(ctx->dd->xmit_buf, req->src, 1274 0, xmit_len, 0); 1275 } 1276 1277 sg_init_table(ctx->sgl, 1); 1278 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len); 1279 1280 ctx->sg = ctx->sgl; 1281 ctx->sg_len = 1; 1282 } 1283 1284 ctx->bufcnt = hash_later; 1285 if (!final) 1286 ctx->total = xmit_len; 1287 1288 return 0; 1289} 1290 1291/** 1292 * s5p_hash_update_dma_stop() - unmap DMA 1293 * @dd: secss device 1294 * 1295 * Unmap scatterlist ctx->sg. 1296 */ 1297static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd) 1298{ 1299 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 1300 1301 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 1302 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 1303} 1304 1305/** 1306 * s5p_hash_finish() - copy calculated digest to crypto layer 1307 * @req: AHASH request 1308 */ 1309static void s5p_hash_finish(struct ahash_request *req) 1310{ 1311 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1312 struct s5p_aes_dev *dd = ctx->dd; 1313 1314 if (ctx->digcnt) 1315 s5p_hash_copy_result(req); 1316 1317 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt); 1318} 1319 1320/** 1321 * s5p_hash_finish_req() - finish request 1322 * @req: AHASH request 1323 * @err: error 1324 */ 1325static void s5p_hash_finish_req(struct ahash_request *req, int err) 1326{ 1327 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1328 struct s5p_aes_dev *dd = ctx->dd; 1329 unsigned long flags; 1330 1331 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags)) 1332 free_pages((unsigned long)sg_virt(ctx->sg), 1333 get_order(ctx->sg->length)); 1334 1335 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags)) 1336 kfree(ctx->sg); 1337 1338 ctx->sg = NULL; 1339 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) | 1340 BIT(HASH_FLAGS_SGS_COPIED)); 1341 1342 if (!err && !ctx->error) { 1343 s5p_hash_read_msg(req); 1344 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags)) 1345 s5p_hash_finish(req); 1346 } else { 1347 ctx->error = true; 1348 } 1349 1350 spin_lock_irqsave(&dd->hash_lock, flags); 1351 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) | 1352 BIT(HASH_FLAGS_DMA_READY) | 1353 BIT(HASH_FLAGS_OUTPUT_READY)); 1354 spin_unlock_irqrestore(&dd->hash_lock, flags); 1355 1356 if (req->base.complete) 1357 ahash_request_complete(req, err); 1358} 1359 1360/** 1361 * s5p_hash_handle_queue() - handle hash queue 1362 * @dd: device s5p_aes_dev 1363 * @req: AHASH request 1364 * 1365 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the 1366 * device then processes the first request from the dd->queue 1367 * 1368 * Returns: see s5p_hash_final below. 1369 */ 1370static int s5p_hash_handle_queue(struct s5p_aes_dev *dd, 1371 struct ahash_request *req) 1372{ 1373 struct crypto_async_request *async_req, *backlog; 1374 struct s5p_hash_reqctx *ctx; 1375 unsigned long flags; 1376 int err = 0, ret = 0; 1377 1378retry: 1379 spin_lock_irqsave(&dd->hash_lock, flags); 1380 if (req) 1381 ret = ahash_enqueue_request(&dd->hash_queue, req); 1382 1383 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1384 spin_unlock_irqrestore(&dd->hash_lock, flags); 1385 return ret; 1386 } 1387 1388 backlog = crypto_get_backlog(&dd->hash_queue); 1389 async_req = crypto_dequeue_request(&dd->hash_queue); 1390 if (async_req) 1391 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags); 1392 1393 spin_unlock_irqrestore(&dd->hash_lock, flags); 1394 1395 if (!async_req) 1396 return ret; 1397 1398 if (backlog) 1399 crypto_request_complete(backlog, -EINPROGRESS); 1400 1401 req = ahash_request_cast(async_req); 1402 dd->hash_req = req; 1403 ctx = ahash_request_ctx(req); 1404 1405 err = s5p_hash_prepare_request(req, ctx->op_update); 1406 if (err || !ctx->total) 1407 goto out; 1408 1409 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n", 1410 ctx->op_update, req->nbytes); 1411 1412 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT); 1413 if (ctx->digcnt) 1414 s5p_hash_write_iv(req); /* restore hash IV */ 1415 1416 if (ctx->op_update) { /* HASH_OP_UPDATE */ 1417 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup); 1418 if (err != -EINPROGRESS && ctx->finup && !ctx->error) 1419 /* no final() after finup() */ 1420 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1421 } else { /* HASH_OP_FINAL */ 1422 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1423 } 1424out: 1425 if (err != -EINPROGRESS) { 1426 /* hash_tasklet_cb will not finish it, so do it here */ 1427 s5p_hash_finish_req(req, err); 1428 req = NULL; 1429 1430 /* 1431 * Execute next request immediately if there is anything 1432 * in queue. 1433 */ 1434 goto retry; 1435 } 1436 1437 return ret; 1438} 1439 1440/** 1441 * s5p_hash_tasklet_cb() - hash tasklet 1442 * @data: ptr to s5p_aes_dev 1443 */ 1444static void s5p_hash_tasklet_cb(unsigned long data) 1445{ 1446 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data; 1447 1448 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1449 s5p_hash_handle_queue(dd, NULL); 1450 return; 1451 } 1452 1453 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) { 1454 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE, 1455 &dd->hash_flags)) { 1456 s5p_hash_update_dma_stop(dd); 1457 } 1458 1459 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY, 1460 &dd->hash_flags)) { 1461 /* hash or semi-hash ready */ 1462 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags); 1463 goto finish; 1464 } 1465 } 1466 1467 return; 1468 1469finish: 1470 /* finish curent request */ 1471 s5p_hash_finish_req(dd->hash_req, 0); 1472 1473 /* If we are not busy, process next req */ 1474 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) 1475 s5p_hash_handle_queue(dd, NULL); 1476} 1477 1478/** 1479 * s5p_hash_enqueue() - enqueue request 1480 * @req: AHASH request 1481 * @op: operation UPDATE (true) or FINAL (false) 1482 * 1483 * Returns: see s5p_hash_final below. 1484 */ 1485static int s5p_hash_enqueue(struct ahash_request *req, bool op) 1486{ 1487 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1488 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1489 1490 ctx->op_update = op; 1491 1492 return s5p_hash_handle_queue(tctx->dd, req); 1493} 1494 1495/** 1496 * s5p_hash_update() - process the hash input data 1497 * @req: AHASH request 1498 * 1499 * If request will fit in buffer, copy it and return immediately 1500 * else enqueue it with OP_UPDATE. 1501 * 1502 * Returns: see s5p_hash_final below. 1503 */ 1504static int s5p_hash_update(struct ahash_request *req) 1505{ 1506 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1507 1508 if (!req->nbytes) 1509 return 0; 1510 1511 if (ctx->bufcnt + req->nbytes <= BUFLEN) { 1512 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1513 0, req->nbytes, 0); 1514 ctx->bufcnt += req->nbytes; 1515 return 0; 1516 } 1517 1518 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */ 1519} 1520 1521/** 1522 * s5p_hash_final() - close up hash and calculate digest 1523 * @req: AHASH request 1524 * 1525 * Note: in final req->src do not have any data, and req->nbytes can be 1526 * non-zero. 1527 * 1528 * If there were no input data processed yet and the buffered hash data is 1529 * less than BUFLEN (64) then calculate the final hash immediately by using 1530 * SW algorithm fallback. 1531 * 1532 * Otherwise enqueues the current AHASH request with OP_FINAL operation op 1533 * and finalize hash message in HW. Note that if digcnt!=0 then there were 1534 * previous update op, so there are always some buffered bytes in ctx->buffer, 1535 * which means that ctx->bufcnt!=0 1536 * 1537 * Returns: 1538 * 0 if the request has been processed immediately, 1539 * -EINPROGRESS if the operation has been queued for later execution or is set 1540 * to processing by HW, 1541 * -EBUSY if queue is full and request should be resubmitted later, 1542 * other negative values denotes an error. 1543 */ 1544static int s5p_hash_final(struct ahash_request *req) 1545{ 1546 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1547 1548 ctx->finup = true; 1549 if (ctx->error) 1550 return -EINVAL; /* uncompleted hash is not needed */ 1551 1552 if (!ctx->digcnt && ctx->bufcnt < BUFLEN) { 1553 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1554 1555 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer, 1556 ctx->bufcnt, req->result); 1557 } 1558 1559 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */ 1560} 1561 1562/** 1563 * s5p_hash_finup() - process last req->src and calculate digest 1564 * @req: AHASH request containing the last update data 1565 * 1566 * Return values: see s5p_hash_final above. 1567 */ 1568static int s5p_hash_finup(struct ahash_request *req) 1569{ 1570 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1571 int err1, err2; 1572 1573 ctx->finup = true; 1574 1575 err1 = s5p_hash_update(req); 1576 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1577 return err1; 1578 1579 /* 1580 * final() has to be always called to cleanup resources even if 1581 * update() failed, except EINPROGRESS or calculate digest for small 1582 * size 1583 */ 1584 err2 = s5p_hash_final(req); 1585 1586 return err1 ?: err2; 1587} 1588 1589/** 1590 * s5p_hash_init() - initialize AHASH request contex 1591 * @req: AHASH request 1592 * 1593 * Init async hash request context. 1594 */ 1595static int s5p_hash_init(struct ahash_request *req) 1596{ 1597 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1598 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1599 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1600 1601 ctx->dd = tctx->dd; 1602 ctx->error = false; 1603 ctx->finup = false; 1604 ctx->bufcnt = 0; 1605 ctx->digcnt = 0; 1606 ctx->total = 0; 1607 ctx->skip = 0; 1608 1609 dev_dbg(tctx->dd->dev, "init: digest size: %d\n", 1610 crypto_ahash_digestsize(tfm)); 1611 1612 switch (crypto_ahash_digestsize(tfm)) { 1613 case MD5_DIGEST_SIZE: 1614 ctx->engine = SSS_HASH_ENGINE_MD5; 1615 ctx->nregs = HASH_MD5_MAX_REG; 1616 break; 1617 case SHA1_DIGEST_SIZE: 1618 ctx->engine = SSS_HASH_ENGINE_SHA1; 1619 ctx->nregs = HASH_SHA1_MAX_REG; 1620 break; 1621 case SHA256_DIGEST_SIZE: 1622 ctx->engine = SSS_HASH_ENGINE_SHA256; 1623 ctx->nregs = HASH_SHA256_MAX_REG; 1624 break; 1625 default: 1626 ctx->error = true; 1627 return -EINVAL; 1628 } 1629 1630 return 0; 1631} 1632 1633/** 1634 * s5p_hash_digest - calculate digest from req->src 1635 * @req: AHASH request 1636 * 1637 * Return values: see s5p_hash_final above. 1638 */ 1639static int s5p_hash_digest(struct ahash_request *req) 1640{ 1641 return s5p_hash_init(req) ?: s5p_hash_finup(req); 1642} 1643 1644/** 1645 * s5p_hash_cra_init_alg - init crypto alg transformation 1646 * @tfm: crypto transformation 1647 */ 1648static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm) 1649{ 1650 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1651 const char *alg_name = crypto_tfm_alg_name(tfm); 1652 1653 tctx->dd = s5p_dev; 1654 /* Allocate a fallback and abort if it failed. */ 1655 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1656 CRYPTO_ALG_NEED_FALLBACK); 1657 if (IS_ERR(tctx->fallback)) { 1658 pr_err("fallback alloc fails for '%s'\n", alg_name); 1659 return PTR_ERR(tctx->fallback); 1660 } 1661 1662 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1663 sizeof(struct s5p_hash_reqctx) + BUFLEN); 1664 1665 return 0; 1666} 1667 1668/** 1669 * s5p_hash_cra_init - init crypto tfm 1670 * @tfm: crypto transformation 1671 */ 1672static int s5p_hash_cra_init(struct crypto_tfm *tfm) 1673{ 1674 return s5p_hash_cra_init_alg(tfm); 1675} 1676 1677/** 1678 * s5p_hash_cra_exit - exit crypto tfm 1679 * @tfm: crypto transformation 1680 * 1681 * free allocated fallback 1682 */ 1683static void s5p_hash_cra_exit(struct crypto_tfm *tfm) 1684{ 1685 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1686 1687 crypto_free_shash(tctx->fallback); 1688 tctx->fallback = NULL; 1689} 1690 1691/** 1692 * s5p_hash_export - export hash state 1693 * @req: AHASH request 1694 * @out: buffer for exported state 1695 */ 1696static int s5p_hash_export(struct ahash_request *req, void *out) 1697{ 1698 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1699 1700 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt); 1701 1702 return 0; 1703} 1704 1705/** 1706 * s5p_hash_import - import hash state 1707 * @req: AHASH request 1708 * @in: buffer with state to be imported from 1709 */ 1710static int s5p_hash_import(struct ahash_request *req, const void *in) 1711{ 1712 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1713 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1714 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1715 const struct s5p_hash_reqctx *ctx_in = in; 1716 1717 memcpy(ctx, in, sizeof(*ctx) + BUFLEN); 1718 if (ctx_in->bufcnt > BUFLEN) { 1719 ctx->error = true; 1720 return -EINVAL; 1721 } 1722 1723 ctx->dd = tctx->dd; 1724 ctx->error = false; 1725 1726 return 0; 1727} 1728 1729static struct ahash_alg algs_sha1_md5_sha256[] = { 1730{ 1731 .init = s5p_hash_init, 1732 .update = s5p_hash_update, 1733 .final = s5p_hash_final, 1734 .finup = s5p_hash_finup, 1735 .digest = s5p_hash_digest, 1736 .export = s5p_hash_export, 1737 .import = s5p_hash_import, 1738 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1739 .halg.digestsize = SHA1_DIGEST_SIZE, 1740 .halg.base = { 1741 .cra_name = "sha1", 1742 .cra_driver_name = "exynos-sha1", 1743 .cra_priority = 100, 1744 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1745 CRYPTO_ALG_ASYNC | 1746 CRYPTO_ALG_NEED_FALLBACK, 1747 .cra_blocksize = HASH_BLOCK_SIZE, 1748 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1749 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK, 1750 .cra_module = THIS_MODULE, 1751 .cra_init = s5p_hash_cra_init, 1752 .cra_exit = s5p_hash_cra_exit, 1753 } 1754}, 1755{ 1756 .init = s5p_hash_init, 1757 .update = s5p_hash_update, 1758 .final = s5p_hash_final, 1759 .finup = s5p_hash_finup, 1760 .digest = s5p_hash_digest, 1761 .export = s5p_hash_export, 1762 .import = s5p_hash_import, 1763 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1764 .halg.digestsize = MD5_DIGEST_SIZE, 1765 .halg.base = { 1766 .cra_name = "md5", 1767 .cra_driver_name = "exynos-md5", 1768 .cra_priority = 100, 1769 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1770 CRYPTO_ALG_ASYNC | 1771 CRYPTO_ALG_NEED_FALLBACK, 1772 .cra_blocksize = HASH_BLOCK_SIZE, 1773 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1774 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK, 1775 .cra_module = THIS_MODULE, 1776 .cra_init = s5p_hash_cra_init, 1777 .cra_exit = s5p_hash_cra_exit, 1778 } 1779}, 1780{ 1781 .init = s5p_hash_init, 1782 .update = s5p_hash_update, 1783 .final = s5p_hash_final, 1784 .finup = s5p_hash_finup, 1785 .digest = s5p_hash_digest, 1786 .export = s5p_hash_export, 1787 .import = s5p_hash_import, 1788 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1789 .halg.digestsize = SHA256_DIGEST_SIZE, 1790 .halg.base = { 1791 .cra_name = "sha256", 1792 .cra_driver_name = "exynos-sha256", 1793 .cra_priority = 100, 1794 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1795 CRYPTO_ALG_ASYNC | 1796 CRYPTO_ALG_NEED_FALLBACK, 1797 .cra_blocksize = HASH_BLOCK_SIZE, 1798 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1799 .cra_alignmask = SSS_HASH_DMA_ALIGN_MASK, 1800 .cra_module = THIS_MODULE, 1801 .cra_init = s5p_hash_cra_init, 1802 .cra_exit = s5p_hash_cra_exit, 1803 } 1804} 1805 1806}; 1807 1808static void s5p_set_aes(struct s5p_aes_dev *dev, 1809 const u8 *key, const u8 *iv, const u8 *ctr, 1810 unsigned int keylen) 1811{ 1812 void __iomem *keystart; 1813 1814 if (iv) 1815 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 1816 AES_BLOCK_SIZE); 1817 1818 if (ctr) 1819 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, 1820 AES_BLOCK_SIZE); 1821 1822 if (keylen == AES_KEYSIZE_256) 1823 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0); 1824 else if (keylen == AES_KEYSIZE_192) 1825 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2); 1826 else 1827 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4); 1828 1829 memcpy_toio(keystart, key, keylen); 1830} 1831 1832static bool s5p_is_sg_aligned(struct scatterlist *sg) 1833{ 1834 while (sg) { 1835 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE)) 1836 return false; 1837 sg = sg_next(sg); 1838 } 1839 1840 return true; 1841} 1842 1843static int s5p_set_indata_start(struct s5p_aes_dev *dev, 1844 struct skcipher_request *req) 1845{ 1846 struct scatterlist *sg; 1847 int err; 1848 1849 dev->sg_src_cpy = NULL; 1850 sg = req->src; 1851 if (!s5p_is_sg_aligned(sg)) { 1852 dev_dbg(dev->dev, 1853 "At least one unaligned source scatter list, making a copy\n"); 1854 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy); 1855 if (err) 1856 return err; 1857 1858 sg = dev->sg_src_cpy; 1859 } 1860 1861 err = s5p_set_indata(dev, sg); 1862 if (err) { 1863 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 1864 return err; 1865 } 1866 1867 return 0; 1868} 1869 1870static int s5p_set_outdata_start(struct s5p_aes_dev *dev, 1871 struct skcipher_request *req) 1872{ 1873 struct scatterlist *sg; 1874 int err; 1875 1876 dev->sg_dst_cpy = NULL; 1877 sg = req->dst; 1878 if (!s5p_is_sg_aligned(sg)) { 1879 dev_dbg(dev->dev, 1880 "At least one unaligned dest scatter list, making a copy\n"); 1881 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy); 1882 if (err) 1883 return err; 1884 1885 sg = dev->sg_dst_cpy; 1886 } 1887 1888 err = s5p_set_outdata(dev, sg); 1889 if (err) { 1890 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 1891 return err; 1892 } 1893 1894 return 0; 1895} 1896 1897static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) 1898{ 1899 struct skcipher_request *req = dev->req; 1900 u32 aes_control; 1901 unsigned long flags; 1902 int err; 1903 u8 *iv, *ctr; 1904 1905 /* This sets bit [13:12] to 00, which selects 128-bit counter */ 1906 aes_control = SSS_AES_KEY_CHANGE_MODE; 1907 if (mode & FLAGS_AES_DECRYPT) 1908 aes_control |= SSS_AES_MODE_DECRYPT; 1909 1910 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) { 1911 aes_control |= SSS_AES_CHAIN_MODE_CBC; 1912 iv = req->iv; 1913 ctr = NULL; 1914 } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) { 1915 aes_control |= SSS_AES_CHAIN_MODE_CTR; 1916 iv = NULL; 1917 ctr = req->iv; 1918 } else { 1919 iv = NULL; /* AES_ECB */ 1920 ctr = NULL; 1921 } 1922 1923 if (dev->ctx->keylen == AES_KEYSIZE_192) 1924 aes_control |= SSS_AES_KEY_SIZE_192; 1925 else if (dev->ctx->keylen == AES_KEYSIZE_256) 1926 aes_control |= SSS_AES_KEY_SIZE_256; 1927 1928 aes_control |= SSS_AES_FIFO_MODE; 1929 1930 /* as a variant it is possible to use byte swapping on DMA side */ 1931 aes_control |= SSS_AES_BYTESWAP_DI 1932 | SSS_AES_BYTESWAP_DO 1933 | SSS_AES_BYTESWAP_IV 1934 | SSS_AES_BYTESWAP_KEY 1935 | SSS_AES_BYTESWAP_CNT; 1936 1937 spin_lock_irqsave(&dev->lock, flags); 1938 1939 SSS_WRITE(dev, FCINTENCLR, 1940 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); 1941 SSS_WRITE(dev, FCFIFOCTRL, 0x00); 1942 1943 err = s5p_set_indata_start(dev, req); 1944 if (err) 1945 goto indata_error; 1946 1947 err = s5p_set_outdata_start(dev, req); 1948 if (err) 1949 goto outdata_error; 1950 1951 SSS_AES_WRITE(dev, AES_CONTROL, aes_control); 1952 s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen); 1953 1954 s5p_set_dma_indata(dev, dev->sg_src); 1955 s5p_set_dma_outdata(dev, dev->sg_dst); 1956 1957 SSS_WRITE(dev, FCINTENSET, 1958 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); 1959 1960 spin_unlock_irqrestore(&dev->lock, flags); 1961 1962 return; 1963 1964outdata_error: 1965 s5p_unset_indata(dev); 1966 1967indata_error: 1968 s5p_sg_done(dev); 1969 dev->busy = false; 1970 spin_unlock_irqrestore(&dev->lock, flags); 1971 s5p_aes_complete(req, err); 1972} 1973 1974static void s5p_tasklet_cb(unsigned long data) 1975{ 1976 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; 1977 struct crypto_async_request *async_req, *backlog; 1978 struct s5p_aes_reqctx *reqctx; 1979 unsigned long flags; 1980 1981 spin_lock_irqsave(&dev->lock, flags); 1982 backlog = crypto_get_backlog(&dev->queue); 1983 async_req = crypto_dequeue_request(&dev->queue); 1984 1985 if (!async_req) { 1986 dev->busy = false; 1987 spin_unlock_irqrestore(&dev->lock, flags); 1988 return; 1989 } 1990 spin_unlock_irqrestore(&dev->lock, flags); 1991 1992 if (backlog) 1993 crypto_request_complete(backlog, -EINPROGRESS); 1994 1995 dev->req = skcipher_request_cast(async_req); 1996 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); 1997 reqctx = skcipher_request_ctx(dev->req); 1998 1999 s5p_aes_crypt_start(dev, reqctx->mode); 2000} 2001 2002static int s5p_aes_handle_req(struct s5p_aes_dev *dev, 2003 struct skcipher_request *req) 2004{ 2005 unsigned long flags; 2006 int err; 2007 2008 spin_lock_irqsave(&dev->lock, flags); 2009 err = crypto_enqueue_request(&dev->queue, &req->base); 2010 if (dev->busy) { 2011 spin_unlock_irqrestore(&dev->lock, flags); 2012 return err; 2013 } 2014 dev->busy = true; 2015 2016 spin_unlock_irqrestore(&dev->lock, flags); 2017 2018 tasklet_schedule(&dev->tasklet); 2019 2020 return err; 2021} 2022 2023static int s5p_aes_crypt(struct skcipher_request *req, unsigned long mode) 2024{ 2025 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 2026 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 2027 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2028 struct s5p_aes_dev *dev = ctx->dev; 2029 2030 if (!req->cryptlen) 2031 return 0; 2032 2033 if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE) && 2034 ((mode & FLAGS_AES_MODE_MASK) != FLAGS_AES_CTR)) { 2035 dev_dbg(dev->dev, "request size is not exact amount of AES blocks\n"); 2036 return -EINVAL; 2037 } 2038 2039 reqctx->mode = mode; 2040 2041 return s5p_aes_handle_req(dev, req); 2042} 2043 2044static int s5p_aes_setkey(struct crypto_skcipher *cipher, 2045 const u8 *key, unsigned int keylen) 2046{ 2047 struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); 2048 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); 2049 2050 if (keylen != AES_KEYSIZE_128 && 2051 keylen != AES_KEYSIZE_192 && 2052 keylen != AES_KEYSIZE_256) 2053 return -EINVAL; 2054 2055 memcpy(ctx->aes_key, key, keylen); 2056 ctx->keylen = keylen; 2057 2058 return 0; 2059} 2060 2061static int s5p_aes_ecb_encrypt(struct skcipher_request *req) 2062{ 2063 return s5p_aes_crypt(req, 0); 2064} 2065 2066static int s5p_aes_ecb_decrypt(struct skcipher_request *req) 2067{ 2068 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); 2069} 2070 2071static int s5p_aes_cbc_encrypt(struct skcipher_request *req) 2072{ 2073 return s5p_aes_crypt(req, FLAGS_AES_CBC); 2074} 2075 2076static int s5p_aes_cbc_decrypt(struct skcipher_request *req) 2077{ 2078 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); 2079} 2080 2081static int s5p_aes_ctr_crypt(struct skcipher_request *req) 2082{ 2083 return s5p_aes_crypt(req, FLAGS_AES_CTR); 2084} 2085 2086static int s5p_aes_init_tfm(struct crypto_skcipher *tfm) 2087{ 2088 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2089 2090 ctx->dev = s5p_dev; 2091 crypto_skcipher_set_reqsize(tfm, sizeof(struct s5p_aes_reqctx)); 2092 2093 return 0; 2094} 2095 2096static struct skcipher_alg algs[] = { 2097 { 2098 .base.cra_name = "ecb(aes)", 2099 .base.cra_driver_name = "ecb-aes-s5p", 2100 .base.cra_priority = 100, 2101 .base.cra_flags = CRYPTO_ALG_ASYNC | 2102 CRYPTO_ALG_KERN_DRIVER_ONLY, 2103 .base.cra_blocksize = AES_BLOCK_SIZE, 2104 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2105 .base.cra_alignmask = 0x0f, 2106 .base.cra_module = THIS_MODULE, 2107 2108 .min_keysize = AES_MIN_KEY_SIZE, 2109 .max_keysize = AES_MAX_KEY_SIZE, 2110 .setkey = s5p_aes_setkey, 2111 .encrypt = s5p_aes_ecb_encrypt, 2112 .decrypt = s5p_aes_ecb_decrypt, 2113 .init = s5p_aes_init_tfm, 2114 }, 2115 { 2116 .base.cra_name = "cbc(aes)", 2117 .base.cra_driver_name = "cbc-aes-s5p", 2118 .base.cra_priority = 100, 2119 .base.cra_flags = CRYPTO_ALG_ASYNC | 2120 CRYPTO_ALG_KERN_DRIVER_ONLY, 2121 .base.cra_blocksize = AES_BLOCK_SIZE, 2122 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2123 .base.cra_alignmask = 0x0f, 2124 .base.cra_module = THIS_MODULE, 2125 2126 .min_keysize = AES_MIN_KEY_SIZE, 2127 .max_keysize = AES_MAX_KEY_SIZE, 2128 .ivsize = AES_BLOCK_SIZE, 2129 .setkey = s5p_aes_setkey, 2130 .encrypt = s5p_aes_cbc_encrypt, 2131 .decrypt = s5p_aes_cbc_decrypt, 2132 .init = s5p_aes_init_tfm, 2133 }, 2134 { 2135 .base.cra_name = "ctr(aes)", 2136 .base.cra_driver_name = "ctr-aes-s5p", 2137 .base.cra_priority = 100, 2138 .base.cra_flags = CRYPTO_ALG_ASYNC | 2139 CRYPTO_ALG_KERN_DRIVER_ONLY, 2140 .base.cra_blocksize = 1, 2141 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2142 .base.cra_alignmask = 0x0f, 2143 .base.cra_module = THIS_MODULE, 2144 2145 .min_keysize = AES_MIN_KEY_SIZE, 2146 .max_keysize = AES_MAX_KEY_SIZE, 2147 .ivsize = AES_BLOCK_SIZE, 2148 .setkey = s5p_aes_setkey, 2149 .encrypt = s5p_aes_ctr_crypt, 2150 .decrypt = s5p_aes_ctr_crypt, 2151 .init = s5p_aes_init_tfm, 2152 }, 2153}; 2154 2155static int s5p_aes_probe(struct platform_device *pdev) 2156{ 2157 struct device *dev = &pdev->dev; 2158 int i, j, err; 2159 const struct samsung_aes_variant *variant; 2160 struct s5p_aes_dev *pdata; 2161 struct resource *res; 2162 unsigned int hash_i; 2163 2164 if (s5p_dev) 2165 return -EEXIST; 2166 2167 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2168 if (!pdata) 2169 return -ENOMEM; 2170 2171 variant = find_s5p_sss_version(pdev); 2172 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2173 if (!res) 2174 return -EINVAL; 2175 2176 /* 2177 * Note: HASH and PRNG uses the same registers in secss, avoid 2178 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG 2179 * is enabled in config. We need larger size for HASH registers in 2180 * secss, current describe only AES/DES 2181 */ 2182 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) { 2183 if (variant == &exynos_aes_data) { 2184 res->end += 0x300; 2185 pdata->use_hash = true; 2186 } 2187 } 2188 2189 pdata->res = res; 2190 pdata->ioaddr = devm_ioremap_resource(dev, res); 2191 if (IS_ERR(pdata->ioaddr)) { 2192 if (!pdata->use_hash) 2193 return PTR_ERR(pdata->ioaddr); 2194 /* try AES without HASH */ 2195 res->end -= 0x300; 2196 pdata->use_hash = false; 2197 pdata->ioaddr = devm_ioremap_resource(dev, res); 2198 if (IS_ERR(pdata->ioaddr)) 2199 return PTR_ERR(pdata->ioaddr); 2200 } 2201 2202 pdata->clk = devm_clk_get(dev, variant->clk_names[0]); 2203 if (IS_ERR(pdata->clk)) 2204 return dev_err_probe(dev, PTR_ERR(pdata->clk), 2205 "failed to find secss clock %s\n", 2206 variant->clk_names[0]); 2207 2208 err = clk_prepare_enable(pdata->clk); 2209 if (err < 0) { 2210 dev_err(dev, "Enabling clock %s failed, err %d\n", 2211 variant->clk_names[0], err); 2212 return err; 2213 } 2214 2215 if (variant->clk_names[1]) { 2216 pdata->pclk = devm_clk_get(dev, variant->clk_names[1]); 2217 if (IS_ERR(pdata->pclk)) { 2218 err = dev_err_probe(dev, PTR_ERR(pdata->pclk), 2219 "failed to find clock %s\n", 2220 variant->clk_names[1]); 2221 goto err_clk; 2222 } 2223 2224 err = clk_prepare_enable(pdata->pclk); 2225 if (err < 0) { 2226 dev_err(dev, "Enabling clock %s failed, err %d\n", 2227 variant->clk_names[0], err); 2228 goto err_clk; 2229 } 2230 } else { 2231 pdata->pclk = NULL; 2232 } 2233 2234 spin_lock_init(&pdata->lock); 2235 spin_lock_init(&pdata->hash_lock); 2236 2237 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset; 2238 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset; 2239 2240 pdata->irq_fc = platform_get_irq(pdev, 0); 2241 if (pdata->irq_fc < 0) { 2242 err = pdata->irq_fc; 2243 dev_warn(dev, "feed control interrupt is not available.\n"); 2244 goto err_irq; 2245 } 2246 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL, 2247 s5p_aes_interrupt, IRQF_ONESHOT, 2248 pdev->name, pdev); 2249 if (err < 0) { 2250 dev_warn(dev, "feed control interrupt is not available.\n"); 2251 goto err_irq; 2252 } 2253 2254 pdata->busy = false; 2255 pdata->dev = dev; 2256 platform_set_drvdata(pdev, pdata); 2257 s5p_dev = pdata; 2258 2259 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); 2260 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); 2261 2262 for (i = 0; i < ARRAY_SIZE(algs); i++) { 2263 err = crypto_register_skcipher(&algs[i]); 2264 if (err) 2265 goto err_algs; 2266 } 2267 2268 if (pdata->use_hash) { 2269 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb, 2270 (unsigned long)pdata); 2271 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH); 2272 2273 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256); 2274 hash_i++) { 2275 struct ahash_alg *alg; 2276 2277 alg = &algs_sha1_md5_sha256[hash_i]; 2278 err = crypto_register_ahash(alg); 2279 if (err) { 2280 dev_err(dev, "can't register '%s': %d\n", 2281 alg->halg.base.cra_driver_name, err); 2282 goto err_hash; 2283 } 2284 } 2285 } 2286 2287 dev_info(dev, "s5p-sss driver registered\n"); 2288 2289 return 0; 2290 2291err_hash: 2292 for (j = hash_i - 1; j >= 0; j--) 2293 crypto_unregister_ahash(&algs_sha1_md5_sha256[j]); 2294 2295 tasklet_kill(&pdata->hash_tasklet); 2296 res->end -= 0x300; 2297 2298err_algs: 2299 if (i < ARRAY_SIZE(algs)) 2300 dev_err(dev, "can't register '%s': %d\n", algs[i].base.cra_name, 2301 err); 2302 2303 for (j = 0; j < i; j++) 2304 crypto_unregister_skcipher(&algs[j]); 2305 2306 tasklet_kill(&pdata->tasklet); 2307 2308err_irq: 2309 clk_disable_unprepare(pdata->pclk); 2310 2311err_clk: 2312 clk_disable_unprepare(pdata->clk); 2313 s5p_dev = NULL; 2314 2315 return err; 2316} 2317 2318static int s5p_aes_remove(struct platform_device *pdev) 2319{ 2320 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); 2321 int i; 2322 2323 for (i = 0; i < ARRAY_SIZE(algs); i++) 2324 crypto_unregister_skcipher(&algs[i]); 2325 2326 tasklet_kill(&pdata->tasklet); 2327 if (pdata->use_hash) { 2328 for (i = ARRAY_SIZE(algs_sha1_md5_sha256) - 1; i >= 0; i--) 2329 crypto_unregister_ahash(&algs_sha1_md5_sha256[i]); 2330 2331 pdata->res->end -= 0x300; 2332 tasklet_kill(&pdata->hash_tasklet); 2333 pdata->use_hash = false; 2334 } 2335 2336 clk_disable_unprepare(pdata->pclk); 2337 2338 clk_disable_unprepare(pdata->clk); 2339 s5p_dev = NULL; 2340 2341 return 0; 2342} 2343 2344static struct platform_driver s5p_aes_crypto = { 2345 .probe = s5p_aes_probe, 2346 .remove = s5p_aes_remove, 2347 .driver = { 2348 .name = "s5p-secss", 2349 .of_match_table = s5p_sss_dt_match, 2350 }, 2351}; 2352 2353module_platform_driver(s5p_aes_crypto); 2354 2355MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); 2356MODULE_LICENSE("GPL v2"); 2357MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); 2358MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>"); 2359