1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Intel Keem Bay OCS HCU Crypto Driver.
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 */
7
8#include <linux/dma-mapping.h>
9
10#ifndef _CRYPTO_OCS_HCU_H
11#define _CRYPTO_OCS_HCU_H
12
13#define OCS_HCU_DMA_BIT_MASK		DMA_BIT_MASK(32)
14
15#define OCS_HCU_HW_KEY_LEN		64
16
17struct ocs_hcu_dma_list;
18
19enum ocs_hcu_algo {
20	OCS_HCU_ALGO_SHA256 = 2,
21	OCS_HCU_ALGO_SHA224 = 3,
22	OCS_HCU_ALGO_SHA384 = 4,
23	OCS_HCU_ALGO_SHA512 = 5,
24	OCS_HCU_ALGO_SM3    = 6,
25};
26
27/**
28 * struct ocs_hcu_dev - OCS HCU device context.
29 * @list:	List of device contexts.
30 * @dev:	OCS HCU device.
31 * @io_base:	Base address of OCS HCU registers.
32 * @engine:	Crypto engine for the device.
33 * @irq:	IRQ number.
34 * @irq_done:	Completion for IRQ.
35 * @irq_err:	Flag indicating an IRQ error has happened.
36 */
37struct ocs_hcu_dev {
38	struct list_head list;
39	struct device *dev;
40	void __iomem *io_base;
41	struct crypto_engine *engine;
42	int irq;
43	struct completion irq_done;
44	bool irq_err;
45};
46
47/**
48 * struct ocs_hcu_idata - Intermediate data generated by the HCU.
49 * @msg_len_lo: Length of data the HCU has operated on in bits, low 32b.
50 * @msg_len_hi: Length of data the HCU has operated on in bits, high 32b.
51 * @digest: The digest read from the HCU. If the HCU is terminated, it will
52 *	    contain the actual hash digest. Otherwise it is the intermediate
53 *	    state.
54 */
55struct ocs_hcu_idata {
56	u32 msg_len_lo;
57	u32 msg_len_hi;
58	u8  digest[SHA512_DIGEST_SIZE];
59};
60
61/**
62 * struct ocs_hcu_hash_ctx - Context for OCS HCU hashing operation.
63 * @algo:	The hashing algorithm being used.
64 * @idata:	The current intermediate data.
65 */
66struct ocs_hcu_hash_ctx {
67	enum ocs_hcu_algo	algo;
68	struct ocs_hcu_idata	idata;
69};
70
71irqreturn_t ocs_hcu_irq_handler(int irq, void *dev_id);
72
73struct ocs_hcu_dma_list *ocs_hcu_dma_list_alloc(struct ocs_hcu_dev *hcu_dev,
74						int max_nents);
75
76void ocs_hcu_dma_list_free(struct ocs_hcu_dev *hcu_dev,
77			   struct ocs_hcu_dma_list *dma_list);
78
79int ocs_hcu_dma_list_add_tail(struct ocs_hcu_dev *hcu_dev,
80			      struct ocs_hcu_dma_list *dma_list,
81			      dma_addr_t addr, u32 len);
82
83int ocs_hcu_hash_init(struct ocs_hcu_hash_ctx *ctx, enum ocs_hcu_algo algo);
84
85int ocs_hcu_hash_update(struct ocs_hcu_dev *hcu_dev,
86			struct ocs_hcu_hash_ctx *ctx,
87			const struct ocs_hcu_dma_list *dma_list);
88
89int ocs_hcu_hash_finup(struct ocs_hcu_dev *hcu_dev,
90		       const struct ocs_hcu_hash_ctx *ctx,
91		       const struct ocs_hcu_dma_list *dma_list,
92		       u8 *dgst, size_t dgst_len);
93
94int ocs_hcu_hash_final(struct ocs_hcu_dev *hcu_dev,
95		       const struct ocs_hcu_hash_ctx *ctx, u8 *dgst,
96		       size_t dgst_len);
97
98int ocs_hcu_digest(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
99		   void *data, size_t data_len, u8 *dgst, size_t dgst_len);
100
101int ocs_hcu_hmac(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
102		 const u8 *key, size_t key_len,
103		 const struct ocs_hcu_dma_list *dma_list,
104		 u8 *dgst, size_t dgst_len);
105
106#endif /* _CRYPTO_OCS_HCU_H */
107