162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#ifndef _CCU_SUNIV_F1C100S_H_ 862306a36Sopenharmony_ci#define _CCU_SUNIV_F1C100S_H_ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include <dt-bindings/clock/suniv-ccu-f1c100s.h> 1162306a36Sopenharmony_ci#include <dt-bindings/reset/suniv-ccu-f1c100s.h> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#define CLK_PLL_CPU 0 1462306a36Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 1 1562306a36Sopenharmony_ci#define CLK_PLL_AUDIO 2 1662306a36Sopenharmony_ci#define CLK_PLL_AUDIO_2X 3 1762306a36Sopenharmony_ci#define CLK_PLL_AUDIO_4X 4 1862306a36Sopenharmony_ci#define CLK_PLL_AUDIO_8X 5 1962306a36Sopenharmony_ci#define CLK_PLL_VIDEO 6 2062306a36Sopenharmony_ci#define CLK_PLL_VIDEO_2X 7 2162306a36Sopenharmony_ci#define CLK_PLL_VE 8 2262306a36Sopenharmony_ci#define CLK_PLL_DDR0 9 2362306a36Sopenharmony_ci#define CLK_PLL_PERIPH 10 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci/* CPU clock is exported */ 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci#define CLK_AHB 12 2862306a36Sopenharmony_ci#define CLK_APB 13 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci/* All bus gates, DRAM gates and mod clocks are exported */ 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci#define CLK_NUMBER (CLK_IR + 1) 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci#endif /* _CCU_SUNIV_F1C100S_H_ */ 35