162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright 2016 Maxime Ripard 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Maxime Ripard <maxime.ripard@free-electrons.com> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef _CCU_SUN50I_A64_H_ 962306a36Sopenharmony_ci#define _CCU_SUN50I_A64_H_ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <dt-bindings/clock/sun50i-a64-ccu.h> 1262306a36Sopenharmony_ci#include <dt-bindings/reset/sun50i-a64-ccu.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci#define CLK_OSC_12M 0 1562306a36Sopenharmony_ci#define CLK_PLL_CPUX 1 1662306a36Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 2 1762306a36Sopenharmony_ci#define CLK_PLL_AUDIO 3 1862306a36Sopenharmony_ci#define CLK_PLL_AUDIO_2X 4 1962306a36Sopenharmony_ci#define CLK_PLL_AUDIO_4X 5 2062306a36Sopenharmony_ci#define CLK_PLL_AUDIO_8X 6 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci/* PLL_VIDEO0 exported for HDMI PHY */ 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci#define CLK_PLL_VIDEO0_2X 8 2562306a36Sopenharmony_ci#define CLK_PLL_VE 9 2662306a36Sopenharmony_ci#define CLK_PLL_DDR0 10 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci/* PLL_PERIPH0 exported for PRCM */ 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci#define CLK_PLL_PERIPH0_2X 12 3162306a36Sopenharmony_ci#define CLK_PLL_PERIPH1 13 3262306a36Sopenharmony_ci#define CLK_PLL_PERIPH1_2X 14 3362306a36Sopenharmony_ci#define CLK_PLL_VIDEO1 15 3462306a36Sopenharmony_ci#define CLK_PLL_GPU 16 3562306a36Sopenharmony_ci#define CLK_PLL_MIPI 17 3662306a36Sopenharmony_ci#define CLK_PLL_HSIC 18 3762306a36Sopenharmony_ci#define CLK_PLL_DE 19 3862306a36Sopenharmony_ci#define CLK_PLL_DDR1 20 3962306a36Sopenharmony_ci#define CLK_AXI 22 4062306a36Sopenharmony_ci#define CLK_APB 23 4162306a36Sopenharmony_ci#define CLK_AHB1 24 4262306a36Sopenharmony_ci#define CLK_APB1 25 4362306a36Sopenharmony_ci#define CLK_APB2 26 4462306a36Sopenharmony_ci#define CLK_AHB2 27 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci/* All the bus gates are exported */ 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci/* The first bunch of module clocks are exported */ 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci#define CLK_USB_OHCI0_12M 90 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci#define CLK_USB_OHCI1_12M 92 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci/* All the DRAM gates are exported */ 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci/* And the DSI and GPU module clock is exported */ 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci#define CLK_NUMBER (CLK_GPU + 1) 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci#endif /* _CCU_SUN50I_A64_H_ */ 61