162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef _CCU_SUN50I_A100_H_ 762306a36Sopenharmony_ci#define _CCU_SUN50I_A100_H_ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <dt-bindings/clock/sun50i-a100-ccu.h> 1062306a36Sopenharmony_ci#include <dt-bindings/reset/sun50i-a100-ccu.h> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci#define CLK_OSC12M 0 1362306a36Sopenharmony_ci#define CLK_PLL_CPUX 1 1462306a36Sopenharmony_ci#define CLK_PLL_DDR0 2 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci/* PLL_PERIPH0 exported for PRCM */ 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci#define CLK_PLL_PERIPH0_2X 4 1962306a36Sopenharmony_ci#define CLK_PLL_PERIPH1 5 2062306a36Sopenharmony_ci#define CLK_PLL_PERIPH1_2X 6 2162306a36Sopenharmony_ci#define CLK_PLL_GPU 7 2262306a36Sopenharmony_ci#define CLK_PLL_VIDEO0 8 2362306a36Sopenharmony_ci#define CLK_PLL_VIDEO0_2X 9 2462306a36Sopenharmony_ci#define CLK_PLL_VIDEO0_4X 10 2562306a36Sopenharmony_ci#define CLK_PLL_VIDEO1 11 2662306a36Sopenharmony_ci#define CLK_PLL_VIDEO1_2X 12 2762306a36Sopenharmony_ci#define CLK_PLL_VIDEO1_4X 13 2862306a36Sopenharmony_ci#define CLK_PLL_VIDEO2 14 2962306a36Sopenharmony_ci#define CLK_PLL_VIDEO2_2X 15 3062306a36Sopenharmony_ci#define CLK_PLL_VIDEO2_4X 16 3162306a36Sopenharmony_ci#define CLK_PLL_VIDEO3 17 3262306a36Sopenharmony_ci#define CLK_PLL_VIDEO3_2X 18 3362306a36Sopenharmony_ci#define CLK_PLL_VIDEO3_4X 19 3462306a36Sopenharmony_ci#define CLK_PLL_VE 20 3562306a36Sopenharmony_ci#define CLK_PLL_COM 21 3662306a36Sopenharmony_ci#define CLK_PLL_COM_AUDIO 22 3762306a36Sopenharmony_ci#define CLK_PLL_AUDIO 23 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci/* CPUX clock exported for DVFS */ 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci#define CLK_AXI 25 4262306a36Sopenharmony_ci#define CLK_CPUX_APB 26 4362306a36Sopenharmony_ci#define CLK_PSI_AHB1_AHB2 27 4462306a36Sopenharmony_ci#define CLK_AHB3 28 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci/* APB1 clock exported for PIO */ 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci#define CLK_APB2 30 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci/* All module clocks and bus gates are exported except DRAM */ 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci#define CLK_BUS_DRAM 58 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci#define CLK_NUMBER (CLK_CSI_ISP + 1) 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci#endif /* _CCU_SUN50I_A100_H_ */ 57