162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright 2017 Priit Laes 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Priit Laes <plaes@plaes.org> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef _CCU_SUN4I_A10_H_ 962306a36Sopenharmony_ci#define _CCU_SUN4I_A10_H_ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <dt-bindings/clock/sun4i-a10-ccu.h> 1262306a36Sopenharmony_ci#include <dt-bindings/clock/sun7i-a20-ccu.h> 1362306a36Sopenharmony_ci#include <dt-bindings/reset/sun4i-a10-ccu.h> 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci/* The HOSC is exported */ 1662306a36Sopenharmony_ci#define CLK_PLL_CORE 2 1762306a36Sopenharmony_ci#define CLK_PLL_AUDIO_BASE 3 1862306a36Sopenharmony_ci#define CLK_PLL_AUDIO 4 1962306a36Sopenharmony_ci#define CLK_PLL_AUDIO_2X 5 2062306a36Sopenharmony_ci#define CLK_PLL_AUDIO_4X 6 2162306a36Sopenharmony_ci#define CLK_PLL_AUDIO_8X 7 2262306a36Sopenharmony_ci#define CLK_PLL_VIDEO0 8 2362306a36Sopenharmony_ci/* The PLL_VIDEO0_2X clock is exported */ 2462306a36Sopenharmony_ci#define CLK_PLL_VE 10 2562306a36Sopenharmony_ci#define CLK_PLL_DDR_BASE 11 2662306a36Sopenharmony_ci#define CLK_PLL_DDR 12 2762306a36Sopenharmony_ci#define CLK_PLL_DDR_OTHER 13 2862306a36Sopenharmony_ci#define CLK_PLL_PERIPH_BASE 14 2962306a36Sopenharmony_ci#define CLK_PLL_PERIPH 15 3062306a36Sopenharmony_ci#define CLK_PLL_PERIPH_SATA 16 3162306a36Sopenharmony_ci#define CLK_PLL_VIDEO1 17 3262306a36Sopenharmony_ci/* The PLL_VIDEO1_2X clock is exported */ 3362306a36Sopenharmony_ci#define CLK_PLL_GPU 19 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci/* The CPU clock is exported */ 3662306a36Sopenharmony_ci#define CLK_AXI 21 3762306a36Sopenharmony_ci#define CLK_AXI_DRAM 22 3862306a36Sopenharmony_ci#define CLK_AHB 23 3962306a36Sopenharmony_ci#define CLK_APB0 24 4062306a36Sopenharmony_ci#define CLK_APB1 25 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci/* AHB gates are exported (23..68) */ 4362306a36Sopenharmony_ci/* APB0 gates are exported (69..78) */ 4462306a36Sopenharmony_ci/* APB1 gates are exported (79..95) */ 4562306a36Sopenharmony_ci/* IP module clocks are exported (96..128) */ 4662306a36Sopenharmony_ci/* DRAM gates are exported (129..142)*/ 4762306a36Sopenharmony_ci/* Media (display engine clocks & etc) are exported (143..169) */ 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_ci#define CLK_NUMBER_SUN4I (CLK_MBUS + 1) 5062306a36Sopenharmony_ci#define CLK_NUMBER_SUN7I (CLK_OUT_B + 1) 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci#endif /* _CCU_SUN4I_A10_H_ */ 53