1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2/* 3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved 4 * 5 * Configuration settings for the STM32MP13x CPU 6 */ 7 8#ifndef STM32MP13_RCC_H 9#define STM32MP13_RCC_H 10/* RCC registers */ 11#define RCC_SECCFGR 0x0 12#define RCC_MP_SREQSETR 0x100 13#define RCC_MP_SREQCLRR 0x104 14#define RCC_MP_APRSTCR 0x108 15#define RCC_MP_APRSTSR 0x10c 16#define RCC_PWRLPDLYCR 0x110 17#define RCC_MP_GRSTCSETR 0x114 18#define RCC_BR_RSTSCLRR 0x118 19#define RCC_MP_RSTSSETR 0x11c 20#define RCC_MP_RSTSCLRR 0x120 21#define RCC_MP_IWDGFZSETR 0x124 22#define RCC_MP_IWDGFZCLRR 0x128 23#define RCC_MP_CIER 0x200 24#define RCC_MP_CIFR 0x204 25#define RCC_BDCR 0x400 26#define RCC_RDLSICR 0x404 27#define RCC_OCENSETR 0x420 28#define RCC_OCENCLRR 0x424 29#define RCC_OCRDYR 0x428 30#define RCC_HSICFGR 0x440 31#define RCC_CSICFGR 0x444 32#define RCC_MCO1CFGR 0x460 33#define RCC_MCO2CFGR 0x464 34#define RCC_DBGCFGR 0x468 35#define RCC_RCK12SELR 0x480 36#define RCC_RCK3SELR 0x484 37#define RCC_RCK4SELR 0x488 38#define RCC_PLL1CR 0x4a0 39#define RCC_PLL1CFGR1 0x4a4 40#define RCC_PLL1CFGR2 0x4a8 41#define RCC_PLL1FRACR 0x4ac 42#define RCC_PLL1CSGR 0x4b0 43#define RCC_PLL2CR 0x4d0 44#define RCC_PLL2CFGR1 0x4d4 45#define RCC_PLL2CFGR2 0x4d8 46#define RCC_PLL2FRACR 0x4dc 47#define RCC_PLL2CSGR 0x4e0 48#define RCC_PLL3CR 0x500 49#define RCC_PLL3CFGR1 0x504 50#define RCC_PLL3CFGR2 0x508 51#define RCC_PLL3FRACR 0x50c 52#define RCC_PLL3CSGR 0x510 53#define RCC_PLL4CR 0x520 54#define RCC_PLL4CFGR1 0x524 55#define RCC_PLL4CFGR2 0x528 56#define RCC_PLL4FRACR 0x52c 57#define RCC_PLL4CSGR 0x530 58#define RCC_MPCKSELR 0x540 59#define RCC_ASSCKSELR 0x544 60#define RCC_MSSCKSELR 0x548 61#define RCC_CPERCKSELR 0x54c 62#define RCC_RTCDIVR 0x560 63#define RCC_MPCKDIVR 0x564 64#define RCC_AXIDIVR 0x568 65#define RCC_MLAHBDIVR 0x56c 66#define RCC_APB1DIVR 0x570 67#define RCC_APB2DIVR 0x574 68#define RCC_APB3DIVR 0x578 69#define RCC_APB4DIVR 0x57c 70#define RCC_APB5DIVR 0x580 71#define RCC_APB6DIVR 0x584 72#define RCC_TIMG1PRER 0x5a0 73#define RCC_TIMG2PRER 0x5a4 74#define RCC_TIMG3PRER 0x5a8 75#define RCC_DDRITFCR 0x5c0 76#define RCC_I2C12CKSELR 0x600 77#define RCC_I2C345CKSELR 0x604 78#define RCC_SPI2S1CKSELR 0x608 79#define RCC_SPI2S23CKSELR 0x60c 80#define RCC_SPI45CKSELR 0x610 81#define RCC_UART12CKSELR 0x614 82#define RCC_UART35CKSELR 0x618 83#define RCC_UART4CKSELR 0x61c 84#define RCC_UART6CKSELR 0x620 85#define RCC_UART78CKSELR 0x624 86#define RCC_LPTIM1CKSELR 0x628 87#define RCC_LPTIM23CKSELR 0x62c 88#define RCC_LPTIM45CKSELR 0x630 89#define RCC_SAI1CKSELR 0x634 90#define RCC_SAI2CKSELR 0x638 91#define RCC_FDCANCKSELR 0x63c 92#define RCC_SPDIFCKSELR 0x640 93#define RCC_ADC12CKSELR 0x644 94#define RCC_SDMMC12CKSELR 0x648 95#define RCC_ETH12CKSELR 0x64c 96#define RCC_USBCKSELR 0x650 97#define RCC_QSPICKSELR 0x654 98#define RCC_FMCCKSELR 0x658 99#define RCC_RNG1CKSELR 0x65c 100#define RCC_STGENCKSELR 0x660 101#define RCC_DCMIPPCKSELR 0x664 102#define RCC_SAESCKSELR 0x668 103#define RCC_APB1RSTSETR 0x6a0 104#define RCC_APB1RSTCLRR 0x6a4 105#define RCC_APB2RSTSETR 0x6a8 106#define RCC_APB2RSTCLRR 0x6ac 107#define RCC_APB3RSTSETR 0x6b0 108#define RCC_APB3RSTCLRR 0x6b4 109#define RCC_APB4RSTSETR 0x6b8 110#define RCC_APB4RSTCLRR 0x6bc 111#define RCC_APB5RSTSETR 0x6c0 112#define RCC_APB5RSTCLRR 0x6c4 113#define RCC_APB6RSTSETR 0x6c8 114#define RCC_APB6RSTCLRR 0x6cc 115#define RCC_AHB2RSTSETR 0x6d0 116#define RCC_AHB2RSTCLRR 0x6d4 117#define RCC_AHB4RSTSETR 0x6e0 118#define RCC_AHB4RSTCLRR 0x6e4 119#define RCC_AHB5RSTSETR 0x6e8 120#define RCC_AHB5RSTCLRR 0x6ec 121#define RCC_AHB6RSTSETR 0x6f0 122#define RCC_AHB6RSTCLRR 0x6f4 123#define RCC_MP_APB1ENSETR 0x700 124#define RCC_MP_APB1ENCLRR 0x704 125#define RCC_MP_APB2ENSETR 0x708 126#define RCC_MP_APB2ENCLRR 0x70c 127#define RCC_MP_APB3ENSETR 0x710 128#define RCC_MP_APB3ENCLRR 0x714 129#define RCC_MP_S_APB3ENSETR 0x718 130#define RCC_MP_S_APB3ENCLRR 0x71c 131#define RCC_MP_NS_APB3ENSETR 0x720 132#define RCC_MP_NS_APB3ENCLRR 0x724 133#define RCC_MP_APB4ENSETR 0x728 134#define RCC_MP_APB4ENCLRR 0x72c 135#define RCC_MP_S_APB4ENSETR 0x730 136#define RCC_MP_S_APB4ENCLRR 0x734 137#define RCC_MP_NS_APB4ENSETR 0x738 138#define RCC_MP_NS_APB4ENCLRR 0x73c 139#define RCC_MP_APB5ENSETR 0x740 140#define RCC_MP_APB5ENCLRR 0x744 141#define RCC_MP_APB6ENSETR 0x748 142#define RCC_MP_APB6ENCLRR 0x74c 143#define RCC_MP_AHB2ENSETR 0x750 144#define RCC_MP_AHB2ENCLRR 0x754 145#define RCC_MP_AHB4ENSETR 0x760 146#define RCC_MP_AHB4ENCLRR 0x764 147#define RCC_MP_S_AHB4ENSETR 0x768 148#define RCC_MP_S_AHB4ENCLRR 0x76c 149#define RCC_MP_NS_AHB4ENSETR 0x770 150#define RCC_MP_NS_AHB4ENCLRR 0x774 151#define RCC_MP_AHB5ENSETR 0x778 152#define RCC_MP_AHB5ENCLRR 0x77c 153#define RCC_MP_AHB6ENSETR 0x780 154#define RCC_MP_AHB6ENCLRR 0x784 155#define RCC_MP_S_AHB6ENSETR 0x788 156#define RCC_MP_S_AHB6ENCLRR 0x78c 157#define RCC_MP_NS_AHB6ENSETR 0x790 158#define RCC_MP_NS_AHB6ENCLRR 0x794 159#define RCC_MP_APB1LPENSETR 0x800 160#define RCC_MP_APB1LPENCLRR 0x804 161#define RCC_MP_APB2LPENSETR 0x808 162#define RCC_MP_APB2LPENCLRR 0x80c 163#define RCC_MP_APB3LPENSETR 0x810 164#define RCC_MP_APB3LPENCLRR 0x814 165#define RCC_MP_S_APB3LPENSETR 0x818 166#define RCC_MP_S_APB3LPENCLRR 0x81c 167#define RCC_MP_NS_APB3LPENSETR 0x820 168#define RCC_MP_NS_APB3LPENCLRR 0x824 169#define RCC_MP_APB4LPENSETR 0x828 170#define RCC_MP_APB4LPENCLRR 0x82c 171#define RCC_MP_S_APB4LPENSETR 0x830 172#define RCC_MP_S_APB4LPENCLRR 0x834 173#define RCC_MP_NS_APB4LPENSETR 0x838 174#define RCC_MP_NS_APB4LPENCLRR 0x83c 175#define RCC_MP_APB5LPENSETR 0x840 176#define RCC_MP_APB5LPENCLRR 0x844 177#define RCC_MP_APB6LPENSETR 0x848 178#define RCC_MP_APB6LPENCLRR 0x84c 179#define RCC_MP_AHB2LPENSETR 0x850 180#define RCC_MP_AHB2LPENCLRR 0x854 181#define RCC_MP_AHB4LPENSETR 0x858 182#define RCC_MP_AHB4LPENCLRR 0x85c 183#define RCC_MP_S_AHB4LPENSETR 0x868 184#define RCC_MP_S_AHB4LPENCLRR 0x86c 185#define RCC_MP_NS_AHB4LPENSETR 0x870 186#define RCC_MP_NS_AHB4LPENCLRR 0x874 187#define RCC_MP_AHB5LPENSETR 0x878 188#define RCC_MP_AHB5LPENCLRR 0x87c 189#define RCC_MP_AHB6LPENSETR 0x880 190#define RCC_MP_AHB6LPENCLRR 0x884 191#define RCC_MP_S_AHB6LPENSETR 0x888 192#define RCC_MP_S_AHB6LPENCLRR 0x88c 193#define RCC_MP_NS_AHB6LPENSETR 0x890 194#define RCC_MP_NS_AHB6LPENCLRR 0x894 195#define RCC_MP_S_AXIMLPENSETR 0x898 196#define RCC_MP_S_AXIMLPENCLRR 0x89c 197#define RCC_MP_NS_AXIMLPENSETR 0x8a0 198#define RCC_MP_NS_AXIMLPENCLRR 0x8a4 199#define RCC_MP_MLAHBLPENSETR 0x8a8 200#define RCC_MP_MLAHBLPENCLRR 0x8ac 201#define RCC_APB3SECSR 0x8c0 202#define RCC_APB4SECSR 0x8c4 203#define RCC_APB5SECSR 0x8c8 204#define RCC_APB6SECSR 0x8cc 205#define RCC_AHB2SECSR 0x8d0 206#define RCC_AHB4SECSR 0x8d4 207#define RCC_AHB5SECSR 0x8d8 208#define RCC_AHB6SECSR 0x8dc 209#define RCC_VERR 0xff4 210#define RCC_IDR 0xff8 211#define RCC_SIDR 0xffc 212 213/* RCC_SECCFGR register fields */ 214#define RCC_SECCFGR_HSISEC 0 215#define RCC_SECCFGR_CSISEC 1 216#define RCC_SECCFGR_HSESEC 2 217#define RCC_SECCFGR_LSISEC 3 218#define RCC_SECCFGR_LSESEC 4 219#define RCC_SECCFGR_PLL12SEC 8 220#define RCC_SECCFGR_PLL3SEC 9 221#define RCC_SECCFGR_PLL4SEC 10 222#define RCC_SECCFGR_MPUSEC 11 223#define RCC_SECCFGR_AXISEC 12 224#define RCC_SECCFGR_MLAHBSEC 13 225#define RCC_SECCFGR_APB3DIVSEC 16 226#define RCC_SECCFGR_APB4DIVSEC 17 227#define RCC_SECCFGR_APB5DIVSEC 18 228#define RCC_SECCFGR_APB6DIVSEC 19 229#define RCC_SECCFGR_TIMG3SEC 20 230#define RCC_SECCFGR_CPERSEC 21 231#define RCC_SECCFGR_MCO1SEC 22 232#define RCC_SECCFGR_MCO2SEC 23 233#define RCC_SECCFGR_STPSEC 24 234#define RCC_SECCFGR_RSTSEC 25 235#define RCC_SECCFGR_PWRSEC 31 236 237/* RCC_MP_SREQSETR register fields */ 238#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) 239 240/* RCC_MP_SREQCLRR register fields */ 241#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) 242 243/* RCC_MP_APRSTCR register fields */ 244#define RCC_MP_APRSTCR_RDCTLEN BIT(0) 245#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) 246#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 247 248/* RCC_MP_APRSTSR register fields */ 249#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) 250#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 251 252/* RCC_PWRLPDLYCR register fields */ 253#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) 254#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 255 256/* RCC_MP_GRSTCSETR register fields */ 257#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) 258#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) 259 260/* RCC_BR_RSTSCLRR register fields */ 261#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) 262#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) 263#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) 264#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) 265#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) 266#define RCC_BR_RSTSCLRR_VCPURSTF BIT(5) 267#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) 268#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) 269#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) 270#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) 271 272/* RCC_MP_RSTSSETR register fields */ 273#define RCC_MP_RSTSSETR_PORRSTF BIT(0) 274#define RCC_MP_RSTSSETR_BORRSTF BIT(1) 275#define RCC_MP_RSTSSETR_PADRSTF BIT(2) 276#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) 277#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) 278#define RCC_MP_RSTSSETR_VCPURSTF BIT(5) 279#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) 280#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) 281#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) 282#define RCC_MP_RSTSSETR_STP2RSTF BIT(10) 283#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) 284#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) 285#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) 286#define RCC_MP_RSTSSETR_SPARE BIT(15) 287 288/* RCC_MP_RSTSCLRR register fields */ 289#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) 290#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) 291#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) 292#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) 293#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) 294#define RCC_MP_RSTSCLRR_VCPURSTF BIT(5) 295#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) 296#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) 297#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) 298#define RCC_MP_RSTSCLRR_STP2RSTF BIT(10) 299#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) 300#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) 301#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) 302#define RCC_MP_RSTSCLRR_SPARE BIT(15) 303 304/* RCC_MP_IWDGFZSETR register fields */ 305#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) 306#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) 307 308/* RCC_MP_IWDGFZCLRR register fields */ 309#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) 310#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) 311 312/* RCC_MP_CIER register fields */ 313#define RCC_MP_CIER_LSIRDYIE BIT(0) 314#define RCC_MP_CIER_LSERDYIE BIT(1) 315#define RCC_MP_CIER_HSIRDYIE BIT(2) 316#define RCC_MP_CIER_HSERDYIE BIT(3) 317#define RCC_MP_CIER_CSIRDYIE BIT(4) 318#define RCC_MP_CIER_PLL1DYIE BIT(8) 319#define RCC_MP_CIER_PLL2DYIE BIT(9) 320#define RCC_MP_CIER_PLL3DYIE BIT(10) 321#define RCC_MP_CIER_PLL4DYIE BIT(11) 322#define RCC_MP_CIER_LSECSSIE BIT(16) 323#define RCC_MP_CIER_WKUPIE BIT(20) 324 325/* RCC_MP_CIFR register fields */ 326#define RCC_MP_CIFR_LSIRDYF BIT(0) 327#define RCC_MP_CIFR_LSERDYF BIT(1) 328#define RCC_MP_CIFR_HSIRDYF BIT(2) 329#define RCC_MP_CIFR_HSERDYF BIT(3) 330#define RCC_MP_CIFR_CSIRDYF BIT(4) 331#define RCC_MP_CIFR_PLL1DYF BIT(8) 332#define RCC_MP_CIFR_PLL2DYF BIT(9) 333#define RCC_MP_CIFR_PLL3DYF BIT(10) 334#define RCC_MP_CIFR_PLL4DYF BIT(11) 335#define RCC_MP_CIFR_LSECSSF BIT(16) 336#define RCC_MP_CIFR_WKUPF BIT(20) 337 338/* RCC_BDCR register fields */ 339#define RCC_BDCR_LSEON BIT(0) 340#define RCC_BDCR_LSEBYP BIT(1) 341#define RCC_BDCR_LSERDY BIT(2) 342#define RCC_BDCR_DIGBYP BIT(3) 343#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) 344#define RCC_BDCR_LSECSSON BIT(8) 345#define RCC_BDCR_LSECSSD BIT(9) 346#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) 347#define RCC_BDCR_RTCCKEN BIT(20) 348#define RCC_BDCR_VSWRST BIT(31) 349#define RCC_BDCR_LSEDRV_SHIFT 4 350#define RCC_BDCR_RTCSRC_SHIFT 16 351 352/* RCC_RDLSICR register fields */ 353#define RCC_RDLSICR_LSION BIT(0) 354#define RCC_RDLSICR_LSIRDY BIT(1) 355#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) 356#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) 357#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) 358#define RCC_RDLSICR_MRD_SHIFT 16 359#define RCC_RDLSICR_EADLY_SHIFT 24 360#define RCC_RDLSICR_SPARE_SHIFT 27 361 362/* RCC_OCENSETR register fields */ 363#define RCC_OCENSETR_HSION BIT(0) 364#define RCC_OCENSETR_HSIKERON BIT(1) 365#define RCC_OCENSETR_CSION BIT(4) 366#define RCC_OCENSETR_CSIKERON BIT(5) 367#define RCC_OCENSETR_DIGBYP BIT(7) 368#define RCC_OCENSETR_HSEON BIT(8) 369#define RCC_OCENSETR_HSEKERON BIT(9) 370#define RCC_OCENSETR_HSEBYP BIT(10) 371#define RCC_OCENSETR_HSECSSON BIT(11) 372 373/* RCC_OCENCLRR register fields */ 374#define RCC_OCENCLRR_HSION BIT(0) 375#define RCC_OCENCLRR_HSIKERON BIT(1) 376#define RCC_OCENCLRR_CSION BIT(4) 377#define RCC_OCENCLRR_CSIKERON BIT(5) 378#define RCC_OCENCLRR_DIGBYP BIT(7) 379#define RCC_OCENCLRR_HSEON BIT(8) 380#define RCC_OCENCLRR_HSEKERON BIT(9) 381#define RCC_OCENCLRR_HSEBYP BIT(10) 382 383/* RCC_OCRDYR register fields */ 384#define RCC_OCRDYR_HSIRDY BIT(0) 385#define RCC_OCRDYR_HSIDIVRDY BIT(2) 386#define RCC_OCRDYR_CSIRDY BIT(4) 387#define RCC_OCRDYR_HSERDY BIT(8) 388#define RCC_OCRDYR_MPUCKRDY BIT(23) 389#define RCC_OCRDYR_AXICKRDY BIT(24) 390 391/* RCC_HSICFGR register fields */ 392#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) 393#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) 394#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16) 395#define RCC_HSICFGR_HSIDIV_SHIFT 0 396#define RCC_HSICFGR_HSITRIM_SHIFT 8 397#define RCC_HSICFGR_HSICAL_SHIFT 16 398 399/* RCC_CSICFGR register fields */ 400#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) 401#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) 402#define RCC_CSICFGR_CSITRIM_SHIFT 8 403#define RCC_CSICFGR_CSICAL_SHIFT 16 404 405/* RCC_MCO1CFGR register fields */ 406#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) 407#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) 408#define RCC_MCO1CFGR_MCO1ON BIT(12) 409#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 410#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 411 412/* RCC_MCO2CFGR register fields */ 413#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) 414#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) 415#define RCC_MCO2CFGR_MCO2ON BIT(12) 416#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 417#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 418 419/* RCC_DBGCFGR register fields */ 420#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) 421#define RCC_DBGCFGR_DBGCKEN BIT(8) 422#define RCC_DBGCFGR_TRACECKEN BIT(9) 423#define RCC_DBGCFGR_DBGRST BIT(12) 424#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 425 426/* RCC_RCK12SELR register fields */ 427#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) 428#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) 429#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 430 431/* RCC_RCK3SELR register fields */ 432#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) 433#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) 434#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 435 436/* RCC_RCK4SELR register fields */ 437#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) 438#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) 439#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 440 441/* RCC_PLL1CR register fields */ 442#define RCC_PLL1CR_PLLON BIT(0) 443#define RCC_PLL1CR_PLL1RDY BIT(1) 444#define RCC_PLL1CR_SSCG_CTRL BIT(2) 445#define RCC_PLL1CR_DIVPEN BIT(4) 446#define RCC_PLL1CR_DIVQEN BIT(5) 447#define RCC_PLL1CR_DIVREN BIT(6) 448 449/* RCC_PLL1CFGR1 register fields */ 450#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) 451#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) 452#define RCC_PLL1CFGR1_DIVN_SHIFT 0 453#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 454 455/* RCC_PLL1CFGR2 register fields */ 456#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) 457#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) 458#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) 459#define RCC_PLL1CFGR2_DIVP_SHIFT 0 460#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 461#define RCC_PLL1CFGR2_DIVR_SHIFT 16 462 463/* RCC_PLL1FRACR register fields */ 464#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) 465#define RCC_PLL1FRACR_FRACLE BIT(16) 466#define RCC_PLL1FRACR_FRACV_SHIFT 3 467 468/* RCC_PLL1CSGR register fields */ 469#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) 470#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) 471#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) 472#define RCC_PLL1CSGR_SSCG_MODE BIT(15) 473#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) 474#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 475#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 476 477/* RCC_PLL2CR register fields */ 478#define RCC_PLL2CR_PLLON BIT(0) 479#define RCC_PLL2CR_PLL2RDY BIT(1) 480#define RCC_PLL2CR_SSCG_CTRL BIT(2) 481#define RCC_PLL2CR_DIVPEN BIT(4) 482#define RCC_PLL2CR_DIVQEN BIT(5) 483#define RCC_PLL2CR_DIVREN BIT(6) 484 485/* RCC_PLL2CFGR1 register fields */ 486#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) 487#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) 488#define RCC_PLL2CFGR1_DIVN_SHIFT 0 489#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 490 491/* RCC_PLL2CFGR2 register fields */ 492#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) 493#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) 494#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) 495#define RCC_PLL2CFGR2_DIVP_SHIFT 0 496#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 497#define RCC_PLL2CFGR2_DIVR_SHIFT 16 498 499/* RCC_PLL2FRACR register fields */ 500#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) 501#define RCC_PLL2FRACR_FRACLE BIT(16) 502#define RCC_PLL2FRACR_FRACV_SHIFT 3 503 504/* RCC_PLL2CSGR register fields */ 505#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) 506#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) 507#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) 508#define RCC_PLL2CSGR_SSCG_MODE BIT(15) 509#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) 510#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 511#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 512 513/* RCC_PLL3CR register fields */ 514#define RCC_PLL3CR_PLLON BIT(0) 515#define RCC_PLL3CR_PLL3RDY BIT(1) 516#define RCC_PLL3CR_SSCG_CTRL BIT(2) 517#define RCC_PLL3CR_DIVPEN BIT(4) 518#define RCC_PLL3CR_DIVQEN BIT(5) 519#define RCC_PLL3CR_DIVREN BIT(6) 520 521/* RCC_PLL3CFGR1 register fields */ 522#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) 523#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) 524#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) 525#define RCC_PLL3CFGR1_DIVN_SHIFT 0 526#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 527#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 528 529/* RCC_PLL3CFGR2 register fields */ 530#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) 531#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) 532#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) 533#define RCC_PLL3CFGR2_DIVP_SHIFT 0 534#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 535#define RCC_PLL3CFGR2_DIVR_SHIFT 16 536 537/* RCC_PLL3FRACR register fields */ 538#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) 539#define RCC_PLL3FRACR_FRACLE BIT(16) 540#define RCC_PLL3FRACR_FRACV_SHIFT 3 541 542/* RCC_PLL3CSGR register fields */ 543#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) 544#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) 545#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) 546#define RCC_PLL3CSGR_SSCG_MODE BIT(15) 547#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) 548#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 549#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 550 551/* RCC_PLL4CR register fields */ 552#define RCC_PLL4CR_PLLON BIT(0) 553#define RCC_PLL4CR_PLL4RDY BIT(1) 554#define RCC_PLL4CR_SSCG_CTRL BIT(2) 555#define RCC_PLL4CR_DIVPEN BIT(4) 556#define RCC_PLL4CR_DIVQEN BIT(5) 557#define RCC_PLL4CR_DIVREN BIT(6) 558 559/* RCC_PLL4CFGR1 register fields */ 560#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) 561#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) 562#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) 563#define RCC_PLL4CFGR1_DIVN_SHIFT 0 564#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 565#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 566 567/* RCC_PLL4CFGR2 register fields */ 568#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) 569#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) 570#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) 571#define RCC_PLL4CFGR2_DIVP_SHIFT 0 572#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 573#define RCC_PLL4CFGR2_DIVR_SHIFT 16 574 575/* RCC_PLL4FRACR register fields */ 576#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) 577#define RCC_PLL4FRACR_FRACLE BIT(16) 578#define RCC_PLL4FRACR_FRACV_SHIFT 3 579 580/* RCC_PLL4CSGR register fields */ 581#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) 582#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) 583#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) 584#define RCC_PLL4CSGR_SSCG_MODE BIT(15) 585#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) 586#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 587#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 588 589/* RCC_MPCKSELR register fields */ 590#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) 591#define RCC_MPCKSELR_MPUSRCRDY BIT(31) 592#define RCC_MPCKSELR_MPUSRC_SHIFT 0 593 594/* RCC_ASSCKSELR register fields */ 595#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) 596#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) 597#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 598 599/* RCC_MSSCKSELR register fields */ 600#define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0) 601#define RCC_MSSCKSELR_MLAHBSSRCRDY BIT(31) 602#define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0 603 604/* RCC_CPERCKSELR register fields */ 605#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) 606#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 607 608/* RCC_RTCDIVR register fields */ 609#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) 610#define RCC_RTCDIVR_RTCDIV_SHIFT 0 611 612/* RCC_MPCKDIVR register fields */ 613#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0) 614#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) 615#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 616 617/* RCC_AXIDIVR register fields */ 618#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) 619#define RCC_AXIDIVR_AXIDIVRDY BIT(31) 620#define RCC_AXIDIVR_AXIDIV_SHIFT 0 621 622/* RCC_MLAHBDIVR register fields */ 623#define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0) 624#define RCC_MLAHBDIVR_MLAHBDIVRDY BIT(31) 625#define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0 626 627/* RCC_APB1DIVR register fields */ 628#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) 629#define RCC_APB1DIVR_APB1DIVRDY BIT(31) 630#define RCC_APB1DIVR_APB1DIV_SHIFT 0 631 632/* RCC_APB2DIVR register fields */ 633#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) 634#define RCC_APB2DIVR_APB2DIVRDY BIT(31) 635#define RCC_APB2DIVR_APB2DIV_SHIFT 0 636 637/* RCC_APB3DIVR register fields */ 638#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) 639#define RCC_APB3DIVR_APB3DIVRDY BIT(31) 640#define RCC_APB3DIVR_APB3DIV_SHIFT 0 641 642/* RCC_APB4DIVR register fields */ 643#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) 644#define RCC_APB4DIVR_APB4DIVRDY BIT(31) 645#define RCC_APB4DIVR_APB4DIV_SHIFT 0 646 647/* RCC_APB5DIVR register fields */ 648#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) 649#define RCC_APB5DIVR_APB5DIVRDY BIT(31) 650#define RCC_APB5DIVR_APB5DIV_SHIFT 0 651 652/* RCC_APB6DIVR register fields */ 653#define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0) 654#define RCC_APB6DIVR_APB6DIVRDY BIT(31) 655#define RCC_APB6DIVR_APB6DIV_SHIFT 0 656 657/* RCC_TIMG1PRER register fields */ 658#define RCC_TIMG1PRER_TIMG1PRE BIT(0) 659#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) 660 661/* RCC_TIMG2PRER register fields */ 662#define RCC_TIMG2PRER_TIMG2PRE BIT(0) 663#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) 664 665/* RCC_TIMG3PRER register fields */ 666#define RCC_TIMG3PRER_TIMG3PRE BIT(0) 667#define RCC_TIMG3PRER_TIMG3PRERDY BIT(31) 668 669/* RCC_DDRITFCR register fields */ 670#define RCC_DDRITFCR_DDRC1EN BIT(0) 671#define RCC_DDRITFCR_DDRC1LPEN BIT(1) 672#define RCC_DDRITFCR_DDRPHYCEN BIT(4) 673#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) 674#define RCC_DDRITFCR_DDRCAPBEN BIT(6) 675#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) 676#define RCC_DDRITFCR_AXIDCGEN BIT(8) 677#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) 678#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) 679#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) 680#define RCC_DDRITFCR_DDRCAPBRST BIT(14) 681#define RCC_DDRITFCR_DDRCAXIRST BIT(15) 682#define RCC_DDRITFCR_DDRCORERST BIT(16) 683#define RCC_DDRITFCR_DPHYAPBRST BIT(17) 684#define RCC_DDRITFCR_DPHYRST BIT(18) 685#define RCC_DDRITFCR_DPHYCTLRST BIT(19) 686#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) 687#define RCC_DDRITFCR_GSKPMOD BIT(23) 688#define RCC_DDRITFCR_GSKPCTRL BIT(24) 689#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) 690#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) 691#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 692#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 693#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 694#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 695 696/* RCC_I2C12CKSELR register fields */ 697#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) 698#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 699 700/* RCC_I2C345CKSELR register fields */ 701#define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0) 702#define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3) 703#define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6) 704#define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0 705#define RCC_I2C345CKSELR_I2C4SRC_SHIFT 3 706#define RCC_I2C345CKSELR_I2C5SRC_SHIFT 6 707 708/* RCC_SPI2S1CKSELR register fields */ 709#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) 710#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 711 712/* RCC_SPI2S23CKSELR register fields */ 713#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) 714#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 715 716/* RCC_SPI45CKSELR register fields */ 717#define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0) 718#define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3) 719#define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0 720#define RCC_SPI45CKSELR_SPI5SRC_SHIFT 3 721 722/* RCC_UART12CKSELR register fields */ 723#define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0) 724#define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3) 725#define RCC_UART12CKSELR_UART1SRC_SHIFT 0 726#define RCC_UART12CKSELR_UART2SRC_SHIFT 3 727 728/* RCC_UART35CKSELR register fields */ 729#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) 730#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 731 732/* RCC_UART4CKSELR register fields */ 733#define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0) 734#define RCC_UART4CKSELR_UART4SRC_SHIFT 0 735 736/* RCC_UART6CKSELR register fields */ 737#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) 738#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 739 740/* RCC_UART78CKSELR register fields */ 741#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) 742#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 743 744/* RCC_LPTIM1CKSELR register fields */ 745#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) 746#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 747 748/* RCC_LPTIM23CKSELR register fields */ 749#define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0) 750#define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3) 751#define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0 752#define RCC_LPTIM23CKSELR_LPTIM3SRC_SHIFT 3 753 754/* RCC_LPTIM45CKSELR register fields */ 755#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) 756#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 757 758/* RCC_SAI1CKSELR register fields */ 759#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) 760#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 761 762/* RCC_SAI2CKSELR register fields */ 763#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) 764#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 765 766/* RCC_FDCANCKSELR register fields */ 767#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) 768#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 769 770/* RCC_SPDIFCKSELR register fields */ 771#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) 772#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 773 774/* RCC_ADC12CKSELR register fields */ 775#define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0) 776#define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2) 777#define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0 778#define RCC_ADC12CKSELR_ADC2SRC_SHIFT 2 779 780/* RCC_SDMMC12CKSELR register fields */ 781#define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0) 782#define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3) 783#define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0 784#define RCC_SDMMC12CKSELR_SDMMC2SRC_SHIFT 3 785 786/* RCC_ETH12CKSELR register fields */ 787#define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0) 788#define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4) 789#define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8) 790#define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12) 791#define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0 792#define RCC_ETH12CKSELR_ETH1PTPDIV_SHIFT 4 793#define RCC_ETH12CKSELR_ETH2SRC_SHIFT 8 794#define RCC_ETH12CKSELR_ETH2PTPDIV_SHIFT 12 795 796/* RCC_USBCKSELR register fields */ 797#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) 798#define RCC_USBCKSELR_USBOSRC BIT(4) 799#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 800 801/* RCC_QSPICKSELR register fields */ 802#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) 803#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 804 805/* RCC_FMCCKSELR register fields */ 806#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) 807#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 808 809/* RCC_RNG1CKSELR register fields */ 810#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) 811#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 812 813/* RCC_STGENCKSELR register fields */ 814#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) 815#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 816 817/* RCC_DCMIPPCKSELR register fields */ 818#define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0) 819#define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0 820 821/* RCC_SAESCKSELR register fields */ 822#define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0) 823#define RCC_SAESCKSELR_SAESSRC_SHIFT 0 824 825/* RCC_APB1RSTSETR register fields */ 826#define RCC_APB1RSTSETR_TIM2RST BIT(0) 827#define RCC_APB1RSTSETR_TIM3RST BIT(1) 828#define RCC_APB1RSTSETR_TIM4RST BIT(2) 829#define RCC_APB1RSTSETR_TIM5RST BIT(3) 830#define RCC_APB1RSTSETR_TIM6RST BIT(4) 831#define RCC_APB1RSTSETR_TIM7RST BIT(5) 832#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) 833#define RCC_APB1RSTSETR_SPI2RST BIT(11) 834#define RCC_APB1RSTSETR_SPI3RST BIT(12) 835#define RCC_APB1RSTSETR_USART3RST BIT(15) 836#define RCC_APB1RSTSETR_UART4RST BIT(16) 837#define RCC_APB1RSTSETR_UART5RST BIT(17) 838#define RCC_APB1RSTSETR_UART7RST BIT(18) 839#define RCC_APB1RSTSETR_UART8RST BIT(19) 840#define RCC_APB1RSTSETR_I2C1RST BIT(21) 841#define RCC_APB1RSTSETR_I2C2RST BIT(22) 842#define RCC_APB1RSTSETR_SPDIFRST BIT(26) 843 844/* RCC_APB1RSTCLRR register fields */ 845#define RCC_APB1RSTCLRR_TIM2RST BIT(0) 846#define RCC_APB1RSTCLRR_TIM3RST BIT(1) 847#define RCC_APB1RSTCLRR_TIM4RST BIT(2) 848#define RCC_APB1RSTCLRR_TIM5RST BIT(3) 849#define RCC_APB1RSTCLRR_TIM6RST BIT(4) 850#define RCC_APB1RSTCLRR_TIM7RST BIT(5) 851#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) 852#define RCC_APB1RSTCLRR_SPI2RST BIT(11) 853#define RCC_APB1RSTCLRR_SPI3RST BIT(12) 854#define RCC_APB1RSTCLRR_USART3RST BIT(15) 855#define RCC_APB1RSTCLRR_UART4RST BIT(16) 856#define RCC_APB1RSTCLRR_UART5RST BIT(17) 857#define RCC_APB1RSTCLRR_UART7RST BIT(18) 858#define RCC_APB1RSTCLRR_UART8RST BIT(19) 859#define RCC_APB1RSTCLRR_I2C1RST BIT(21) 860#define RCC_APB1RSTCLRR_I2C2RST BIT(22) 861#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) 862 863/* RCC_APB2RSTSETR register fields */ 864#define RCC_APB2RSTSETR_TIM1RST BIT(0) 865#define RCC_APB2RSTSETR_TIM8RST BIT(1) 866#define RCC_APB2RSTSETR_SPI1RST BIT(8) 867#define RCC_APB2RSTSETR_USART6RST BIT(13) 868#define RCC_APB2RSTSETR_SAI1RST BIT(16) 869#define RCC_APB2RSTSETR_SAI2RST BIT(17) 870#define RCC_APB2RSTSETR_DFSDMRST BIT(20) 871#define RCC_APB2RSTSETR_FDCANRST BIT(24) 872 873/* RCC_APB2RSTCLRR register fields */ 874#define RCC_APB2RSTCLRR_TIM1RST BIT(0) 875#define RCC_APB2RSTCLRR_TIM8RST BIT(1) 876#define RCC_APB2RSTCLRR_SPI1RST BIT(8) 877#define RCC_APB2RSTCLRR_USART6RST BIT(13) 878#define RCC_APB2RSTCLRR_SAI1RST BIT(16) 879#define RCC_APB2RSTCLRR_SAI2RST BIT(17) 880#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) 881#define RCC_APB2RSTCLRR_FDCANRST BIT(24) 882 883/* RCC_APB3RSTSETR register fields */ 884#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) 885#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) 886#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) 887#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) 888#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) 889#define RCC_APB3RSTSETR_VREFRST BIT(13) 890#define RCC_APB3RSTSETR_DTSRST BIT(16) 891#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) 892 893/* RCC_APB3RSTCLRR register fields */ 894#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) 895#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) 896#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) 897#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) 898#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) 899#define RCC_APB3RSTCLRR_VREFRST BIT(13) 900#define RCC_APB3RSTCLRR_DTSRST BIT(16) 901#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) 902 903/* RCC_APB4RSTSETR register fields */ 904#define RCC_APB4RSTSETR_LTDCRST BIT(0) 905#define RCC_APB4RSTSETR_DCMIPPRST BIT(1) 906#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) 907#define RCC_APB4RSTSETR_USBPHYRST BIT(16) 908 909/* RCC_APB4RSTCLRR register fields */ 910#define RCC_APB4RSTCLRR_LTDCRST BIT(0) 911#define RCC_APB4RSTCLRR_DCMIPPRST BIT(1) 912#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) 913#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) 914 915/* RCC_APB5RSTSETR register fields */ 916#define RCC_APB5RSTSETR_STGENRST BIT(20) 917 918/* RCC_APB5RSTCLRR register fields */ 919#define RCC_APB5RSTCLRR_STGENRST BIT(20) 920 921/* RCC_APB6RSTSETR register fields */ 922#define RCC_APB6RSTSETR_USART1RST BIT(0) 923#define RCC_APB6RSTSETR_USART2RST BIT(1) 924#define RCC_APB6RSTSETR_SPI4RST BIT(2) 925#define RCC_APB6RSTSETR_SPI5RST BIT(3) 926#define RCC_APB6RSTSETR_I2C3RST BIT(4) 927#define RCC_APB6RSTSETR_I2C4RST BIT(5) 928#define RCC_APB6RSTSETR_I2C5RST BIT(6) 929#define RCC_APB6RSTSETR_TIM12RST BIT(7) 930#define RCC_APB6RSTSETR_TIM13RST BIT(8) 931#define RCC_APB6RSTSETR_TIM14RST BIT(9) 932#define RCC_APB6RSTSETR_TIM15RST BIT(10) 933#define RCC_APB6RSTSETR_TIM16RST BIT(11) 934#define RCC_APB6RSTSETR_TIM17RST BIT(12) 935 936/* RCC_APB6RSTCLRR register fields */ 937#define RCC_APB6RSTCLRR_USART1RST BIT(0) 938#define RCC_APB6RSTCLRR_USART2RST BIT(1) 939#define RCC_APB6RSTCLRR_SPI4RST BIT(2) 940#define RCC_APB6RSTCLRR_SPI5RST BIT(3) 941#define RCC_APB6RSTCLRR_I2C3RST BIT(4) 942#define RCC_APB6RSTCLRR_I2C4RST BIT(5) 943#define RCC_APB6RSTCLRR_I2C5RST BIT(6) 944#define RCC_APB6RSTCLRR_TIM12RST BIT(7) 945#define RCC_APB6RSTCLRR_TIM13RST BIT(8) 946#define RCC_APB6RSTCLRR_TIM14RST BIT(9) 947#define RCC_APB6RSTCLRR_TIM15RST BIT(10) 948#define RCC_APB6RSTCLRR_TIM16RST BIT(11) 949#define RCC_APB6RSTCLRR_TIM17RST BIT(12) 950 951/* RCC_AHB2RSTSETR register fields */ 952#define RCC_AHB2RSTSETR_DMA1RST BIT(0) 953#define RCC_AHB2RSTSETR_DMA2RST BIT(1) 954#define RCC_AHB2RSTSETR_DMAMUX1RST BIT(2) 955#define RCC_AHB2RSTSETR_DMA3RST BIT(3) 956#define RCC_AHB2RSTSETR_DMAMUX2RST BIT(4) 957#define RCC_AHB2RSTSETR_ADC1RST BIT(5) 958#define RCC_AHB2RSTSETR_ADC2RST BIT(6) 959#define RCC_AHB2RSTSETR_USBORST BIT(8) 960 961/* RCC_AHB2RSTCLRR register fields */ 962#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) 963#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) 964#define RCC_AHB2RSTCLRR_DMAMUX1RST BIT(2) 965#define RCC_AHB2RSTCLRR_DMA3RST BIT(3) 966#define RCC_AHB2RSTCLRR_DMAMUX2RST BIT(4) 967#define RCC_AHB2RSTCLRR_ADC1RST BIT(5) 968#define RCC_AHB2RSTCLRR_ADC2RST BIT(6) 969#define RCC_AHB2RSTCLRR_USBORST BIT(8) 970 971/* RCC_AHB4RSTSETR register fields */ 972#define RCC_AHB4RSTSETR_GPIOARST BIT(0) 973#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) 974#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) 975#define RCC_AHB4RSTSETR_GPIODRST BIT(3) 976#define RCC_AHB4RSTSETR_GPIOERST BIT(4) 977#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) 978#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) 979#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) 980#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) 981#define RCC_AHB4RSTSETR_TSCRST BIT(15) 982 983/* RCC_AHB4RSTCLRR register fields */ 984#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) 985#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) 986#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) 987#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) 988#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) 989#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) 990#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) 991#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) 992#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) 993#define RCC_AHB4RSTCLRR_TSCRST BIT(15) 994 995/* RCC_AHB5RSTSETR register fields */ 996#define RCC_AHB5RSTSETR_PKARST BIT(2) 997#define RCC_AHB5RSTSETR_SAESRST BIT(3) 998#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) 999#define RCC_AHB5RSTSETR_HASH1RST BIT(5) 1000#define RCC_AHB5RSTSETR_RNG1RST BIT(6) 1001#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) 1002 1003/* RCC_AHB5RSTCLRR register fields */ 1004#define RCC_AHB5RSTCLRR_PKARST BIT(2) 1005#define RCC_AHB5RSTCLRR_SAESRST BIT(3) 1006#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) 1007#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) 1008#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) 1009#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) 1010 1011/* RCC_AHB6RSTSETR register fields */ 1012#define RCC_AHB6RSTSETR_MDMARST BIT(0) 1013#define RCC_AHB6RSTSETR_MCERST BIT(1) 1014#define RCC_AHB6RSTSETR_ETH1MACRST BIT(10) 1015#define RCC_AHB6RSTSETR_FMCRST BIT(12) 1016#define RCC_AHB6RSTSETR_QSPIRST BIT(14) 1017#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) 1018#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) 1019#define RCC_AHB6RSTSETR_CRC1RST BIT(20) 1020#define RCC_AHB6RSTSETR_USBHRST BIT(24) 1021#define RCC_AHB6RSTSETR_ETH2MACRST BIT(30) 1022 1023/* RCC_AHB6RSTCLRR register fields */ 1024#define RCC_AHB6RSTCLRR_MDMARST BIT(0) 1025#define RCC_AHB6RSTCLRR_MCERST BIT(1) 1026#define RCC_AHB6RSTCLRR_ETH1MACRST BIT(10) 1027#define RCC_AHB6RSTCLRR_FMCRST BIT(12) 1028#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) 1029#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) 1030#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) 1031#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) 1032#define RCC_AHB6RSTCLRR_USBHRST BIT(24) 1033#define RCC_AHB6RSTCLRR_ETH2MACRST BIT(30) 1034 1035/* RCC_MP_APB1ENSETR register fields */ 1036#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) 1037#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) 1038#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) 1039#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) 1040#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) 1041#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) 1042#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) 1043#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) 1044#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) 1045#define RCC_MP_APB1ENSETR_USART3EN BIT(15) 1046#define RCC_MP_APB1ENSETR_UART4EN BIT(16) 1047#define RCC_MP_APB1ENSETR_UART5EN BIT(17) 1048#define RCC_MP_APB1ENSETR_UART7EN BIT(18) 1049#define RCC_MP_APB1ENSETR_UART8EN BIT(19) 1050#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) 1051#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) 1052#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) 1053 1054/* RCC_MP_APB1ENCLRR register fields */ 1055#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) 1056#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) 1057#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) 1058#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) 1059#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) 1060#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) 1061#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) 1062#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) 1063#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) 1064#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) 1065#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) 1066#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) 1067#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) 1068#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) 1069#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) 1070#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) 1071#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) 1072 1073/* RCC_MP_APB2ENSETR register fields */ 1074#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) 1075#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) 1076#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) 1077#define RCC_MP_APB2ENSETR_USART6EN BIT(13) 1078#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) 1079#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) 1080#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) 1081#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) 1082#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) 1083 1084/* RCC_MP_APB2ENCLRR register fields */ 1085#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) 1086#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) 1087#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) 1088#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) 1089#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) 1090#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) 1091#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) 1092#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) 1093#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) 1094 1095/* RCC_MP_APB3ENSETR register fields */ 1096#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) 1097#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) 1098#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) 1099#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) 1100#define RCC_MP_APB3ENSETR_VREFEN BIT(13) 1101#define RCC_MP_APB3ENSETR_DTSEN BIT(16) 1102#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) 1103#define RCC_MP_APB3ENSETR_HDPEN BIT(20) 1104 1105/* RCC_MP_APB3ENCLRR register fields */ 1106#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) 1107#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) 1108#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) 1109#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) 1110#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) 1111#define RCC_MP_APB3ENCLRR_DTSEN BIT(16) 1112#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) 1113#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) 1114 1115/* RCC_MP_S_APB3ENSETR register fields */ 1116#define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0) 1117 1118/* RCC_MP_S_APB3ENCLRR register fields */ 1119#define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0) 1120 1121/* RCC_MP_NS_APB3ENSETR register fields */ 1122#define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0) 1123 1124/* RCC_MP_NS_APB3ENCLRR register fields */ 1125#define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0) 1126 1127/* RCC_MP_APB4ENSETR register fields */ 1128#define RCC_MP_APB4ENSETR_DCMIPPEN BIT(1) 1129#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) 1130#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) 1131#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) 1132#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) 1133 1134/* RCC_MP_APB4ENCLRR register fields */ 1135#define RCC_MP_APB4ENCLRR_DCMIPPEN BIT(1) 1136#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) 1137#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) 1138#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) 1139#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) 1140 1141/* RCC_MP_S_APB4ENSETR register fields */ 1142#define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0) 1143 1144/* RCC_MP_S_APB4ENCLRR register fields */ 1145#define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0) 1146 1147/* RCC_MP_NS_APB4ENSETR register fields */ 1148#define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0) 1149 1150/* RCC_MP_NS_APB4ENCLRR register fields */ 1151#define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0) 1152 1153/* RCC_MP_APB5ENSETR register fields */ 1154#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) 1155#define RCC_MP_APB5ENSETR_TZCEN BIT(11) 1156#define RCC_MP_APB5ENSETR_ETZPCEN BIT(13) 1157#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) 1158#define RCC_MP_APB5ENSETR_BSECEN BIT(16) 1159#define RCC_MP_APB5ENSETR_STGENCEN BIT(20) 1160 1161/* RCC_MP_APB5ENCLRR register fields */ 1162#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) 1163#define RCC_MP_APB5ENCLRR_TZCEN BIT(11) 1164#define RCC_MP_APB5ENCLRR_ETZPCEN BIT(13) 1165#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) 1166#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) 1167#define RCC_MP_APB5ENCLRR_STGENCEN BIT(20) 1168 1169/* RCC_MP_APB6ENSETR register fields */ 1170#define RCC_MP_APB6ENSETR_USART1EN BIT(0) 1171#define RCC_MP_APB6ENSETR_USART2EN BIT(1) 1172#define RCC_MP_APB6ENSETR_SPI4EN BIT(2) 1173#define RCC_MP_APB6ENSETR_SPI5EN BIT(3) 1174#define RCC_MP_APB6ENSETR_I2C3EN BIT(4) 1175#define RCC_MP_APB6ENSETR_I2C4EN BIT(5) 1176#define RCC_MP_APB6ENSETR_I2C5EN BIT(6) 1177#define RCC_MP_APB6ENSETR_TIM12EN BIT(7) 1178#define RCC_MP_APB6ENSETR_TIM13EN BIT(8) 1179#define RCC_MP_APB6ENSETR_TIM14EN BIT(9) 1180#define RCC_MP_APB6ENSETR_TIM15EN BIT(10) 1181#define RCC_MP_APB6ENSETR_TIM16EN BIT(11) 1182#define RCC_MP_APB6ENSETR_TIM17EN BIT(12) 1183 1184/* RCC_MP_APB6ENCLRR register fields */ 1185#define RCC_MP_APB6ENCLRR_USART1EN BIT(0) 1186#define RCC_MP_APB6ENCLRR_USART2EN BIT(1) 1187#define RCC_MP_APB6ENCLRR_SPI4EN BIT(2) 1188#define RCC_MP_APB6ENCLRR_SPI5EN BIT(3) 1189#define RCC_MP_APB6ENCLRR_I2C3EN BIT(4) 1190#define RCC_MP_APB6ENCLRR_I2C4EN BIT(5) 1191#define RCC_MP_APB6ENCLRR_I2C5EN BIT(6) 1192#define RCC_MP_APB6ENCLRR_TIM12EN BIT(7) 1193#define RCC_MP_APB6ENCLRR_TIM13EN BIT(8) 1194#define RCC_MP_APB6ENCLRR_TIM14EN BIT(9) 1195#define RCC_MP_APB6ENCLRR_TIM15EN BIT(10) 1196#define RCC_MP_APB6ENCLRR_TIM16EN BIT(11) 1197#define RCC_MP_APB6ENCLRR_TIM17EN BIT(12) 1198 1199/* RCC_MP_AHB2ENSETR register fields */ 1200#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) 1201#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) 1202#define RCC_MP_AHB2ENSETR_DMAMUX1EN BIT(2) 1203#define RCC_MP_AHB2ENSETR_DMA3EN BIT(3) 1204#define RCC_MP_AHB2ENSETR_DMAMUX2EN BIT(4) 1205#define RCC_MP_AHB2ENSETR_ADC1EN BIT(5) 1206#define RCC_MP_AHB2ENSETR_ADC2EN BIT(6) 1207#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) 1208 1209/* RCC_MP_AHB2ENCLRR register fields */ 1210#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) 1211#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) 1212#define RCC_MP_AHB2ENCLRR_DMAMUX1EN BIT(2) 1213#define RCC_MP_AHB2ENCLRR_DMA3EN BIT(3) 1214#define RCC_MP_AHB2ENCLRR_DMAMUX2EN BIT(4) 1215#define RCC_MP_AHB2ENCLRR_ADC1EN BIT(5) 1216#define RCC_MP_AHB2ENCLRR_ADC2EN BIT(6) 1217#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) 1218 1219/* RCC_MP_AHB4ENSETR register fields */ 1220#define RCC_MP_AHB4ENSETR_TSCEN BIT(15) 1221 1222/* RCC_MP_AHB4ENCLRR register fields */ 1223#define RCC_MP_AHB4ENCLRR_TSCEN BIT(15) 1224 1225/* RCC_MP_S_AHB4ENSETR register fields */ 1226#define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0) 1227#define RCC_MP_S_AHB4ENSETR_GPIOBEN BIT(1) 1228#define RCC_MP_S_AHB4ENSETR_GPIOCEN BIT(2) 1229#define RCC_MP_S_AHB4ENSETR_GPIODEN BIT(3) 1230#define RCC_MP_S_AHB4ENSETR_GPIOEEN BIT(4) 1231#define RCC_MP_S_AHB4ENSETR_GPIOFEN BIT(5) 1232#define RCC_MP_S_AHB4ENSETR_GPIOGEN BIT(6) 1233#define RCC_MP_S_AHB4ENSETR_GPIOHEN BIT(7) 1234#define RCC_MP_S_AHB4ENSETR_GPIOIEN BIT(8) 1235 1236/* RCC_MP_S_AHB4ENCLRR register fields */ 1237#define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0) 1238#define RCC_MP_S_AHB4ENCLRR_GPIOBEN BIT(1) 1239#define RCC_MP_S_AHB4ENCLRR_GPIOCEN BIT(2) 1240#define RCC_MP_S_AHB4ENCLRR_GPIODEN BIT(3) 1241#define RCC_MP_S_AHB4ENCLRR_GPIOEEN BIT(4) 1242#define RCC_MP_S_AHB4ENCLRR_GPIOFEN BIT(5) 1243#define RCC_MP_S_AHB4ENCLRR_GPIOGEN BIT(6) 1244#define RCC_MP_S_AHB4ENCLRR_GPIOHEN BIT(7) 1245#define RCC_MP_S_AHB4ENCLRR_GPIOIEN BIT(8) 1246 1247/* RCC_MP_NS_AHB4ENSETR register fields */ 1248#define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0) 1249#define RCC_MP_NS_AHB4ENSETR_GPIOBEN BIT(1) 1250#define RCC_MP_NS_AHB4ENSETR_GPIOCEN BIT(2) 1251#define RCC_MP_NS_AHB4ENSETR_GPIODEN BIT(3) 1252#define RCC_MP_NS_AHB4ENSETR_GPIOEEN BIT(4) 1253#define RCC_MP_NS_AHB4ENSETR_GPIOFEN BIT(5) 1254#define RCC_MP_NS_AHB4ENSETR_GPIOGEN BIT(6) 1255#define RCC_MP_NS_AHB4ENSETR_GPIOHEN BIT(7) 1256#define RCC_MP_NS_AHB4ENSETR_GPIOIEN BIT(8) 1257 1258/* RCC_MP_NS_AHB4ENCLRR register fields */ 1259#define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0) 1260#define RCC_MP_NS_AHB4ENCLRR_GPIOBEN BIT(1) 1261#define RCC_MP_NS_AHB4ENCLRR_GPIOCEN BIT(2) 1262#define RCC_MP_NS_AHB4ENCLRR_GPIODEN BIT(3) 1263#define RCC_MP_NS_AHB4ENCLRR_GPIOEEN BIT(4) 1264#define RCC_MP_NS_AHB4ENCLRR_GPIOFEN BIT(5) 1265#define RCC_MP_NS_AHB4ENCLRR_GPIOGEN BIT(6) 1266#define RCC_MP_NS_AHB4ENCLRR_GPIOHEN BIT(7) 1267#define RCC_MP_NS_AHB4ENCLRR_GPIOIEN BIT(8) 1268 1269/* RCC_MP_AHB5ENSETR register fields */ 1270#define RCC_MP_AHB5ENSETR_PKAEN BIT(2) 1271#define RCC_MP_AHB5ENSETR_SAESEN BIT(3) 1272#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) 1273#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) 1274#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) 1275#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) 1276#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) 1277 1278/* RCC_MP_AHB5ENCLRR register fields */ 1279#define RCC_MP_AHB5ENCLRR_PKAEN BIT(2) 1280#define RCC_MP_AHB5ENCLRR_SAESEN BIT(3) 1281#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) 1282#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) 1283#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) 1284#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) 1285#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) 1286 1287/* RCC_MP_AHB6ENSETR register fields */ 1288#define RCC_MP_AHB6ENSETR_MCEEN BIT(1) 1289#define RCC_MP_AHB6ENSETR_ETH1CKEN BIT(7) 1290#define RCC_MP_AHB6ENSETR_ETH1TXEN BIT(8) 1291#define RCC_MP_AHB6ENSETR_ETH1RXEN BIT(9) 1292#define RCC_MP_AHB6ENSETR_ETH1MACEN BIT(10) 1293#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) 1294#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) 1295#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) 1296#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) 1297#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) 1298#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) 1299#define RCC_MP_AHB6ENSETR_ETH2CKEN BIT(27) 1300#define RCC_MP_AHB6ENSETR_ETH2TXEN BIT(28) 1301#define RCC_MP_AHB6ENSETR_ETH2RXEN BIT(29) 1302#define RCC_MP_AHB6ENSETR_ETH2MACEN BIT(30) 1303 1304/* RCC_MP_AHB6ENCLRR register fields */ 1305#define RCC_MP_AHB6ENCLRR_MCEEN BIT(1) 1306#define RCC_MP_AHB6ENCLRR_ETH1CKEN BIT(7) 1307#define RCC_MP_AHB6ENCLRR_ETH1TXEN BIT(8) 1308#define RCC_MP_AHB6ENCLRR_ETH1RXEN BIT(9) 1309#define RCC_MP_AHB6ENCLRR_ETH1MACEN BIT(10) 1310#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) 1311#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) 1312#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) 1313#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) 1314#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) 1315#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) 1316#define RCC_MP_AHB6ENCLRR_ETH2CKEN BIT(27) 1317#define RCC_MP_AHB6ENCLRR_ETH2TXEN BIT(28) 1318#define RCC_MP_AHB6ENCLRR_ETH2RXEN BIT(29) 1319#define RCC_MP_AHB6ENCLRR_ETH2MACEN BIT(30) 1320 1321/* RCC_MP_S_AHB6ENSETR register fields */ 1322#define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0) 1323 1324/* RCC_MP_S_AHB6ENCLRR register fields */ 1325#define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0) 1326 1327/* RCC_MP_NS_AHB6ENSETR register fields */ 1328#define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0) 1329 1330/* RCC_MP_NS_AHB6ENCLRR register fields */ 1331#define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0) 1332 1333/* RCC_MP_APB1LPENSETR register fields */ 1334#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) 1335#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) 1336#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) 1337#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) 1338#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) 1339#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) 1340#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) 1341#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) 1342#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) 1343#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) 1344#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) 1345#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) 1346#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) 1347#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) 1348#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) 1349#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) 1350#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) 1351 1352/* RCC_MP_APB1LPENCLRR register fields */ 1353#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) 1354#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) 1355#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) 1356#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) 1357#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) 1358#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) 1359#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) 1360#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) 1361#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) 1362#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) 1363#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) 1364#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) 1365#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) 1366#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) 1367#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) 1368#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) 1369#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) 1370 1371/* RCC_MP_APB2LPENSETR register fields */ 1372#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) 1373#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) 1374#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) 1375#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) 1376#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) 1377#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) 1378#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) 1379#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) 1380#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) 1381 1382/* RCC_MP_APB2LPENCLRR register fields */ 1383#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) 1384#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) 1385#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) 1386#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) 1387#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) 1388#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) 1389#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) 1390#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) 1391#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) 1392 1393/* RCC_MP_APB3LPENSETR register fields */ 1394#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) 1395#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) 1396#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) 1397#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) 1398#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) 1399#define RCC_MP_APB3LPENSETR_DTSLPEN BIT(16) 1400#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) 1401 1402/* RCC_MP_APB3LPENCLRR register fields */ 1403#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) 1404#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) 1405#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) 1406#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) 1407#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) 1408#define RCC_MP_APB3LPENCLRR_DTSLPEN BIT(16) 1409#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) 1410 1411/* RCC_MP_S_APB3LPENSETR register fields */ 1412#define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0) 1413 1414/* RCC_MP_S_APB3LPENCLRR register fields */ 1415#define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0) 1416 1417/* RCC_MP_NS_APB3LPENSETR register fields */ 1418#define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0) 1419 1420/* RCC_MP_NS_APB3LPENCLRR register fields */ 1421#define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0) 1422 1423/* RCC_MP_APB4LPENSETR register fields */ 1424#define RCC_MP_APB4LPENSETR_DCMIPPLPEN BIT(1) 1425#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) 1426#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) 1427#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) 1428#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) 1429#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) 1430 1431/* RCC_MP_APB4LPENCLRR register fields */ 1432#define RCC_MP_APB4LPENCLRR_DCMIPPLPEN BIT(1) 1433#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) 1434#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) 1435#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) 1436#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) 1437#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) 1438 1439/* RCC_MP_S_APB4LPENSETR register fields */ 1440#define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0) 1441 1442/* RCC_MP_S_APB4LPENCLRR register fields */ 1443#define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0) 1444 1445/* RCC_MP_NS_APB4LPENSETR register fields */ 1446#define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0) 1447 1448/* RCC_MP_NS_APB4LPENCLRR register fields */ 1449#define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0) 1450 1451/* RCC_MP_APB5LPENSETR register fields */ 1452#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) 1453#define RCC_MP_APB5LPENSETR_TZCLPEN BIT(11) 1454#define RCC_MP_APB5LPENSETR_ETZPCLPEN BIT(13) 1455#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) 1456#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) 1457#define RCC_MP_APB5LPENSETR_STGENCLPEN BIT(20) 1458#define RCC_MP_APB5LPENSETR_STGENCSTPEN BIT(21) 1459 1460/* RCC_MP_APB5LPENCLRR register fields */ 1461#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) 1462#define RCC_MP_APB5LPENCLRR_TZCLPEN BIT(11) 1463#define RCC_MP_APB5LPENCLRR_ETZPCLPEN BIT(13) 1464#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) 1465#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) 1466#define RCC_MP_APB5LPENCLRR_STGENCLPEN BIT(20) 1467#define RCC_MP_APB5LPENCLRR_STGENCSTPEN BIT(21) 1468 1469/* RCC_MP_APB6LPENSETR register fields */ 1470#define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0) 1471#define RCC_MP_APB6LPENSETR_USART2LPEN BIT(1) 1472#define RCC_MP_APB6LPENSETR_SPI4LPEN BIT(2) 1473#define RCC_MP_APB6LPENSETR_SPI5LPEN BIT(3) 1474#define RCC_MP_APB6LPENSETR_I2C3LPEN BIT(4) 1475#define RCC_MP_APB6LPENSETR_I2C4LPEN BIT(5) 1476#define RCC_MP_APB6LPENSETR_I2C5LPEN BIT(6) 1477#define RCC_MP_APB6LPENSETR_TIM12LPEN BIT(7) 1478#define RCC_MP_APB6LPENSETR_TIM13LPEN BIT(8) 1479#define RCC_MP_APB6LPENSETR_TIM14LPEN BIT(9) 1480#define RCC_MP_APB6LPENSETR_TIM15LPEN BIT(10) 1481#define RCC_MP_APB6LPENSETR_TIM16LPEN BIT(11) 1482#define RCC_MP_APB6LPENSETR_TIM17LPEN BIT(12) 1483 1484/* RCC_MP_APB6LPENCLRR register fields */ 1485#define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0) 1486#define RCC_MP_APB6LPENCLRR_USART2LPEN BIT(1) 1487#define RCC_MP_APB6LPENCLRR_SPI4LPEN BIT(2) 1488#define RCC_MP_APB6LPENCLRR_SPI5LPEN BIT(3) 1489#define RCC_MP_APB6LPENCLRR_I2C3LPEN BIT(4) 1490#define RCC_MP_APB6LPENCLRR_I2C4LPEN BIT(5) 1491#define RCC_MP_APB6LPENCLRR_I2C5LPEN BIT(6) 1492#define RCC_MP_APB6LPENCLRR_TIM12LPEN BIT(7) 1493#define RCC_MP_APB6LPENCLRR_TIM13LPEN BIT(8) 1494#define RCC_MP_APB6LPENCLRR_TIM14LPEN BIT(9) 1495#define RCC_MP_APB6LPENCLRR_TIM15LPEN BIT(10) 1496#define RCC_MP_APB6LPENCLRR_TIM16LPEN BIT(11) 1497#define RCC_MP_APB6LPENCLRR_TIM17LPEN BIT(12) 1498 1499/* RCC_MP_AHB2LPENSETR register fields */ 1500#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) 1501#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) 1502#define RCC_MP_AHB2LPENSETR_DMAMUX1LPEN BIT(2) 1503#define RCC_MP_AHB2LPENSETR_DMA3LPEN BIT(3) 1504#define RCC_MP_AHB2LPENSETR_DMAMUX2LPEN BIT(4) 1505#define RCC_MP_AHB2LPENSETR_ADC1LPEN BIT(5) 1506#define RCC_MP_AHB2LPENSETR_ADC2LPEN BIT(6) 1507#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) 1508 1509/* RCC_MP_AHB2LPENCLRR register fields */ 1510#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) 1511#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) 1512#define RCC_MP_AHB2LPENCLRR_DMAMUX1LPEN BIT(2) 1513#define RCC_MP_AHB2LPENCLRR_DMA3LPEN BIT(3) 1514#define RCC_MP_AHB2LPENCLRR_DMAMUX2LPEN BIT(4) 1515#define RCC_MP_AHB2LPENCLRR_ADC1LPEN BIT(5) 1516#define RCC_MP_AHB2LPENCLRR_ADC2LPEN BIT(6) 1517#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) 1518 1519/* RCC_MP_AHB4LPENSETR register fields */ 1520#define RCC_MP_AHB4LPENSETR_TSCLPEN BIT(15) 1521 1522/* RCC_MP_AHB4LPENCLRR register fields */ 1523#define RCC_MP_AHB4LPENCLRR_TSCLPEN BIT(15) 1524 1525/* RCC_MP_S_AHB4LPENSETR register fields */ 1526#define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0) 1527#define RCC_MP_S_AHB4LPENSETR_GPIOBLPEN BIT(1) 1528#define RCC_MP_S_AHB4LPENSETR_GPIOCLPEN BIT(2) 1529#define RCC_MP_S_AHB4LPENSETR_GPIODLPEN BIT(3) 1530#define RCC_MP_S_AHB4LPENSETR_GPIOELPEN BIT(4) 1531#define RCC_MP_S_AHB4LPENSETR_GPIOFLPEN BIT(5) 1532#define RCC_MP_S_AHB4LPENSETR_GPIOGLPEN BIT(6) 1533#define RCC_MP_S_AHB4LPENSETR_GPIOHLPEN BIT(7) 1534#define RCC_MP_S_AHB4LPENSETR_GPIOILPEN BIT(8) 1535 1536/* RCC_MP_S_AHB4LPENCLRR register fields */ 1537#define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0) 1538#define RCC_MP_S_AHB4LPENCLRR_GPIOBLPEN BIT(1) 1539#define RCC_MP_S_AHB4LPENCLRR_GPIOCLPEN BIT(2) 1540#define RCC_MP_S_AHB4LPENCLRR_GPIODLPEN BIT(3) 1541#define RCC_MP_S_AHB4LPENCLRR_GPIOELPEN BIT(4) 1542#define RCC_MP_S_AHB4LPENCLRR_GPIOFLPEN BIT(5) 1543#define RCC_MP_S_AHB4LPENCLRR_GPIOGLPEN BIT(6) 1544#define RCC_MP_S_AHB4LPENCLRR_GPIOHLPEN BIT(7) 1545#define RCC_MP_S_AHB4LPENCLRR_GPIOILPEN BIT(8) 1546 1547/* RCC_MP_NS_AHB4LPENSETR register fields */ 1548#define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0) 1549#define RCC_MP_NS_AHB4LPENSETR_GPIOBLPEN BIT(1) 1550#define RCC_MP_NS_AHB4LPENSETR_GPIOCLPEN BIT(2) 1551#define RCC_MP_NS_AHB4LPENSETR_GPIODLPEN BIT(3) 1552#define RCC_MP_NS_AHB4LPENSETR_GPIOELPEN BIT(4) 1553#define RCC_MP_NS_AHB4LPENSETR_GPIOFLPEN BIT(5) 1554#define RCC_MP_NS_AHB4LPENSETR_GPIOGLPEN BIT(6) 1555#define RCC_MP_NS_AHB4LPENSETR_GPIOHLPEN BIT(7) 1556#define RCC_MP_NS_AHB4LPENSETR_GPIOILPEN BIT(8) 1557 1558/* RCC_MP_NS_AHB4LPENCLRR register fields */ 1559#define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0) 1560#define RCC_MP_NS_AHB4LPENCLRR_GPIOBLPEN BIT(1) 1561#define RCC_MP_NS_AHB4LPENCLRR_GPIOCLPEN BIT(2) 1562#define RCC_MP_NS_AHB4LPENCLRR_GPIODLPEN BIT(3) 1563#define RCC_MP_NS_AHB4LPENCLRR_GPIOELPEN BIT(4) 1564#define RCC_MP_NS_AHB4LPENCLRR_GPIOFLPEN BIT(5) 1565#define RCC_MP_NS_AHB4LPENCLRR_GPIOGLPEN BIT(6) 1566#define RCC_MP_NS_AHB4LPENCLRR_GPIOHLPEN BIT(7) 1567#define RCC_MP_NS_AHB4LPENCLRR_GPIOILPEN BIT(8) 1568 1569/* RCC_MP_AHB5LPENSETR register fields */ 1570#define RCC_MP_AHB5LPENSETR_PKALPEN BIT(2) 1571#define RCC_MP_AHB5LPENSETR_SAESLPEN BIT(3) 1572#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) 1573#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) 1574#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) 1575#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) 1576 1577/* RCC_MP_AHB5LPENCLRR register fields */ 1578#define RCC_MP_AHB5LPENCLRR_PKALPEN BIT(2) 1579#define RCC_MP_AHB5LPENCLRR_SAESLPEN BIT(3) 1580#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) 1581#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) 1582#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) 1583#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) 1584 1585/* RCC_MP_AHB6LPENSETR register fields */ 1586#define RCC_MP_AHB6LPENSETR_MCELPEN BIT(1) 1587#define RCC_MP_AHB6LPENSETR_ETH1CKLPEN BIT(7) 1588#define RCC_MP_AHB6LPENSETR_ETH1TXLPEN BIT(8) 1589#define RCC_MP_AHB6LPENSETR_ETH1RXLPEN BIT(9) 1590#define RCC_MP_AHB6LPENSETR_ETH1MACLPEN BIT(10) 1591#define RCC_MP_AHB6LPENSETR_ETH1STPEN BIT(11) 1592#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) 1593#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) 1594#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) 1595#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) 1596#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) 1597#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) 1598#define RCC_MP_AHB6LPENSETR_ETH2CKLPEN BIT(27) 1599#define RCC_MP_AHB6LPENSETR_ETH2TXLPEN BIT(28) 1600#define RCC_MP_AHB6LPENSETR_ETH2RXLPEN BIT(29) 1601#define RCC_MP_AHB6LPENSETR_ETH2MACLPEN BIT(30) 1602#define RCC_MP_AHB6LPENSETR_ETH2STPEN BIT(31) 1603 1604/* RCC_MP_AHB6LPENCLRR register fields */ 1605#define RCC_MP_AHB6LPENCLRR_MCELPEN BIT(1) 1606#define RCC_MP_AHB6LPENCLRR_ETH1CKLPEN BIT(7) 1607#define RCC_MP_AHB6LPENCLRR_ETH1TXLPEN BIT(8) 1608#define RCC_MP_AHB6LPENCLRR_ETH1RXLPEN BIT(9) 1609#define RCC_MP_AHB6LPENCLRR_ETH1MACLPEN BIT(10) 1610#define RCC_MP_AHB6LPENCLRR_ETH1STPEN BIT(11) 1611#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) 1612#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) 1613#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) 1614#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) 1615#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) 1616#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) 1617#define RCC_MP_AHB6LPENCLRR_ETH2CKLPEN BIT(27) 1618#define RCC_MP_AHB6LPENCLRR_ETH2TXLPEN BIT(28) 1619#define RCC_MP_AHB6LPENCLRR_ETH2RXLPEN BIT(29) 1620#define RCC_MP_AHB6LPENCLRR_ETH2MACLPEN BIT(30) 1621#define RCC_MP_AHB6LPENCLRR_ETH2STPEN BIT(31) 1622 1623/* RCC_MP_S_AHB6LPENSETR register fields */ 1624#define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0) 1625 1626/* RCC_MP_S_AHB6LPENCLRR register fields */ 1627#define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0) 1628 1629/* RCC_MP_NS_AHB6LPENSETR register fields */ 1630#define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0) 1631 1632/* RCC_MP_NS_AHB6LPENCLRR register fields */ 1633#define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0) 1634 1635/* RCC_MP_S_AXIMLPENSETR register fields */ 1636#define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0) 1637 1638/* RCC_MP_S_AXIMLPENCLRR register fields */ 1639#define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0) 1640 1641/* RCC_MP_NS_AXIMLPENSETR register fields */ 1642#define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0) 1643 1644/* RCC_MP_NS_AXIMLPENCLRR register fields */ 1645#define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0) 1646 1647/* RCC_MP_MLAHBLPENSETR register fields */ 1648#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) 1649#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) 1650#define RCC_MP_MLAHBLPENSETR_SRAM3LPEN BIT(2) 1651 1652/* RCC_MP_MLAHBLPENCLRR register fields */ 1653#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) 1654#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) 1655#define RCC_MP_MLAHBLPENCLRR_SRAM3LPEN BIT(2) 1656 1657/* RCC_APB3SECSR register fields */ 1658#define RCC_APB3SECSR_LPTIM2SECF 0 1659#define RCC_APB3SECSR_LPTIM3SECF 1 1660#define RCC_APB3SECSR_VREFSECF 13 1661 1662/* RCC_APB4SECSR register fields */ 1663#define RCC_APB4SECSR_DCMIPPSECF 1 1664#define RCC_APB4SECSR_USBPHYSECF 16 1665 1666/* RCC_APB5SECSR register fields */ 1667#define RCC_APB5SECSR_RTCSECF 8 1668#define RCC_APB5SECSR_TZCSECF 11 1669#define RCC_APB5SECSR_ETZPCSECF 13 1670#define RCC_APB5SECSR_IWDG1SECF 15 1671#define RCC_APB5SECSR_BSECSECF 16 1672#define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20) 1673#define RCC_APB5SECSR_STGENCSECF 20 1674#define RCC_APB5SECSR_STGENROSECF 21 1675 1676/* RCC_APB6SECSR register fields */ 1677#define RCC_APB6SECSR_USART1SECF 0 1678#define RCC_APB6SECSR_USART2SECF 1 1679#define RCC_APB6SECSR_SPI4SECF 2 1680#define RCC_APB6SECSR_SPI5SECF 3 1681#define RCC_APB6SECSR_I2C3SECF 4 1682#define RCC_APB6SECSR_I2C4SECF 5 1683#define RCC_APB6SECSR_I2C5SECF 6 1684#define RCC_APB6SECSR_TIM12SECF 7 1685#define RCC_APB6SECSR_TIM13SECF 8 1686#define RCC_APB6SECSR_TIM14SECF 9 1687#define RCC_APB6SECSR_TIM15SECF 10 1688#define RCC_APB6SECSR_TIM16SECF 11 1689#define RCC_APB6SECSR_TIM17SECF 12 1690 1691/* RCC_AHB2SECSR register fields */ 1692#define RCC_AHB2SECSR_DMA3SECF 3 1693#define RCC_AHB2SECSR_DMAMUX2SECF 4 1694#define RCC_AHB2SECSR_ADC1SECF 5 1695#define RCC_AHB2SECSR_ADC2SECF 6 1696#define RCC_AHB2SECSR_USBOSECF 8 1697 1698/* RCC_AHB4SECSR register fields */ 1699#define RCC_AHB4SECSR_TSCSECF 15 1700 1701/* RCC_AHB5SECSR register fields */ 1702#define RCC_AHB5SECSR_PKASECF 2 1703#define RCC_AHB5SECSR_SAESSECF 3 1704#define RCC_AHB5SECSR_CRYP1SECF 4 1705#define RCC_AHB5SECSR_HASH1SECF 5 1706#define RCC_AHB5SECSR_RNG1SECF 6 1707#define RCC_AHB5SECSR_BKPSRAMSECF 8 1708 1709/* RCC_AHB6SECSR register fields */ 1710#define RCC_AHB6SECSR_MCESECF 1 1711#define RCC_AHB6SECSR_FMCSECF 12 1712#define RCC_AHB6SECSR_QSPISECF 14 1713#define RCC_AHB6SECSR_SDMMC1SECF 16 1714#define RCC_AHB6SECSR_SDMMC2SECF 17 1715 1716#define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7) 1717#define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27) 1718#define RCC_AHB6SECSR_ETH1SECF_SHIFT 7 1719#define RCC_AHB6SECSR_ETH2SECF_SHIFT 27 1720 1721#define RCC_AHB6SECSR_ETH1CKSECF 7 1722#define RCC_AHB6SECSR_ETH1TXSECF 8 1723#define RCC_AHB6SECSR_ETH1RXSECF 9 1724#define RCC_AHB6SECSR_ETH1MACSECF 10 1725#define RCC_AHB6SECSR_ETH1STPSECF 11 1726 1727#define RCC_AHB6SECSR_ETH2CKSECF 27 1728#define RCC_AHB6SECSR_ETH2TXSECF 28 1729#define RCC_AHB6SECSR_ETH2RXSECF 29 1730#define RCC_AHB6SECSR_ETH2MACSECF 30 1731#define RCC_AHB6SECSR_ETH2STPSECF 31 1732 1733/* RCC_VERR register fields */ 1734#define RCC_VERR_MINREV_MASK GENMASK(3, 0) 1735#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) 1736#define RCC_VERR_MINREV_SHIFT 0 1737#define RCC_VERR_MAJREV_SHIFT 4 1738 1739/* RCC_IDR register fields */ 1740#define RCC_IDR_ID_MASK GENMASK(31, 0) 1741#define RCC_IDR_ID_SHIFT 0 1742 1743/* RCC_SIDR register fields */ 1744#define RCC_SIDR_SID_MASK GENMASK(31, 0) 1745#define RCC_SIDR_SID_SHIFT 0 1746 1747#endif /* STM32MP13_RCC_H */ 1748 1749