1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/module.h> 9#include <linux/of.h> 10#include <linux/of_address.h> 11#include <linux/platform_device.h> 12#include <linux/syscore_ops.h> 13#include <dt-bindings/clock/rk3568-cru.h> 14#include "clk.h" 15 16#define RK3568_GRF_SOC_STATUS0 0x580 17 18enum rk3568_pmu_plls { 19 ppll, hpll, 20}; 21 22enum rk3568_plls { 23 apll, dpll, gpll, cpll, npll, vpll, 24}; 25 26static struct rockchip_pll_rate_table rk3568_pll_rates[] = { 27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 28 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 29 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 30 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 31 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 32 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 33 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 34 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), 43 RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), 44 RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), 45 RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), 46 RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), 47 RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), 48 RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), 49 RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), 50 RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), 51 RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), 52 RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), 53 RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), 54 RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), 55 RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), 56 RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), 57 RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), 58 RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), 59 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), 60 RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), 61 RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), 62 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 63 RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), 64 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 66 RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), 67 RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), 68 RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), 69 RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), 70 RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), 71 RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), 72 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 73 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), 74 RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), 75 RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0), 76 RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), 77 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 78 RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), 79 RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), 80 RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), 81 RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), 82 RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), 83 RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), 84 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), 85 RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), 86 RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), 87 RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), 88 { /* sentinel */ }, 89}; 90 91#define RK3568_DIV_ATCLK_CORE_MASK 0x1f 92#define RK3568_DIV_ATCLK_CORE_SHIFT 0 93#define RK3568_DIV_GICCLK_CORE_MASK 0x1f 94#define RK3568_DIV_GICCLK_CORE_SHIFT 8 95#define RK3568_DIV_PCLK_CORE_MASK 0x1f 96#define RK3568_DIV_PCLK_CORE_SHIFT 0 97#define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f 98#define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 99#define RK3568_DIV_ACLK_CORE_MASK 0x1f 100#define RK3568_DIV_ACLK_CORE_SHIFT 8 101 102#define RK3568_DIV_SCLK_CORE_MASK 0xf 103#define RK3568_DIV_SCLK_CORE_SHIFT 0 104#define RK3568_MUX_SCLK_CORE_MASK 0x3 105#define RK3568_MUX_SCLK_CORE_SHIFT 8 106#define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1 107#define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 108#define RK3568_MUX_CLK_CORE_APLL_MASK 0x1 109#define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 110#define RK3568_MUX_CLK_PVTPLL_MASK 0x1 111#define RK3568_MUX_CLK_PVTPLL_SHIFT 15 112 113#define RK3568_CLKSEL1(_sclk_core) \ 114{ \ 115 .reg = RK3568_CLKSEL_CON(2), \ 116 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \ 117 RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \ 118 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \ 119 RK3568_MUX_SCLK_CORE_SHIFT) | \ 120 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \ 121 RK3568_DIV_SCLK_CORE_SHIFT), \ 122} 123 124#define RK3568_CLKSEL2(_aclk_core) \ 125{ \ 126 .reg = RK3568_CLKSEL_CON(5), \ 127 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \ 128 RK3568_DIV_ACLK_CORE_SHIFT), \ 129} 130 131#define RK3568_CLKSEL3(_atclk_core, _gic_core) \ 132{ \ 133 .reg = RK3568_CLKSEL_CON(3), \ 134 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \ 135 RK3568_DIV_ATCLK_CORE_SHIFT) | \ 136 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \ 137 RK3568_DIV_GICCLK_CORE_SHIFT), \ 138} 139 140#define RK3568_CLKSEL4(_pclk_core, _periph_core) \ 141{ \ 142 .reg = RK3568_CLKSEL_CON(4), \ 143 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \ 144 RK3568_DIV_PCLK_CORE_SHIFT) | \ 145 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \ 146 RK3568_DIV_PERIPHCLK_CORE_SHIFT), \ 147} 148 149#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \ 150{ \ 151 .prate = _prate##U, \ 152 .divs = { \ 153 RK3568_CLKSEL1(_sclk), \ 154 RK3568_CLKSEL2(_acore), \ 155 RK3568_CLKSEL3(_atcore, _gicclk), \ 156 RK3568_CLKSEL4(_pclk, _periph), \ 157 }, \ 158} 159 160static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { 161 RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), 162 RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), 163 RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), 164 RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), 165 RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), 166 RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), 167 RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), 168 RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), 169 RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), 170 RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), 171 RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), 172 RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), 173 RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), 174 RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5), 175 RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5), 176 RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5), 177 RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), 178 RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), 179 RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), 180 RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), 181 RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), 182 RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), 183 RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), 184 RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), 185 RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), 186 RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), 187 RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), 188 RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), 189 RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), 190 RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), 191}; 192 193static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { 194 .core_reg[0] = RK3568_CLKSEL_CON(0), 195 .div_core_shift[0] = 0, 196 .div_core_mask[0] = 0x1f, 197 .core_reg[1] = RK3568_CLKSEL_CON(0), 198 .div_core_shift[1] = 8, 199 .div_core_mask[1] = 0x1f, 200 .core_reg[2] = RK3568_CLKSEL_CON(1), 201 .div_core_shift[2] = 0, 202 .div_core_mask[2] = 0x1f, 203 .core_reg[3] = RK3568_CLKSEL_CON(1), 204 .div_core_shift[3] = 8, 205 .div_core_mask[3] = 0x1f, 206 .num_cores = 4, 207 .mux_core_alt = 1, 208 .mux_core_main = 0, 209 .mux_core_shift = 6, 210 .mux_core_mask = 0x1, 211}; 212 213PNAME(mux_pll_p) = { "xin24m" }; 214PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; 215PNAME(mux_armclk_p) = { "apll", "gpll" }; 216PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; 217PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; 218PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; 219PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" }; 220PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "}; 221PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" }; 222PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" }; 223PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; 224PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; 225PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 226PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 227PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 228PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 229PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 230PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 231PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 232PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 233PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 234PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; 235PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; 236PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; 237PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; 238PNAME(npll_gpll_p) = { "npll", "gpll" }; 239PNAME(cpll_gpll_p) = { "cpll", "gpll" }; 240PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 241PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; 242PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; 243PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; 244PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" }; 245PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; 246PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; 247PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; 248PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; 249PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; 250PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" }; 251PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; 252PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; 253PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; 254PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; 255PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; 256PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; 257PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; 258PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; 259PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; 260PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; 261PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; 262PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; 263PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; 264PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" }; 265PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; 266PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" }; 267PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 268PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; 269PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" }; 270PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" }; 271PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" }; 272PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; 273PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; 274PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; 275PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; 276PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" }; 277PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; 278PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; 279PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; 280PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" }; 281PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; 282PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; 283PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; 284PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; 285PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; 286PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" }; 287PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 288PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; 289PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; 290PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; 291PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; 292PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; 293PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; 294PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; 295PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; 296PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; 297PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; 298PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; 299PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; 300PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; 301PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" }; 302PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; 303PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; 304PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; 305PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" }; 306PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; 307PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; 308PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; 309PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; 310PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; 311PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" }; 312 313static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = { 314 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, 315 0, RK3568_PMU_PLL_CON(0), 316 RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates), 317 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 318 0, RK3568_PMU_PLL_CON(16), 319 RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates), 320}; 321 322static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = { 323 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 324 0, RK3568_PLL_CON(0), 325 RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates), 326 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 327 0, RK3568_PLL_CON(8), 328 RK3568_MODE_CON0, 2, 1, 0, NULL), 329 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 330 0, RK3568_PLL_CON(24), 331 RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates), 332 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 333 0, RK3568_PLL_CON(16), 334 RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates), 335 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 336 0, RK3568_PLL_CON(32), 337 RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates), 338 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 339 0, RK3568_PLL_CON(40), 340 RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates), 341}; 342 343#define MFLAGS CLK_MUX_HIWORD_MASK 344#define DFLAGS CLK_DIVIDER_HIWORD_MASK 345#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 346 347static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata = 348 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 349 RK3568_CLKSEL_CON(11), 10, 2, MFLAGS); 350 351static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata = 352 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 353 RK3568_CLKSEL_CON(13), 10, 2, MFLAGS); 354 355static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata = 356 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 357 RK3568_CLKSEL_CON(15), 10, 2, MFLAGS); 358 359static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata = 360 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 361 RK3568_CLKSEL_CON(17), 10, 2, MFLAGS); 362 363static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata = 364 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, 365 RK3568_CLKSEL_CON(19), 10, 2, MFLAGS); 366 367static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata = 368 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, 369 RK3568_CLKSEL_CON(21), 10, 2, MFLAGS); 370 371static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata = 372 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, 373 RK3568_CLKSEL_CON(83), 10, 2, MFLAGS); 374 375static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata = 376 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, 377 RK3568_CLKSEL_CON(23), 15, 1, MFLAGS); 378 379static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata = 380 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, 381 RK3568_CLKSEL_CON(25), 15, 1, MFLAGS); 382 383static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata = 384 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, 385 RK3568_CLKSEL_CON(52), 12, 2, MFLAGS); 386 387static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata = 388 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT, 389 RK3568_CLKSEL_CON(54), 12, 2, MFLAGS); 390 391static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata = 392 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT, 393 RK3568_CLKSEL_CON(56), 12, 2, MFLAGS); 394 395static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata = 396 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT, 397 RK3568_CLKSEL_CON(58), 12, 2, MFLAGS); 398 399static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata = 400 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT, 401 RK3568_CLKSEL_CON(60), 12, 2, MFLAGS); 402 403static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata = 404 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT, 405 RK3568_CLKSEL_CON(62), 12, 2, MFLAGS); 406 407static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata = 408 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT, 409 RK3568_CLKSEL_CON(64), 12, 2, MFLAGS); 410 411static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata = 412 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT, 413 RK3568_CLKSEL_CON(66), 12, 2, MFLAGS); 414 415static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata = 416 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT, 417 RK3568_CLKSEL_CON(68), 12, 2, MFLAGS); 418 419static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata = 420 MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT, 421 RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS); 422 423static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata = 424 MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 425 RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS); 426 427static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 428 /* 429 * Clock-Architecture Diagram 1 430 */ 431 /* SRC_CLK */ 432 COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED, 433 RK3568_CLKSEL_CON(75), 0, 5, DFLAGS, 434 RK3568_CLKGATE_CON(35), 0, GFLAGS), 435 COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED, 436 RK3568_CLKSEL_CON(75), 8, 5, DFLAGS, 437 RK3568_CLKGATE_CON(35), 1, GFLAGS), 438 COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED, 439 RK3568_CLKSEL_CON(76), 0, 5, DFLAGS, 440 RK3568_CLKGATE_CON(35), 2, GFLAGS), 441 COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED, 442 RK3568_CLKSEL_CON(76), 8, 5, DFLAGS, 443 RK3568_CLKGATE_CON(35), 3, GFLAGS), 444 COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED, 445 RK3568_CLKSEL_CON(77), 0, 5, DFLAGS, 446 RK3568_CLKGATE_CON(35), 4, GFLAGS), 447 COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED, 448 RK3568_CLKSEL_CON(77), 8, 5, DFLAGS, 449 RK3568_CLKGATE_CON(35), 5, GFLAGS), 450 COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED, 451 RK3568_CLKSEL_CON(78), 0, 6, DFLAGS, 452 RK3568_CLKGATE_CON(35), 6, GFLAGS), 453 COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED, 454 RK3568_CLKSEL_CON(78), 8, 5, DFLAGS, 455 RK3568_CLKGATE_CON(35), 7, GFLAGS), 456 COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED, 457 RK3568_CLKSEL_CON(79), 0, 5, DFLAGS, 458 RK3568_CLKGATE_CON(35), 8, GFLAGS), 459 COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED, 460 RK3568_CLKSEL_CON(79), 8, 5, DFLAGS, 461 RK3568_CLKGATE_CON(35), 9, GFLAGS), 462 COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED, 463 RK3568_CLKSEL_CON(80), 0, 5, DFLAGS, 464 RK3568_CLKGATE_CON(35), 10, GFLAGS), 465 COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED, 466 RK3568_CLKSEL_CON(82), 0, 5, DFLAGS, 467 RK3568_CLKGATE_CON(35), 11, GFLAGS), 468 COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED, 469 RK3568_CLKSEL_CON(80), 8, 5, DFLAGS, 470 RK3568_CLKGATE_CON(35), 12, GFLAGS), 471 COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED, 472 RK3568_CLKSEL_CON(81), 0, 5, DFLAGS, 473 RK3568_CLKGATE_CON(35), 13, GFLAGS), 474 COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED, 475 RK3568_CLKSEL_CON(81), 8, 6, DFLAGS, 476 RK3568_CLKGATE_CON(35), 14, GFLAGS), 477 COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED, 478 RK3568_CLKSEL_CON(82), 8, 6, DFLAGS, 479 RK3568_CLKGATE_CON(35), 15, GFLAGS), 480 FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2), 481 FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), 482 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 483 RK3568_MODE_CON0, 14, 2, MFLAGS), 484 485 /* PD_CORE */ 486 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED, 487 RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 488 RK3568_CLKGATE_CON(0), 5, GFLAGS), 489 COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED, 490 RK3568_CLKSEL_CON(2), 15, 1, MFLAGS, 491 RK3568_CLKGATE_CON(0), 7, GFLAGS), 492 493 COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED, 494 RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 495 RK3568_CLKGATE_CON(0), 8, GFLAGS), 496 COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED, 497 RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 498 RK3568_CLKGATE_CON(0), 9, GFLAGS), 499 COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 500 RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 501 RK3568_CLKGATE_CON(0), 10, GFLAGS), 502 COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED, 503 RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 504 RK3568_CLKGATE_CON(0), 11, GFLAGS), 505 COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, 506 RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 507 RK3568_CLKGATE_CON(0), 14, GFLAGS), 508 COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED, 509 RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 510 RK3568_CLKGATE_CON(0), 15, GFLAGS), 511 COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED, 512 RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 513 RK3568_CLKGATE_CON(1), 0, GFLAGS), 514 515 COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 516 RK3568_CLKSEL_CON(5), 14, 2, MFLAGS, 517 RK3568_CLKGATE_CON(1), 2, GFLAGS), 518 519 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0, 520 RK3568_CLKGATE_CON(1), 10, GFLAGS), 521 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0, 522 RK3568_CLKGATE_CON(1), 11, GFLAGS), 523 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED, 524 RK3568_CLKGATE_CON(1), 12, GFLAGS), 525 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0, 526 RK3568_CLKGATE_CON(1), 9, GFLAGS), 527 528 /* PD_GPU */ 529 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0, 530 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 531 RK3568_CLKGATE_CON(2), 0, GFLAGS), 532 MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT, 533 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY), 534 DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0, 535 RK3568_CLKSEL_CON(6), 8, 2, DFLAGS), 536 DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0, 537 RK3568_CLKSEL_CON(6), 12, 4, DFLAGS), 538 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0, 539 RK3568_CLKGATE_CON(2), 3, GFLAGS), 540 541 GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0, 542 RK3568_CLKGATE_CON(2), 6, GFLAGS), 543 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, 544 RK3568_CLKGATE_CON(2), 7, GFLAGS), 545 GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0, 546 RK3568_CLKGATE_CON(2), 8, GFLAGS), 547 GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED, 548 RK3568_CLKGATE_CON(2), 9, GFLAGS), 549 550 /* PD_NPU */ 551 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0, 552 RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS, 553 RK3568_CLKGATE_CON(3), 0, GFLAGS), 554 MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 555 RK3568_CLKSEL_CON(7), 8, 1, MFLAGS), 556 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT, 557 RK3568_CLKSEL_CON(7), 15, 1, MFLAGS), 558 COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0, 559 RK3568_CLKSEL_CON(8), 0, 4, DFLAGS, 560 RK3568_CLKGATE_CON(3), 2, GFLAGS), 561 COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0, 562 RK3568_CLKSEL_CON(8), 4, 4, DFLAGS, 563 RK3568_CLKGATE_CON(3), 3, GFLAGS), 564 GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0, 565 RK3568_CLKGATE_CON(3), 4, GFLAGS), 566 GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0, 567 RK3568_CLKGATE_CON(3), 7, GFLAGS), 568 GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0, 569 RK3568_CLKGATE_CON(3), 8, GFLAGS), 570 571 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0, 572 RK3568_CLKGATE_CON(3), 9, GFLAGS), 573 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, 574 RK3568_CLKGATE_CON(3), 10, GFLAGS), 575 GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0, 576 RK3568_CLKGATE_CON(3), 11, GFLAGS), 577 GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED, 578 RK3568_CLKGATE_CON(3), 12, GFLAGS), 579 580 /* PD_DDR */ 581 COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED, 582 RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 583 RK3568_CLKGATE_CON(4), 0, GFLAGS), 584 MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT, 585 RK3568_CLKSEL_CON(9), 15, 1, MFLAGS), 586 587 COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED, 588 RK3568_CLKSEL_CON(10), 0, 2, DFLAGS, 589 RK3568_CLKGATE_CON(4), 2, GFLAGS), 590 GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED, 591 RK3568_CLKGATE_CON(4), 15, GFLAGS), 592 593 /* PD_GIC_AUDIO */ 594 COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED, 595 RK3568_CLKSEL_CON(10), 8, 2, MFLAGS, 596 RK3568_CLKGATE_CON(5), 0, GFLAGS), 597 COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 598 RK3568_CLKSEL_CON(10), 10, 2, MFLAGS, 599 RK3568_CLKGATE_CON(5), 1, GFLAGS), 600 GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0, 601 RK3568_CLKGATE_CON(5), 8, GFLAGS), 602 COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0, 603 RK3568_CLKSEL_CON(10), 12, 2, MFLAGS, 604 RK3568_CLKGATE_CON(5), 9, GFLAGS), 605 GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED, 606 RK3568_CLKGATE_CON(5), 4, GFLAGS), 607 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED, 608 RK3568_CLKGATE_CON(5), 7, GFLAGS), 609 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0, 610 RK3568_CLKGATE_CON(5), 10, GFLAGS), 611 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0, 612 RK3568_CLKGATE_CON(5), 11, GFLAGS), 613 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0, 614 RK3568_CLKGATE_CON(5), 12, GFLAGS), 615 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0, 616 RK3568_CLKGATE_CON(5), 13, GFLAGS), 617 618 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0, 619 RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS, 620 RK3568_CLKGATE_CON(6), 0, GFLAGS), 621 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT, 622 RK3568_CLKSEL_CON(12), 0, 623 RK3568_CLKGATE_CON(6), 1, GFLAGS, 624 &rk3568_i2s0_8ch_tx_fracmux), 625 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, 626 RK3568_CLKGATE_CON(6), 2, GFLAGS), 627 COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT, 628 RK3568_CLKSEL_CON(11), 15, 1, MFLAGS, 629 RK3568_CLKGATE_CON(6), 3, GFLAGS), 630 631 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0, 632 RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS, 633 RK3568_CLKGATE_CON(6), 4, GFLAGS), 634 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT, 635 RK3568_CLKSEL_CON(14), 0, 636 RK3568_CLKGATE_CON(6), 5, GFLAGS, 637 &rk3568_i2s0_8ch_rx_fracmux), 638 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, 639 RK3568_CLKGATE_CON(6), 6, GFLAGS), 640 COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT, 641 RK3568_CLKSEL_CON(13), 15, 1, MFLAGS, 642 RK3568_CLKGATE_CON(6), 7, GFLAGS), 643 644 COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0, 645 RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS, 646 RK3568_CLKGATE_CON(6), 8, GFLAGS), 647 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT, 648 RK3568_CLKSEL_CON(16), 0, 649 RK3568_CLKGATE_CON(6), 9, GFLAGS, 650 &rk3568_i2s1_8ch_tx_fracmux), 651 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, 652 RK3568_CLKGATE_CON(6), 10, GFLAGS), 653 COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT, 654 RK3568_CLKSEL_CON(15), 15, 1, MFLAGS, 655 RK3568_CLKGATE_CON(6), 11, GFLAGS), 656 657 COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0, 658 RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS, 659 RK3568_CLKGATE_CON(6), 12, GFLAGS), 660 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT, 661 RK3568_CLKSEL_CON(18), 0, 662 RK3568_CLKGATE_CON(6), 13, GFLAGS, 663 &rk3568_i2s1_8ch_rx_fracmux), 664 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, 665 RK3568_CLKGATE_CON(6), 14, GFLAGS), 666 COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT, 667 RK3568_CLKSEL_CON(17), 15, 1, MFLAGS, 668 RK3568_CLKGATE_CON(6), 15, GFLAGS), 669 670 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0, 671 RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS, 672 RK3568_CLKGATE_CON(7), 0, GFLAGS), 673 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, 674 RK3568_CLKSEL_CON(20), 0, 675 RK3568_CLKGATE_CON(7), 1, GFLAGS, 676 &rk3568_i2s2_2ch_fracmux), 677 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, 678 RK3568_CLKGATE_CON(7), 2, GFLAGS), 679 COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT, 680 RK3568_CLKSEL_CON(19), 15, 1, MFLAGS, 681 RK3568_CLKGATE_CON(7), 3, GFLAGS), 682 683 COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0, 684 RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS, 685 RK3568_CLKGATE_CON(7), 4, GFLAGS), 686 COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT, 687 RK3568_CLKSEL_CON(22), 0, 688 RK3568_CLKGATE_CON(7), 5, GFLAGS, 689 &rk3568_i2s3_2ch_tx_fracmux), 690 GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0, 691 RK3568_CLKGATE_CON(7), 6, GFLAGS), 692 COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT, 693 RK3568_CLKSEL_CON(21), 15, 1, MFLAGS, 694 RK3568_CLKGATE_CON(7), 7, GFLAGS), 695 696 COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0, 697 RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS, 698 RK3568_CLKGATE_CON(7), 8, GFLAGS), 699 COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT, 700 RK3568_CLKSEL_CON(84), 0, 701 RK3568_CLKGATE_CON(7), 9, GFLAGS, 702 &rk3568_i2s3_2ch_rx_fracmux), 703 GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0, 704 RK3568_CLKGATE_CON(7), 10, GFLAGS), 705 COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT, 706 RK3568_CLKSEL_CON(83), 15, 1, MFLAGS, 707 RK3568_CLKGATE_CON(7), 11, GFLAGS), 708 709 GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0, 710 RK3568_CLKGATE_CON(5), 14, GFLAGS), 711 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0, 712 RK3568_CLKSEL_CON(23), 8, 2, MFLAGS, 713 RK3568_CLKGATE_CON(5), 15, GFLAGS), 714 GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0, 715 RK3568_CLKGATE_CON(7), 12, GFLAGS), 716 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0, 717 RK3568_CLKGATE_CON(7), 13, GFLAGS), 718 719 COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0, 720 RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS, 721 RK3568_CLKGATE_CON(7), 14, GFLAGS), 722 COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT, 723 RK3568_CLKSEL_CON(24), 0, 724 RK3568_CLKGATE_CON(7), 15, GFLAGS, 725 &rk3568_spdif_8ch_fracmux), 726 727 GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0, 728 RK3568_CLKGATE_CON(8), 0, GFLAGS), 729 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0, 730 RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS, 731 RK3568_CLKGATE_CON(8), 1, GFLAGS), 732 COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT, 733 RK3568_CLKSEL_CON(26), 0, 734 RK3568_CLKGATE_CON(8), 2, GFLAGS, 735 &rk3568_audpwm_fracmux), 736 737 GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0, 738 RK3568_CLKGATE_CON(8), 3, GFLAGS), 739 COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0, 740 RK3568_CLKSEL_CON(23), 10, 2, MFLAGS, 741 RK3568_CLKGATE_CON(8), 4, GFLAGS), 742 GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0, 743 RK3568_CLKGATE_CON(8), 5, GFLAGS), 744 GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0, 745 RK3568_CLKGATE_CON(8), 6, GFLAGS), 746 747 /* PD_SECURE_FLASH */ 748 COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0, 749 RK3568_CLKSEL_CON(27), 0, 2, MFLAGS, 750 RK3568_CLKGATE_CON(8), 7, GFLAGS), 751 COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0, 752 RK3568_CLKSEL_CON(27), 2, 2, MFLAGS, 753 RK3568_CLKGATE_CON(8), 8, GFLAGS), 754 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0, 755 RK3568_CLKGATE_CON(8), 11, GFLAGS), 756 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0, 757 RK3568_CLKGATE_CON(8), 12, GFLAGS), 758 COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0, 759 RK3568_CLKSEL_CON(27), 4, 2, MFLAGS, 760 RK3568_CLKGATE_CON(8), 13, GFLAGS), 761 COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0, 762 RK3568_CLKSEL_CON(27), 6, 2, MFLAGS, 763 RK3568_CLKGATE_CON(8), 14, GFLAGS), 764 GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0, 765 RK3568_CLKGATE_CON(8), 15, GFLAGS), 766 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, 767 RK3568_CLKGATE_CON(9), 10, GFLAGS), 768 GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED, 769 RK3568_CLKGATE_CON(9), 11, GFLAGS), 770 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0, 771 RK3568_CLKGATE_CON(26), 9, GFLAGS), 772 GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0, 773 RK3568_CLKGATE_CON(26), 10, GFLAGS), 774 GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0, 775 RK3568_CLKGATE_CON(26), 11, GFLAGS), 776 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0, 777 RK3568_CLKGATE_CON(9), 0, GFLAGS), 778 COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0, 779 RK3568_CLKSEL_CON(28), 0, 2, MFLAGS, 780 RK3568_CLKGATE_CON(9), 1, GFLAGS), 781 GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0, 782 RK3568_CLKGATE_CON(9), 2, GFLAGS), 783 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0, 784 RK3568_CLKGATE_CON(9), 3, GFLAGS), 785 COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0, 786 RK3568_CLKSEL_CON(28), 4, 3, MFLAGS, 787 RK3568_CLKGATE_CON(9), 4, GFLAGS), 788 GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0, 789 RK3568_CLKGATE_CON(9), 5, GFLAGS), 790 GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0, 791 RK3568_CLKGATE_CON(9), 6, GFLAGS), 792 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0, 793 RK3568_CLKSEL_CON(28), 8, 2, MFLAGS, 794 RK3568_CLKGATE_CON(9), 7, GFLAGS), 795 COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0, 796 RK3568_CLKSEL_CON(28), 12, 3, MFLAGS, 797 RK3568_CLKGATE_CON(9), 8, GFLAGS), 798 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, 799 RK3568_CLKGATE_CON(9), 9, GFLAGS), 800 MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1), 801 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1), 802 803 /* PD_PIPE */ 804 COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0, 805 RK3568_CLKSEL_CON(29), 0, 2, MFLAGS, 806 RK3568_CLKGATE_CON(10), 0, GFLAGS), 807 COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0, 808 RK3568_CLKSEL_CON(29), 4, 4, DFLAGS, 809 RK3568_CLKGATE_CON(10), 1, GFLAGS), 810 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0, 811 RK3568_CLKGATE_CON(12), 0, GFLAGS), 812 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0, 813 RK3568_CLKGATE_CON(12), 1, GFLAGS), 814 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0, 815 RK3568_CLKGATE_CON(12), 2, GFLAGS), 816 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0, 817 RK3568_CLKGATE_CON(12), 3, GFLAGS), 818 GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0, 819 RK3568_CLKGATE_CON(12), 4, GFLAGS), 820 GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0, 821 RK3568_CLKGATE_CON(12), 8, GFLAGS), 822 GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0, 823 RK3568_CLKGATE_CON(12), 9, GFLAGS), 824 GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0, 825 RK3568_CLKGATE_CON(12), 10, GFLAGS), 826 GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0, 827 RK3568_CLKGATE_CON(12), 11, GFLAGS), 828 GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0, 829 RK3568_CLKGATE_CON(12), 12, GFLAGS), 830 GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0, 831 RK3568_CLKGATE_CON(13), 0, GFLAGS), 832 GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0, 833 RK3568_CLKGATE_CON(13), 1, GFLAGS), 834 GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0, 835 RK3568_CLKGATE_CON(13), 2, GFLAGS), 836 GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0, 837 RK3568_CLKGATE_CON(13), 3, GFLAGS), 838 GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0, 839 RK3568_CLKGATE_CON(13), 4, GFLAGS), 840 GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0, 841 RK3568_CLKGATE_CON(11), 0, GFLAGS), 842 GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0, 843 RK3568_CLKGATE_CON(11), 1, GFLAGS), 844 GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0, 845 RK3568_CLKGATE_CON(11), 2, GFLAGS), 846 GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0, 847 RK3568_CLKGATE_CON(11), 4, GFLAGS), 848 GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0, 849 RK3568_CLKGATE_CON(11), 5, GFLAGS), 850 GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0, 851 RK3568_CLKGATE_CON(11), 6, GFLAGS), 852 GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0, 853 RK3568_CLKGATE_CON(11), 8, GFLAGS), 854 GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0, 855 RK3568_CLKGATE_CON(11), 9, GFLAGS), 856 GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0, 857 RK3568_CLKGATE_CON(11), 10, GFLAGS), 858 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0, 859 RK3568_CLKGATE_CON(10), 8, GFLAGS), 860 GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, 861 RK3568_CLKGATE_CON(10), 9, GFLAGS), 862 COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0, 863 RK3568_CLKSEL_CON(29), 8, 1, MFLAGS, 864 RK3568_CLKGATE_CON(10), 10, GFLAGS), 865 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0, 866 RK3568_CLKGATE_CON(10), 12, GFLAGS), 867 GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, 868 RK3568_CLKGATE_CON(10), 13, GFLAGS), 869 COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0, 870 RK3568_CLKSEL_CON(29), 9, 1, MFLAGS, 871 RK3568_CLKGATE_CON(10), 14, GFLAGS), 872 COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0, 873 RK3568_CLKSEL_CON(29), 13, 1, MFLAGS, 874 RK3568_CLKGATE_CON(10), 4, GFLAGS), 875 GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0, 876 RK3568_CLKGATE_CON(13), 6, GFLAGS), 877 878 /* PD_PHP */ 879 COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0, 880 RK3568_CLKSEL_CON(30), 0, 2, MFLAGS, 881 RK3568_CLKGATE_CON(14), 8, GFLAGS), 882 COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0, 883 RK3568_CLKSEL_CON(30), 2, 2, MFLAGS, 884 RK3568_CLKGATE_CON(14), 9, GFLAGS), 885 COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, 886 RK3568_CLKSEL_CON(30), 4, 4, DFLAGS, 887 RK3568_CLKGATE_CON(14), 10, GFLAGS), 888 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0, 889 RK3568_CLKGATE_CON(15), 0, GFLAGS), 890 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0, 891 RK3568_CLKSEL_CON(30), 8, 3, MFLAGS, 892 RK3568_CLKGATE_CON(15), 1, GFLAGS), 893 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1), 894 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1), 895 896 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0, 897 RK3568_CLKGATE_CON(15), 2, GFLAGS), 898 COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0, 899 RK3568_CLKSEL_CON(30), 12, 3, MFLAGS, 900 RK3568_CLKGATE_CON(15), 3, GFLAGS), 901 MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1), 902 MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1), 903 904 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0, 905 RK3568_CLKGATE_CON(15), 5, GFLAGS), 906 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0, 907 RK3568_CLKGATE_CON(15), 6, GFLAGS), 908 COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0, 909 RK3568_CLKSEL_CON(31), 8, 2, MFLAGS, 910 RK3568_CLKGATE_CON(15), 7, GFLAGS), 911 COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0, 912 RK3568_CLKSEL_CON(31), 14, 2, MFLAGS, 913 RK3568_CLKGATE_CON(15), 8, GFLAGS), 914 GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0, 915 RK3568_CLKGATE_CON(15), 12, GFLAGS), 916 COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0, 917 RK3568_CLKSEL_CON(31), 12, 2, MFLAGS, 918 RK3568_CLKGATE_CON(15), 4, GFLAGS), 919 MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 920 RK3568_CLKSEL_CON(31), 2, 1, MFLAGS), 921 FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5), 922 FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50), 923 FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2), 924 FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20), 925 MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0, 926 RK3568_CLKSEL_CON(31), 4, 2, MFLAGS), 927 MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0, 928 RK3568_CLKSEL_CON(31), 3, 1, MFLAGS), 929 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT, 930 RK3568_CLKSEL_CON(31), 0, 2, MFLAGS), 931 932 /* PD_USB */ 933 COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0, 934 RK3568_CLKSEL_CON(32), 0, 2, MFLAGS, 935 RK3568_CLKGATE_CON(16), 0, GFLAGS), 936 COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0, 937 RK3568_CLKSEL_CON(32), 2, 2, MFLAGS, 938 RK3568_CLKGATE_CON(16), 1, GFLAGS), 939 COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0, 940 RK3568_CLKSEL_CON(32), 4, 4, DFLAGS, 941 RK3568_CLKGATE_CON(16), 2, GFLAGS), 942 GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0, 943 RK3568_CLKGATE_CON(16), 12, GFLAGS), 944 GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0, 945 RK3568_CLKGATE_CON(16), 13, GFLAGS), 946 GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0, 947 RK3568_CLKGATE_CON(16), 14, GFLAGS), 948 GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0, 949 RK3568_CLKGATE_CON(16), 15, GFLAGS), 950 GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0, 951 RK3568_CLKGATE_CON(17), 0, GFLAGS), 952 COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0, 953 RK3568_CLKSEL_CON(32), 8, 3, MFLAGS, 954 RK3568_CLKGATE_CON(17), 1, GFLAGS), 955 MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1), 956 MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1), 957 958 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0, 959 RK3568_CLKGATE_CON(17), 3, GFLAGS), 960 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0, 961 RK3568_CLKGATE_CON(17), 4, GFLAGS), 962 COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0, 963 RK3568_CLKSEL_CON(33), 8, 2, MFLAGS, 964 RK3568_CLKGATE_CON(17), 5, GFLAGS), 965 COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0, 966 RK3568_CLKSEL_CON(33), 14, 2, MFLAGS, 967 RK3568_CLKGATE_CON(17), 6, GFLAGS), 968 GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0, 969 RK3568_CLKGATE_CON(17), 10, GFLAGS), 970 COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0, 971 RK3568_CLKSEL_CON(33), 12, 2, MFLAGS, 972 RK3568_CLKGATE_CON(17), 2, GFLAGS), 973 MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 974 RK3568_CLKSEL_CON(33), 2, 1, MFLAGS), 975 FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5), 976 FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50), 977 FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2), 978 FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20), 979 MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0, 980 RK3568_CLKSEL_CON(33), 4, 2, MFLAGS), 981 MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0, 982 RK3568_CLKSEL_CON(33), 3, 1, MFLAGS), 983 MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT, 984 RK3568_CLKSEL_CON(33), 0, 2, MFLAGS), 985 986 /* PD_PERI */ 987 COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED, 988 RK3568_CLKSEL_CON(10), 4, 2, MFLAGS, 989 RK3568_CLKGATE_CON(14), 0, GFLAGS), 990 COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED, 991 RK3568_CLKSEL_CON(10), 6, 2, MFLAGS, 992 RK3568_CLKGATE_CON(14), 1, GFLAGS), 993 994 /* PD_VI */ 995 COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0, 996 RK3568_CLKSEL_CON(34), 0, 2, MFLAGS, 997 RK3568_CLKGATE_CON(18), 0, GFLAGS), 998 COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0, 999 RK3568_CLKSEL_CON(34), 4, 4, DFLAGS, 1000 RK3568_CLKGATE_CON(18), 1, GFLAGS), 1001 COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0, 1002 RK3568_CLKSEL_CON(34), 8, 4, DFLAGS, 1003 RK3568_CLKGATE_CON(18), 2, GFLAGS), 1004 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0, 1005 RK3568_CLKGATE_CON(18), 9, GFLAGS), 1006 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, 1007 RK3568_CLKGATE_CON(18), 10, GFLAGS), 1008 COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0, 1009 RK3568_CLKSEL_CON(34), 14, 2, MFLAGS, 1010 RK3568_CLKGATE_CON(18), 11, GFLAGS), 1011 GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0, 1012 RK3568_CLKGATE_CON(18), 13, GFLAGS), 1013 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0, 1014 RK3568_CLKGATE_CON(19), 0, GFLAGS), 1015 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, 1016 RK3568_CLKGATE_CON(19), 1, GFLAGS), 1017 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0, 1018 RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 1019 RK3568_CLKGATE_CON(19), 2, GFLAGS), 1020 GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0, 1021 RK3568_CLKGATE_CON(19), 4, GFLAGS), 1022 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0, 1023 RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS, 1024 RK3568_CLKGATE_CON(19), 8, GFLAGS), 1025 COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0, 1026 RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS, 1027 RK3568_CLKGATE_CON(19), 9, GFLAGS), 1028 COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0, 1029 RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS, 1030 RK3568_CLKGATE_CON(19), 10, GFLAGS), 1031 1032 /* PD_VO */ 1033 COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0, 1034 RK3568_CLKSEL_CON(37), 0, 2, MFLAGS, 1035 RK3568_CLKGATE_CON(20), 0, GFLAGS), 1036 COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0, 1037 RK3568_CLKSEL_CON(37), 8, 4, DFLAGS, 1038 RK3568_CLKGATE_CON(20), 1, GFLAGS), 1039 COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0, 1040 RK3568_CLKSEL_CON(37), 12, 4, DFLAGS, 1041 RK3568_CLKGATE_CON(20), 2, GFLAGS), 1042 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0, 1043 RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS, 1044 RK3568_CLKGATE_CON(20), 6, GFLAGS), 1045 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, 1046 RK3568_CLKGATE_CON(20), 8, GFLAGS), 1047 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, 1048 RK3568_CLKGATE_CON(20), 9, GFLAGS), 1049 COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1050 RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, 1051 RK3568_CLKGATE_CON(20), 10, GFLAGS), 1052 COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1053 RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, 1054 RK3568_CLKGATE_CON(20), 11, GFLAGS), 1055 COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, 1056 RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, 1057 RK3568_CLKGATE_CON(20), 12, GFLAGS), 1058 GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, 1059 RK3568_CLKGATE_CON(20), 13, GFLAGS), 1060 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0, 1061 RK3568_CLKGATE_CON(21), 0, GFLAGS), 1062 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0, 1063 RK3568_CLKGATE_CON(21), 1, GFLAGS), 1064 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0, 1065 RK3568_CLKGATE_CON(21), 2, GFLAGS), 1066 GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0, 1067 RK3568_CLKGATE_CON(21), 3, GFLAGS), 1068 GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, 1069 RK3568_CLKGATE_CON(21), 4, GFLAGS), 1070 GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0, 1071 RK3568_CLKGATE_CON(21), 5, GFLAGS), 1072 GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0, 1073 RK3568_CLKGATE_CON(21), 6, GFLAGS), 1074 GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0, 1075 RK3568_CLKGATE_CON(21), 7, GFLAGS), 1076 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0, 1077 RK3568_CLKGATE_CON(21), 8, GFLAGS), 1078 COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0, 1079 RK3568_CLKSEL_CON(38), 8, 2, MFLAGS, 1080 RK3568_CLKGATE_CON(21), 9, GFLAGS), 1081 1082 /* PD_VPU */ 1083 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0, 1084 RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS, 1085 RK3568_CLKGATE_CON(22), 0, GFLAGS), 1086 COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1087 RK3568_CLKSEL_CON(42), 8, 4, DFLAGS, 1088 RK3568_CLKGATE_CON(22), 1, GFLAGS), 1089 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, 1090 RK3568_CLKGATE_CON(22), 4, GFLAGS), 1091 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, 1092 RK3568_CLKGATE_CON(22), 5, GFLAGS), 1093 1094 /* PD_RGA */ 1095 COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0, 1096 RK3568_CLKSEL_CON(43), 0, 2, MFLAGS, 1097 RK3568_CLKGATE_CON(23), 0, GFLAGS), 1098 COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0, 1099 RK3568_CLKSEL_CON(43), 8, 4, DFLAGS, 1100 RK3568_CLKGATE_CON(23), 1, GFLAGS), 1101 COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0, 1102 RK3568_CLKSEL_CON(43), 12, 4, DFLAGS, 1103 RK3568_CLKGATE_CON(22), 12, GFLAGS), 1104 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, 1105 RK3568_CLKGATE_CON(23), 4, GFLAGS), 1106 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 1107 RK3568_CLKGATE_CON(23), 5, GFLAGS), 1108 COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0, 1109 RK3568_CLKSEL_CON(43), 2, 2, MFLAGS, 1110 RK3568_CLKGATE_CON(23), 6, GFLAGS), 1111 GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0, 1112 RK3568_CLKGATE_CON(23), 7, GFLAGS), 1113 GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0, 1114 RK3568_CLKGATE_CON(23), 8, GFLAGS), 1115 COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0, 1116 RK3568_CLKSEL_CON(43), 4, 2, MFLAGS, 1117 RK3568_CLKGATE_CON(23), 9, GFLAGS), 1118 GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS), 1119 COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0, 1120 RK3568_CLKSEL_CON(43), 6, 2, MFLAGS, 1121 RK3568_CLKGATE_CON(23), 11, GFLAGS), 1122 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0, 1123 RK3568_CLKGATE_CON(23), 12, GFLAGS), 1124 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, 1125 RK3568_CLKGATE_CON(23), 13, GFLAGS), 1126 GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0, 1127 RK3568_CLKGATE_CON(23), 14, GFLAGS), 1128 GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0, 1129 RK3568_CLKGATE_CON(23), 15, GFLAGS), 1130 GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0, 1131 RK3568_CLKGATE_CON(22), 14, GFLAGS), 1132 GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0, 1133 RK3568_CLKGATE_CON(22), 15, GFLAGS), 1134 1135 /* PD_RKVENC */ 1136 COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0, 1137 RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, 1138 RK3568_CLKGATE_CON(24), 0, GFLAGS), 1139 COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1140 RK3568_CLKSEL_CON(44), 8, 4, DFLAGS, 1141 RK3568_CLKGATE_CON(24), 1, GFLAGS), 1142 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, 1143 RK3568_CLKGATE_CON(24), 6, GFLAGS), 1144 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, 1145 RK3568_CLKGATE_CON(24), 7, GFLAGS), 1146 COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0, 1147 RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS, 1148 RK3568_CLKGATE_CON(24), 8, GFLAGS), 1149 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT, 1150 RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS, 1151 RK3568_CLKGATE_CON(25), 0, GFLAGS), 1152 COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1153 RK3568_CLKSEL_CON(47), 8, 4, DFLAGS, 1154 RK3568_CLKGATE_CON(25), 1, GFLAGS), 1155 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, 1156 RK3568_CLKGATE_CON(25), 4, GFLAGS), 1157 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, 1158 RK3568_CLKGATE_CON(25), 5, GFLAGS), 1159 COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0, 1160 RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 1161 RK3568_CLKGATE_CON(25), 6, GFLAGS), 1162 COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT, 1163 RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, 1164 RK3568_CLKGATE_CON(25), 7, GFLAGS), 1165 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0, 1166 RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, 1167 RK3568_CLKGATE_CON(25), 8, GFLAGS), 1168 1169 /* PD_BUS */ 1170 COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0, 1171 RK3568_CLKSEL_CON(50), 0, 2, MFLAGS, 1172 RK3568_CLKGATE_CON(26), 0, GFLAGS), 1173 COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0, 1174 RK3568_CLKSEL_CON(50), 4, 2, MFLAGS, 1175 RK3568_CLKGATE_CON(26), 1, GFLAGS), 1176 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, 1177 RK3568_CLKGATE_CON(26), 4, GFLAGS), 1178 COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0, 1179 RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS, 1180 RK3568_CLKGATE_CON(26), 5, GFLAGS), 1181 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0, 1182 RK3568_CLKSEL_CON(51), 8, 7, DFLAGS, 1183 RK3568_CLKGATE_CON(26), 6, GFLAGS), 1184 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, 1185 RK3568_CLKGATE_CON(26), 7, GFLAGS), 1186 GATE(CLK_SARADC, "clk_saradc", "xin24m", 0, 1187 RK3568_CLKGATE_CON(26), 8, GFLAGS), 1188 GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED, 1189 RK3568_CLKGATE_CON(26), 12, GFLAGS), 1190 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0, 1191 RK3568_CLKGATE_CON(26), 13, GFLAGS), 1192 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, 1193 RK3568_CLKGATE_CON(26), 14, GFLAGS), 1194 GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED, 1195 RK3568_CLKGATE_CON(32), 13, GFLAGS), 1196 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED, 1197 RK3568_CLKGATE_CON(32), 14, GFLAGS), 1198 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, 1199 RK3568_CLKGATE_CON(32), 15, GFLAGS), 1200 1201 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, 1202 RK3568_CLKGATE_CON(27), 12, GFLAGS), 1203 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0, 1204 RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS, 1205 RK3568_CLKGATE_CON(27), 13, GFLAGS), 1206 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 1207 RK3568_CLKSEL_CON(53), 0, 1208 RK3568_CLKGATE_CON(27), 14, GFLAGS, 1209 &rk3568_uart1_fracmux), 1210 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, 1211 RK3568_CLKGATE_CON(27), 15, GFLAGS), 1212 1213 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, 1214 RK3568_CLKGATE_CON(28), 0, GFLAGS), 1215 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0, 1216 RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS, 1217 RK3568_CLKGATE_CON(28), 1, GFLAGS), 1218 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 1219 RK3568_CLKSEL_CON(55), 0, 1220 RK3568_CLKGATE_CON(28), 2, GFLAGS, 1221 &rk3568_uart2_fracmux), 1222 GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0, 1223 RK3568_CLKGATE_CON(28), 3, GFLAGS), 1224 1225 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, 1226 RK3568_CLKGATE_CON(28), 4, GFLAGS), 1227 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0, 1228 RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS, 1229 RK3568_CLKGATE_CON(28), 5, GFLAGS), 1230 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 1231 RK3568_CLKSEL_CON(57), 0, 1232 RK3568_CLKGATE_CON(28), 6, GFLAGS, 1233 &rk3568_uart3_fracmux), 1234 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, 1235 RK3568_CLKGATE_CON(28), 7, GFLAGS), 1236 1237 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, 1238 RK3568_CLKGATE_CON(28), 8, GFLAGS), 1239 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0, 1240 RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS, 1241 RK3568_CLKGATE_CON(28), 9, GFLAGS), 1242 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 1243 RK3568_CLKSEL_CON(59), 0, 1244 RK3568_CLKGATE_CON(28), 10, GFLAGS, 1245 &rk3568_uart4_fracmux), 1246 GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0, 1247 RK3568_CLKGATE_CON(28), 11, GFLAGS), 1248 1249 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0, 1250 RK3568_CLKGATE_CON(28), 12, GFLAGS), 1251 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0, 1252 RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS, 1253 RK3568_CLKGATE_CON(28), 13, GFLAGS), 1254 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 1255 RK3568_CLKSEL_CON(61), 0, 1256 RK3568_CLKGATE_CON(28), 14, GFLAGS, 1257 &rk3568_uart5_fracmux), 1258 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0, 1259 RK3568_CLKGATE_CON(28), 15, GFLAGS), 1260 1261 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0, 1262 RK3568_CLKGATE_CON(29), 0, GFLAGS), 1263 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0, 1264 RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS, 1265 RK3568_CLKGATE_CON(29), 1, GFLAGS), 1266 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 1267 RK3568_CLKSEL_CON(63), 0, 1268 RK3568_CLKGATE_CON(29), 2, GFLAGS, 1269 &rk3568_uart6_fracmux), 1270 GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0, 1271 RK3568_CLKGATE_CON(29), 3, GFLAGS), 1272 1273 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0, 1274 RK3568_CLKGATE_CON(29), 4, GFLAGS), 1275 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0, 1276 RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS, 1277 RK3568_CLKGATE_CON(29), 5, GFLAGS), 1278 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 1279 RK3568_CLKSEL_CON(65), 0, 1280 RK3568_CLKGATE_CON(29), 6, GFLAGS, 1281 &rk3568_uart7_fracmux), 1282 GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0, 1283 RK3568_CLKGATE_CON(29), 7, GFLAGS), 1284 1285 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0, 1286 RK3568_CLKGATE_CON(29), 8, GFLAGS), 1287 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0, 1288 RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS, 1289 RK3568_CLKGATE_CON(29), 9, GFLAGS), 1290 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 1291 RK3568_CLKSEL_CON(67), 0, 1292 RK3568_CLKGATE_CON(29), 10, GFLAGS, 1293 &rk3568_uart8_fracmux), 1294 GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0, 1295 RK3568_CLKGATE_CON(29), 11, GFLAGS), 1296 1297 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0, 1298 RK3568_CLKGATE_CON(29), 12, GFLAGS), 1299 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0, 1300 RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS, 1301 RK3568_CLKGATE_CON(29), 13, GFLAGS), 1302 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 1303 RK3568_CLKSEL_CON(69), 0, 1304 RK3568_CLKGATE_CON(29), 14, GFLAGS, 1305 &rk3568_uart9_fracmux), 1306 GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0, 1307 RK3568_CLKGATE_CON(29), 15, GFLAGS), 1308 1309 GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0, 1310 RK3568_CLKGATE_CON(27), 5, GFLAGS), 1311 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 1312 RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS, 1313 RK3568_CLKGATE_CON(27), 6, GFLAGS), 1314 GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0, 1315 RK3568_CLKGATE_CON(27), 7, GFLAGS), 1316 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 1317 RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS, 1318 RK3568_CLKGATE_CON(27), 8, GFLAGS), 1319 GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0, 1320 RK3568_CLKGATE_CON(27), 9, GFLAGS), 1321 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, 1322 RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS, 1323 RK3568_CLKGATE_CON(27), 10, GFLAGS), 1324 COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0, 1325 RK3568_CLKSEL_CON(71), 8, 2, MFLAGS, 1326 RK3568_CLKGATE_CON(32), 10, GFLAGS), 1327 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, 1328 RK3568_CLKGATE_CON(30), 0, GFLAGS), 1329 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, 1330 RK3568_CLKGATE_CON(30), 1, GFLAGS), 1331 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, 1332 RK3568_CLKGATE_CON(30), 2, GFLAGS), 1333 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, 1334 RK3568_CLKGATE_CON(30), 3, GFLAGS), 1335 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, 1336 RK3568_CLKGATE_CON(30), 4, GFLAGS), 1337 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, 1338 RK3568_CLKGATE_CON(30), 5, GFLAGS), 1339 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, 1340 RK3568_CLKGATE_CON(30), 6, GFLAGS), 1341 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, 1342 RK3568_CLKGATE_CON(30), 7, GFLAGS), 1343 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, 1344 RK3568_CLKGATE_CON(30), 8, GFLAGS), 1345 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, 1346 RK3568_CLKGATE_CON(30), 9, GFLAGS), 1347 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, 1348 RK3568_CLKGATE_CON(30), 10, GFLAGS), 1349 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0, 1350 RK3568_CLKSEL_CON(72), 0, 1, MFLAGS, 1351 RK3568_CLKGATE_CON(30), 11, GFLAGS), 1352 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, 1353 RK3568_CLKGATE_CON(30), 12, GFLAGS), 1354 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0, 1355 RK3568_CLKSEL_CON(72), 2, 1, MFLAGS, 1356 RK3568_CLKGATE_CON(30), 13, GFLAGS), 1357 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, 1358 RK3568_CLKGATE_CON(30), 14, GFLAGS), 1359 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0, 1360 RK3568_CLKSEL_CON(72), 4, 1, MFLAGS, 1361 RK3568_CLKGATE_CON(30), 15, GFLAGS), 1362 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0, 1363 RK3568_CLKGATE_CON(31), 0, GFLAGS), 1364 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0, 1365 RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), 1366 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), 1367 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, 1368 RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, 1369 RK3568_CLKGATE_CON(31), 11, GFLAGS), 1370 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, 1371 RK3568_CLKGATE_CON(31), 12, GFLAGS), 1372 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, 1373 RK3568_CLKGATE_CON(31), 13, GFLAGS), 1374 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, 1375 RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, 1376 RK3568_CLKGATE_CON(31), 14, GFLAGS), 1377 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, 1378 RK3568_CLKGATE_CON(31), 15, GFLAGS), 1379 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, 1380 RK3568_CLKGATE_CON(32), 0, GFLAGS), 1381 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, 1382 RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, 1383 RK3568_CLKGATE_CON(32), 1, GFLAGS), 1384 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, 1385 RK3568_CLKGATE_CON(32), 2, GFLAGS), 1386 COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0, 1387 RK3568_CLKSEL_CON(72), 14, 1, MFLAGS, 1388 RK3568_CLKGATE_CON(32), 11, GFLAGS), 1389 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, 1390 RK3568_CLKGATE_CON(31), 2, GFLAGS), 1391 GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0, 1392 RK3568_CLKGATE_CON(31), 3, GFLAGS), 1393 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, 1394 RK3568_CLKGATE_CON(31), 4, GFLAGS), 1395 GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0, 1396 RK3568_CLKGATE_CON(31), 5, GFLAGS), 1397 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, 1398 RK3568_CLKGATE_CON(31), 6, GFLAGS), 1399 GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0, 1400 RK3568_CLKGATE_CON(31), 7, GFLAGS), 1401 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, 1402 RK3568_CLKGATE_CON(31), 8, GFLAGS), 1403 GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0, 1404 RK3568_CLKGATE_CON(31), 9, GFLAGS), 1405 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, 1406 RK3568_CLKGATE_CON(32), 3, GFLAGS), 1407 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, 1408 RK3568_CLKGATE_CON(32), 4, GFLAGS), 1409 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, 1410 RK3568_CLKGATE_CON(32), 5, GFLAGS), 1411 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, 1412 RK3568_CLKGATE_CON(32), 6, GFLAGS), 1413 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, 1414 RK3568_CLKGATE_CON(32), 7, GFLAGS), 1415 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, 1416 RK3568_CLKGATE_CON(32), 8, GFLAGS), 1417 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, 1418 RK3568_CLKGATE_CON(32), 9, GFLAGS), 1419 1420 /* PD_TOP */ 1421 COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0, 1422 RK3568_CLKSEL_CON(73), 0, 2, MFLAGS, 1423 RK3568_CLKGATE_CON(33), 0, GFLAGS), 1424 COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0, 1425 RK3568_CLKSEL_CON(73), 4, 2, MFLAGS, 1426 RK3568_CLKGATE_CON(33), 1, GFLAGS), 1427 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0, 1428 RK3568_CLKSEL_CON(73), 8, 2, MFLAGS, 1429 RK3568_CLKGATE_CON(33), 2, GFLAGS), 1430 COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0, 1431 RK3568_CLKSEL_CON(73), 12, 2, MFLAGS, 1432 RK3568_CLKGATE_CON(33), 3, GFLAGS), 1433 GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0, 1434 RK3568_CLKGATE_CON(33), 8, GFLAGS), 1435 COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0, 1436 RK3568_CLKSEL_CON(73), 15, 1, MFLAGS, 1437 RK3568_CLKGATE_CON(33), 9, GFLAGS), 1438 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0, 1439 RK3568_CLKGATE_CON(33), 13, GFLAGS), 1440 GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0, 1441 RK3568_CLKGATE_CON(33), 14, GFLAGS), 1442 GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0, 1443 RK3568_CLKGATE_CON(33), 15, GFLAGS), 1444 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0, 1445 RK3568_CLKGATE_CON(34), 4, GFLAGS), 1446 GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0, 1447 RK3568_CLKGATE_CON(34), 5, GFLAGS), 1448 GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0, 1449 RK3568_CLKGATE_CON(34), 6, GFLAGS), 1450 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0, 1451 RK3568_CLKGATE_CON(34), 11, GFLAGS), 1452 GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0, 1453 RK3568_CLKGATE_CON(34), 12, GFLAGS), 1454 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0, 1455 RK3568_CLKGATE_CON(34), 13, GFLAGS), 1456 GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0, 1457 RK3568_CLKGATE_CON(34), 14, GFLAGS), 1458}; 1459 1460static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { 1461 /* PD_PMU */ 1462 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2), 1463 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2), 1464 FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2), 1465 1466 MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, 1467 RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS), 1468 COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0, 1469 RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS, 1470 RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS), 1471 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 1472 RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS), 1473 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 1474 RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS), 1475 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0, 1476 RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS), 1477 COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0, 1478 RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1479 RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS), 1480 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0, 1481 RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS), 1482 1483 COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 1484 RK3568_PMU_CLKSEL_CON(1), 0, 1485 RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS, 1486 &rk3568_rtc32k_pmu_fracmux), 1487 1488 COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED, 1489 RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, 1490 RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS), 1491 1492 COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0, 1493 RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS, 1494 RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS), 1495 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT, 1496 RK3568_PMU_CLKSEL_CON(5), 0, 1497 RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS, 1498 &rk3568_uart0_fracmux), 1499 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0, 1500 RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS), 1501 1502 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0, 1503 RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS), 1504 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0, 1505 RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 1506 RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS), 1507 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0, 1508 RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS), 1509 COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0, 1510 RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS, 1511 RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS), 1512 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0, 1513 RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS), 1514 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0, 1515 RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS), 1516 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0, 1517 RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS), 1518 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0, 1519 RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS), 1520 COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0, 1521 RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS, 1522 RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS), 1523 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0, 1524 RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS), 1525 MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, 1526 RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS), 1527 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0, 1528 RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS), 1529 MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, 1530 RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS), 1531 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0, 1532 RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS), 1533 MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, 1534 RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS), 1535 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0, 1536 RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS), 1537 MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, 1538 RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS), 1539 COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0, 1540 RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS, 1541 RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS), 1542 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0, 1543 RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS), 1544 MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT, 1545 RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS), 1546 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, 1547 RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS, 1548 RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS), 1549 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0, 1550 RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS), 1551 MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT, 1552 RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS), 1553 COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0, 1554 RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS, 1555 RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS), 1556 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0, 1557 RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS), 1558 MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT, 1559 RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS), 1560 COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0, 1561 RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS, 1562 RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS), 1563 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0, 1564 RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS), 1565 MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT, 1566 RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS), 1567 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0, 1568 RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS), 1569 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0, 1570 RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), 1571 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, 1572 RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), 1573 MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, 1574 RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), 1575}; 1576 1577static const char *const rk3568_cru_critical_clocks[] __initconst = { 1578 "armclk", 1579 "pclk_core_pre", 1580 "aclk_bus", 1581 "pclk_bus", 1582 "aclk_top_high", 1583 "aclk_top_low", 1584 "hclk_top", 1585 "pclk_top", 1586 "aclk_perimid", 1587 "hclk_perimid", 1588 "aclk_secure_flash", 1589 "hclk_secure_flash", 1590 "aclk_core_niu2bus", 1591 "npll", 1592 "clk_optc_arb", 1593 "hclk_php", 1594 "pclk_php", 1595 "hclk_usb", 1596 "hclk_vo", 1597}; 1598 1599static const char *const rk3568_pmucru_critical_clocks[] __initconst = { 1600 "pclk_pdpmu", 1601 "pclk_pmu", 1602 "clk_pmu", 1603}; 1604 1605static void __init rk3568_pmu_clk_init(struct device_node *np) 1606{ 1607 struct rockchip_clk_provider *ctx; 1608 void __iomem *reg_base; 1609 1610 reg_base = of_iomap(np, 0); 1611 if (!reg_base) { 1612 pr_err("%s: could not map cru pmu region\n", __func__); 1613 return; 1614 } 1615 1616 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1617 if (IS_ERR(ctx)) { 1618 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1619 return; 1620 } 1621 1622 rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks, 1623 ARRAY_SIZE(rk3568_pmu_pll_clks), 1624 RK3568_GRF_SOC_STATUS0); 1625 1626 rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches, 1627 ARRAY_SIZE(rk3568_clk_pmu_branches)); 1628 1629 rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0), 1630 ROCKCHIP_SOFTRST_HIWORD_MASK); 1631 1632 rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks, 1633 ARRAY_SIZE(rk3568_pmucru_critical_clocks)); 1634 1635 rockchip_clk_of_add_provider(np, ctx); 1636} 1637 1638CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init); 1639 1640static void __init rk3568_clk_init(struct device_node *np) 1641{ 1642 struct rockchip_clk_provider *ctx; 1643 void __iomem *reg_base; 1644 1645 reg_base = of_iomap(np, 0); 1646 if (!reg_base) { 1647 pr_err("%s: could not map cru region\n", __func__); 1648 return; 1649 } 1650 1651 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 1652 if (IS_ERR(ctx)) { 1653 pr_err("%s: rockchip clk init failed\n", __func__); 1654 iounmap(reg_base); 1655 return; 1656 } 1657 1658 rockchip_clk_register_plls(ctx, rk3568_pll_clks, 1659 ARRAY_SIZE(rk3568_pll_clks), 1660 RK3568_GRF_SOC_STATUS0); 1661 1662 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 1663 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 1664 &rk3568_cpuclk_data, rk3568_cpuclk_rates, 1665 ARRAY_SIZE(rk3568_cpuclk_rates)); 1666 1667 rockchip_clk_register_branches(ctx, rk3568_clk_branches, 1668 ARRAY_SIZE(rk3568_clk_branches)); 1669 1670 rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0), 1671 ROCKCHIP_SOFTRST_HIWORD_MASK); 1672 1673 rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL); 1674 1675 rockchip_clk_protect_critical(rk3568_cru_critical_clocks, 1676 ARRAY_SIZE(rk3568_cru_critical_clocks)); 1677 1678 rockchip_clk_of_add_provider(np, ctx); 1679} 1680 1681CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init); 1682 1683struct clk_rk3568_inits { 1684 void (*inits)(struct device_node *np); 1685}; 1686 1687static const struct clk_rk3568_inits clk_rk3568_pmucru_init = { 1688 .inits = rk3568_pmu_clk_init, 1689}; 1690 1691static const struct clk_rk3568_inits clk_3568_cru_init = { 1692 .inits = rk3568_clk_init, 1693}; 1694 1695static const struct of_device_id clk_rk3568_match_table[] = { 1696 { 1697 .compatible = "rockchip,rk3568-cru", 1698 .data = &clk_3568_cru_init, 1699 }, { 1700 .compatible = "rockchip,rk3568-pmucru", 1701 .data = &clk_rk3568_pmucru_init, 1702 }, 1703 { } 1704}; 1705 1706static int __init clk_rk3568_probe(struct platform_device *pdev) 1707{ 1708 struct device_node *np = pdev->dev.of_node; 1709 const struct clk_rk3568_inits *init_data; 1710 1711 init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev); 1712 if (!init_data) 1713 return -EINVAL; 1714 1715 if (init_data->inits) 1716 init_data->inits(np); 1717 1718 return 0; 1719} 1720 1721static struct platform_driver clk_rk3568_driver = { 1722 .driver = { 1723 .name = "clk-rk3568", 1724 .of_match_table = clk_rk3568_match_table, 1725 .suppress_bind_attrs = true, 1726 }, 1727}; 1728builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe); 1729