1// SPDX-License-Identifier: GPL-2.0 2/* 3 * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 * Based on r8a779a0-cpg-mssr.c 8 */ 9 10#include <linux/bitfield.h> 11#include <linux/clk.h> 12#include <linux/clk-provider.h> 13#include <linux/device.h> 14#include <linux/err.h> 15#include <linux/kernel.h> 16#include <linux/soc/renesas/rcar-rst.h> 17 18#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 19 20#include "renesas-cpg-mssr.h" 21#include "rcar-gen4-cpg.h" 22 23enum clk_ids { 24 /* Core Clock Outputs exported to DT */ 25 LAST_DT_CORE_CLK = R8A779F0_CLK_R, 26 27 /* External Input Clocks */ 28 CLK_EXTAL, 29 CLK_EXTALR, 30 31 /* Internal Core Clocks */ 32 CLK_MAIN, 33 CLK_PLL1, 34 CLK_PLL2, 35 CLK_PLL3, 36 CLK_PLL5, 37 CLK_PLL6, 38 CLK_PLL1_DIV2, 39 CLK_PLL2_DIV2, 40 CLK_PLL3_DIV2, 41 CLK_PLL5_DIV2, 42 CLK_PLL5_DIV4, 43 CLK_PLL6_DIV2, 44 CLK_S0, 45 CLK_SASYNCPER, 46 CLK_SDSRC, 47 CLK_RPCSRC, 48 CLK_OCO, 49 50 /* Module Clocks */ 51 MOD_CLK_BASE 52}; 53 54static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 55 /* External Clock Inputs */ 56 DEF_INPUT("extal", CLK_EXTAL), 57 DEF_INPUT("extalr", CLK_EXTALR), 58 59 /* Internal Core Clocks */ 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), 61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), 62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), 63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), 64 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), 65 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), 66 67 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 68 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), 69 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), 70 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 71 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 72 DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), 73 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 74 75 DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), 76 DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), 77 DEF_RATE(".oco", CLK_OCO, 32768), 78 79 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), 80 81 /* Core Clock Outputs */ 82 DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0), 83 DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8), 84 DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), 85 DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), 86 DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), 87 DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), 88 DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), 89 DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), 90 DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), 91 DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), 92 DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), 93 DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), 94 DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), 95 DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), 96 DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), 97 DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), 98 DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), 99 DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), 100 DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), 101 DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), 102 DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), 103 DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), 104 DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), 105 DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), 106 DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), 107 DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), 108 DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), 109 DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1), 110 DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 111 DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), 112 113 DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), 114 DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1), 115 DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), 116 DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), 117 118 DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), 119 DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870), 120 121 DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), 122 DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), 123 124 DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 125 126 DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), 127 DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 128}; 129 130static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 131 DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1), 132 DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1), 133 DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1), 134 DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1), 135 DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), 136 DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), 137 DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER), 138 DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER), 139 DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER), 140 DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER), 141 DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO), 142 DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO), 143 DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO), 144 DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO), 145 DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2), 146 DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2), 147 DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4), 148 DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4), 149 DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4), 150 DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4), 151 DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), 152 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), 153 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), 154 DEF_MOD("tmu0", 713, R8A779F0_CLK_SASYNCRT), 155 DEF_MOD("tmu1", 714, R8A779F0_CLK_SASYNCPERD2), 156 DEF_MOD("tmu2", 715, R8A779F0_CLK_SASYNCPERD2), 157 DEF_MOD("tmu3", 716, R8A779F0_CLK_SASYNCPERD2), 158 DEF_MOD("tmu4", 717, R8A779F0_CLK_SASYNCPERD2), 159 DEF_MOD("wdt", 907, R8A779F0_CLK_R), 160 DEF_MOD("cmt0", 910, R8A779F0_CLK_R), 161 DEF_MOD("cmt1", 911, R8A779F0_CLK_R), 162 DEF_MOD("cmt2", 912, R8A779F0_CLK_R), 163 DEF_MOD("cmt3", 913, R8A779F0_CLK_R), 164 DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX), 165 DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), 166 DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2), 167 DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC), 168 DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), 169}; 170 171static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { 172 MOD_CLK_ID(907), /* WDT */ 173}; 174 175/* 176 * CPG Clock Data 177 */ 178/* 179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC 180 * 14 13 (MHz) 181 * ------------------------------------------------------------------------ 182 * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15 183 * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19 184 * 1 0 Prohibited setting 185 * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38 186 */ 187#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 188 (((md) & BIT(13)) >> 13)) 189 190static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { 191 /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ 192 { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, }, 193 { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, }, 194 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 195 { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, }, 196}; 197 198static int __init r8a779f0_cpg_mssr_init(struct device *dev) 199{ 200 const struct rcar_gen4_cpg_pll_config *cpg_pll_config; 201 u32 cpg_mode; 202 int error; 203 204 error = rcar_rst_read_mode_pins(&cpg_mode); 205 if (error) 206 return error; 207 208 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 209 if (!cpg_pll_config->extal_div) { 210 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 211 return -EINVAL; 212 } 213 214 return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 215} 216 217const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { 218 /* Core Clocks */ 219 .core_clks = r8a779f0_core_clks, 220 .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks), 221 .last_dt_core_clk = LAST_DT_CORE_CLK, 222 .num_total_core_clks = MOD_CLK_BASE, 223 224 /* Module Clocks */ 225 .mod_clks = r8a779f0_mod_clks, 226 .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), 227 .num_hw_mod_clks = 28 * 32, 228 229 /* Critical Module Clocks */ 230 .crit_mod_clks = r8a779f0_crit_mod_clks, 231 .num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks), 232 233 /* Callbacks */ 234 .init = r8a779f0_cpg_mssr_init, 235 .cpg_clk_register = rcar_gen4_cpg_clk_register, 236 237 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, 238}; 239