1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 3 4#include <linux/kernel.h> 5#include <linux/bitops.h> 6#include <linux/err.h> 7#include <linux/platform_device.h> 8#include <linux/module.h> 9#include <linux/of.h> 10#include <linux/clk-provider.h> 11#include <linux/regmap.h> 12#include <linux/reset-controller.h> 13 14#include <dt-bindings/clock/qcom,gcc-sm8150.h> 15 16#include "common.h" 17#include "clk-alpha-pll.h" 18#include "clk-branch.h" 19#include "clk-pll.h" 20#include "clk-rcg.h" 21#include "clk-regmap.h" 22#include "reset.h" 23#include "gdsc.h" 24 25enum { 26 P_BI_TCXO, 27 P_AUD_REF_CLK, 28 P_GPLL0_OUT_EVEN, 29 P_GPLL0_OUT_MAIN, 30 P_GPLL7_OUT_MAIN, 31 P_GPLL9_OUT_MAIN, 32 P_SLEEP_CLK, 33}; 34 35static struct clk_alpha_pll gpll0 = { 36 .offset = 0x0, 37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 38 .clkr = { 39 .enable_reg = 0x52000, 40 .enable_mask = BIT(0), 41 .hw.init = &(struct clk_init_data){ 42 .name = "gpll0", 43 .parent_data = &(const struct clk_parent_data){ 44 .fw_name = "bi_tcxo", 45 .name = "bi_tcxo", 46 }, 47 .num_parents = 1, 48 .ops = &clk_alpha_pll_fixed_trion_ops, 49 }, 50 }, 51}; 52 53static const struct clk_div_table post_div_table_trion_even[] = { 54 { 0x0, 1 }, 55 { 0x1, 2 }, 56 { 0x3, 4 }, 57 { 0x7, 8 }, 58 { } 59}; 60 61static struct clk_alpha_pll_postdiv gpll0_out_even = { 62 .offset = 0x0, 63 .post_div_shift = 8, 64 .post_div_table = post_div_table_trion_even, 65 .num_post_div = ARRAY_SIZE(post_div_table_trion_even), 66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 67 .width = 4, 68 .clkr.hw.init = &(struct clk_init_data){ 69 .name = "gpll0_out_even", 70 .parent_hws = (const struct clk_hw*[]){ 71 &gpll0.clkr.hw, 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_postdiv_trion_ops, 75 }, 76}; 77 78static struct clk_alpha_pll gpll7 = { 79 .offset = 0x1a000, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 81 .clkr = { 82 .enable_reg = 0x52000, 83 .enable_mask = BIT(7), 84 .hw.init = &(struct clk_init_data){ 85 .name = "gpll7", 86 .parent_data = &(const struct clk_parent_data){ 87 .fw_name = "bi_tcxo", 88 .name = "bi_tcxo", 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_fixed_trion_ops, 92 }, 93 }, 94}; 95 96static struct clk_alpha_pll gpll9 = { 97 .offset = 0x1c000, 98 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 99 .clkr = { 100 .enable_reg = 0x52000, 101 .enable_mask = BIT(9), 102 .hw.init = &(struct clk_init_data){ 103 .name = "gpll9", 104 .parent_data = &(const struct clk_parent_data){ 105 .fw_name = "bi_tcxo", 106 .name = "bi_tcxo", 107 }, 108 .num_parents = 1, 109 .ops = &clk_alpha_pll_fixed_trion_ops, 110 }, 111 }, 112}; 113 114static const struct parent_map gcc_parent_map_0[] = { 115 { P_BI_TCXO, 0 }, 116 { P_GPLL0_OUT_MAIN, 1 }, 117 { P_GPLL0_OUT_EVEN, 6 }, 118}; 119 120static const struct clk_parent_data gcc_parents_0[] = { 121 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 122 { .hw = &gpll0.clkr.hw }, 123 { .hw = &gpll0_out_even.clkr.hw }, 124}; 125 126static const struct parent_map gcc_parent_map_1[] = { 127 { P_BI_TCXO, 0 }, 128 { P_GPLL0_OUT_MAIN, 1 }, 129 { P_SLEEP_CLK, 5 }, 130 { P_GPLL0_OUT_EVEN, 6 }, 131}; 132 133static const struct clk_parent_data gcc_parents_1[] = { 134 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 135 { .hw = &gpll0.clkr.hw }, 136 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 137 { .hw = &gpll0_out_even.clkr.hw }, 138}; 139 140static const struct parent_map gcc_parent_map_2[] = { 141 { P_BI_TCXO, 0 }, 142 { P_SLEEP_CLK, 5 }, 143}; 144 145static const struct clk_parent_data gcc_parents_2[] = { 146 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 147 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 148}; 149 150static const struct parent_map gcc_parent_map_3[] = { 151 { P_BI_TCXO, 0 }, 152 { P_GPLL0_OUT_MAIN, 1 }, 153}; 154 155static const struct clk_parent_data gcc_parents_3[] = { 156 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 157 { .hw = &gpll0.clkr.hw }, 158}; 159 160static const struct parent_map gcc_parent_map_4[] = { 161 { P_BI_TCXO, 0 }, 162}; 163 164static const struct clk_parent_data gcc_parents_4[] = { 165 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 166}; 167 168static const struct parent_map gcc_parent_map_5[] = { 169 { P_BI_TCXO, 0 }, 170 { P_GPLL0_OUT_MAIN, 1 }, 171 { P_GPLL7_OUT_MAIN, 3 }, 172 { P_GPLL0_OUT_EVEN, 6 }, 173}; 174 175static const struct clk_parent_data gcc_parents_5[] = { 176 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 177 { .hw = &gpll0.clkr.hw }, 178 { .hw = &gpll7.clkr.hw }, 179 { .hw = &gpll0_out_even.clkr.hw }, 180}; 181 182static const struct parent_map gcc_parent_map_6[] = { 183 { P_BI_TCXO, 0 }, 184 { P_GPLL0_OUT_MAIN, 1 }, 185 { P_GPLL9_OUT_MAIN, 2 }, 186 { P_GPLL0_OUT_EVEN, 6 }, 187}; 188 189static const struct clk_parent_data gcc_parents_6[] = { 190 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 191 { .hw = &gpll0.clkr.hw }, 192 { .hw = &gpll9.clkr.hw }, 193 { .hw = &gpll0_out_even.clkr.hw }, 194}; 195 196static const struct parent_map gcc_parent_map_7[] = { 197 { P_BI_TCXO, 0 }, 198 { P_GPLL0_OUT_MAIN, 1 }, 199 { P_AUD_REF_CLK, 2 }, 200 { P_GPLL0_OUT_EVEN, 6 }, 201}; 202 203static const struct clk_parent_data gcc_parents_7[] = { 204 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 205 { .hw = &gpll0.clkr.hw }, 206 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, 207 { .hw = &gpll0_out_even.clkr.hw }, 208}; 209 210static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 211 F(19200000, P_BI_TCXO, 1, 0, 0), 212 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 213 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 214 { } 215}; 216 217static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 218 .cmd_rcgr = 0x48014, 219 .mnd_width = 0, 220 .hid_width = 5, 221 .parent_map = gcc_parent_map_0, 222 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 223 .clkr.hw.init = &(struct clk_init_data){ 224 .name = "gcc_cpuss_ahb_clk_src", 225 .parent_data = gcc_parents_0, 226 .num_parents = ARRAY_SIZE(gcc_parents_0), 227 .flags = CLK_SET_RATE_PARENT, 228 .ops = &clk_rcg2_ops, 229 }, 230}; 231 232static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { 233 F(19200000, P_BI_TCXO, 1, 0, 0), 234 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 235 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 236 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 237 { } 238}; 239 240static struct clk_rcg2 gcc_emac_ptp_clk_src = { 241 .cmd_rcgr = 0x6038, 242 .mnd_width = 0, 243 .hid_width = 5, 244 .parent_map = gcc_parent_map_5, 245 .freq_tbl = ftbl_gcc_emac_ptp_clk_src, 246 .clkr.hw.init = &(struct clk_init_data){ 247 .name = "gcc_emac_ptp_clk_src", 248 .parent_data = gcc_parents_5, 249 .num_parents = ARRAY_SIZE(gcc_parents_5), 250 .flags = CLK_SET_RATE_PARENT, 251 .ops = &clk_rcg2_ops, 252 }, 253}; 254 255static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { 256 F(2500000, P_BI_TCXO, 1, 25, 192), 257 F(5000000, P_BI_TCXO, 1, 25, 96), 258 F(19200000, P_BI_TCXO, 1, 0, 0), 259 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 260 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 261 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), 262 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), 263 { } 264}; 265 266static struct clk_rcg2 gcc_emac_rgmii_clk_src = { 267 .cmd_rcgr = 0x601c, 268 .mnd_width = 8, 269 .hid_width = 5, 270 .parent_map = gcc_parent_map_5, 271 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, 272 .clkr.hw.init = &(struct clk_init_data){ 273 .name = "gcc_emac_rgmii_clk_src", 274 .parent_data = gcc_parents_5, 275 .num_parents = ARRAY_SIZE(gcc_parents_5), 276 .flags = CLK_SET_RATE_PARENT, 277 .ops = &clk_rcg2_ops, 278 }, 279}; 280 281static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 282 F(19200000, P_BI_TCXO, 1, 0, 0), 283 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 284 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 285 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 286 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 287 { } 288}; 289 290static struct clk_rcg2 gcc_gp1_clk_src = { 291 .cmd_rcgr = 0x64004, 292 .mnd_width = 8, 293 .hid_width = 5, 294 .parent_map = gcc_parent_map_1, 295 .freq_tbl = ftbl_gcc_gp1_clk_src, 296 .clkr.hw.init = &(struct clk_init_data){ 297 .name = "gcc_gp1_clk_src", 298 .parent_data = gcc_parents_1, 299 .num_parents = ARRAY_SIZE(gcc_parents_1), 300 .flags = CLK_SET_RATE_PARENT, 301 .ops = &clk_rcg2_ops, 302 }, 303}; 304 305static struct clk_rcg2 gcc_gp2_clk_src = { 306 .cmd_rcgr = 0x65004, 307 .mnd_width = 8, 308 .hid_width = 5, 309 .parent_map = gcc_parent_map_1, 310 .freq_tbl = ftbl_gcc_gp1_clk_src, 311 .clkr.hw.init = &(struct clk_init_data){ 312 .name = "gcc_gp2_clk_src", 313 .parent_data = gcc_parents_1, 314 .num_parents = ARRAY_SIZE(gcc_parents_1), 315 .flags = CLK_SET_RATE_PARENT, 316 .ops = &clk_rcg2_ops, 317 }, 318}; 319 320static struct clk_rcg2 gcc_gp3_clk_src = { 321 .cmd_rcgr = 0x66004, 322 .mnd_width = 8, 323 .hid_width = 5, 324 .parent_map = gcc_parent_map_1, 325 .freq_tbl = ftbl_gcc_gp1_clk_src, 326 .clkr.hw.init = &(struct clk_init_data){ 327 .name = "gcc_gp3_clk_src", 328 .parent_data = gcc_parents_1, 329 .num_parents = ARRAY_SIZE(gcc_parents_1), 330 .flags = CLK_SET_RATE_PARENT, 331 .ops = &clk_rcg2_ops, 332 }, 333}; 334 335static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 336 F(9600000, P_BI_TCXO, 2, 0, 0), 337 F(19200000, P_BI_TCXO, 1, 0, 0), 338 { } 339}; 340 341static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 342 .cmd_rcgr = 0x6b02c, 343 .mnd_width = 16, 344 .hid_width = 5, 345 .parent_map = gcc_parent_map_2, 346 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 347 .clkr.hw.init = &(struct clk_init_data){ 348 .name = "gcc_pcie_0_aux_clk_src", 349 .parent_data = gcc_parents_2, 350 .num_parents = ARRAY_SIZE(gcc_parents_2), 351 .flags = CLK_SET_RATE_PARENT, 352 .ops = &clk_rcg2_ops, 353 }, 354}; 355 356static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 357 .cmd_rcgr = 0x8d02c, 358 .mnd_width = 16, 359 .hid_width = 5, 360 .parent_map = gcc_parent_map_2, 361 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 362 .clkr.hw.init = &(struct clk_init_data){ 363 .name = "gcc_pcie_1_aux_clk_src", 364 .parent_data = gcc_parents_2, 365 .num_parents = ARRAY_SIZE(gcc_parents_2), 366 .flags = CLK_SET_RATE_PARENT, 367 .ops = &clk_rcg2_ops, 368 }, 369}; 370 371static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { 372 F(19200000, P_BI_TCXO, 1, 0, 0), 373 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 374 { } 375}; 376 377static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { 378 .cmd_rcgr = 0x6f014, 379 .mnd_width = 0, 380 .hid_width = 5, 381 .parent_map = gcc_parent_map_0, 382 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, 383 .clkr.hw.init = &(struct clk_init_data){ 384 .name = "gcc_pcie_phy_refgen_clk_src", 385 .parent_data = gcc_parents_0, 386 .num_parents = ARRAY_SIZE(gcc_parents_0), 387 .flags = CLK_SET_RATE_PARENT, 388 .ops = &clk_rcg2_ops, 389 }, 390}; 391 392static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 393 F(9600000, P_BI_TCXO, 2, 0, 0), 394 F(19200000, P_BI_TCXO, 1, 0, 0), 395 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 396 { } 397}; 398 399static struct clk_rcg2 gcc_pdm2_clk_src = { 400 .cmd_rcgr = 0x33010, 401 .mnd_width = 0, 402 .hid_width = 5, 403 .parent_map = gcc_parent_map_0, 404 .freq_tbl = ftbl_gcc_pdm2_clk_src, 405 .clkr.hw.init = &(struct clk_init_data){ 406 .name = "gcc_pdm2_clk_src", 407 .parent_data = gcc_parents_0, 408 .num_parents = ARRAY_SIZE(gcc_parents_0), 409 .flags = CLK_SET_RATE_PARENT, 410 .ops = &clk_rcg2_ops, 411 }, 412}; 413 414static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { 415 F(19200000, P_BI_TCXO, 1, 0, 0), 416 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 417 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 418 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 419 { } 420}; 421 422static struct clk_rcg2 gcc_qspi_core_clk_src = { 423 .cmd_rcgr = 0x4b008, 424 .mnd_width = 0, 425 .hid_width = 5, 426 .parent_map = gcc_parent_map_0, 427 .freq_tbl = ftbl_gcc_qspi_core_clk_src, 428 .clkr.hw.init = &(struct clk_init_data){ 429 .name = "gcc_qspi_core_clk_src", 430 .parent_data = gcc_parents_0, 431 .num_parents = ARRAY_SIZE(gcc_parents_0), 432 .flags = CLK_SET_RATE_PARENT, 433 .ops = &clk_rcg2_ops, 434 }, 435}; 436 437static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 438 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), 439 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), 440 F(19200000, P_BI_TCXO, 1, 0, 0), 441 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), 442 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), 443 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), 444 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), 445 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), 446 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), 447 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), 448 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), 449 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), 450 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), 451 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), 452 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), 453 { } 454}; 455 456static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 457 .cmd_rcgr = 0x17148, 458 .mnd_width = 16, 459 .hid_width = 5, 460 .parent_map = gcc_parent_map_0, 461 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 462 .clkr.hw.init = &(struct clk_init_data){ 463 .name = "gcc_qupv3_wrap0_s0_clk_src", 464 .parent_data = gcc_parents_0, 465 .num_parents = ARRAY_SIZE(gcc_parents_0), 466 .flags = CLK_SET_RATE_PARENT, 467 .ops = &clk_rcg2_ops, 468 }, 469}; 470 471static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 472 .cmd_rcgr = 0x17278, 473 .mnd_width = 16, 474 .hid_width = 5, 475 .parent_map = gcc_parent_map_0, 476 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 477 .clkr.hw.init = &(struct clk_init_data){ 478 .name = "gcc_qupv3_wrap0_s1_clk_src", 479 .parent_data = gcc_parents_0, 480 .num_parents = ARRAY_SIZE(gcc_parents_0), 481 .flags = CLK_SET_RATE_PARENT, 482 .ops = &clk_rcg2_ops, 483 }, 484}; 485 486static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 487 .cmd_rcgr = 0x173a8, 488 .mnd_width = 16, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_0, 491 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "gcc_qupv3_wrap0_s2_clk_src", 494 .parent_data = gcc_parents_0, 495 .num_parents = ARRAY_SIZE(gcc_parents_0), 496 .flags = CLK_SET_RATE_PARENT, 497 .ops = &clk_rcg2_ops, 498 }, 499}; 500 501static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 502 .cmd_rcgr = 0x174d8, 503 .mnd_width = 16, 504 .hid_width = 5, 505 .parent_map = gcc_parent_map_0, 506 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 507 .clkr.hw.init = &(struct clk_init_data){ 508 .name = "gcc_qupv3_wrap0_s3_clk_src", 509 .parent_data = gcc_parents_0, 510 .num_parents = ARRAY_SIZE(gcc_parents_0), 511 .flags = CLK_SET_RATE_PARENT, 512 .ops = &clk_rcg2_ops, 513 }, 514}; 515 516static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 517 .cmd_rcgr = 0x17608, 518 .mnd_width = 16, 519 .hid_width = 5, 520 .parent_map = gcc_parent_map_0, 521 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 522 .clkr.hw.init = &(struct clk_init_data){ 523 .name = "gcc_qupv3_wrap0_s4_clk_src", 524 .parent_data = gcc_parents_0, 525 .num_parents = ARRAY_SIZE(gcc_parents_0), 526 .flags = CLK_SET_RATE_PARENT, 527 .ops = &clk_rcg2_ops, 528 }, 529}; 530 531static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 532 .cmd_rcgr = 0x17738, 533 .mnd_width = 16, 534 .hid_width = 5, 535 .parent_map = gcc_parent_map_0, 536 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 537 .clkr.hw.init = &(struct clk_init_data){ 538 .name = "gcc_qupv3_wrap0_s5_clk_src", 539 .parent_data = gcc_parents_0, 540 .num_parents = ARRAY_SIZE(gcc_parents_0), 541 .flags = CLK_SET_RATE_PARENT, 542 .ops = &clk_rcg2_ops, 543 }, 544}; 545 546static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 547 .cmd_rcgr = 0x17868, 548 .mnd_width = 16, 549 .hid_width = 5, 550 .parent_map = gcc_parent_map_0, 551 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 552 .clkr.hw.init = &(struct clk_init_data){ 553 .name = "gcc_qupv3_wrap0_s6_clk_src", 554 .parent_data = gcc_parents_0, 555 .num_parents = ARRAY_SIZE(gcc_parents_0), 556 .flags = CLK_SET_RATE_PARENT, 557 .ops = &clk_rcg2_ops, 558 }, 559}; 560 561static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 562 .cmd_rcgr = 0x17998, 563 .mnd_width = 16, 564 .hid_width = 5, 565 .parent_map = gcc_parent_map_0, 566 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 567 .clkr.hw.init = &(struct clk_init_data){ 568 .name = "gcc_qupv3_wrap0_s7_clk_src", 569 .parent_data = gcc_parents_0, 570 .num_parents = ARRAY_SIZE(gcc_parents_0), 571 .flags = CLK_SET_RATE_PARENT, 572 .ops = &clk_rcg2_ops, 573 }, 574}; 575 576static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 577 .cmd_rcgr = 0x18148, 578 .mnd_width = 16, 579 .hid_width = 5, 580 .parent_map = gcc_parent_map_0, 581 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 582 .clkr.hw.init = &(struct clk_init_data){ 583 .name = "gcc_qupv3_wrap1_s0_clk_src", 584 .parent_data = gcc_parents_0, 585 .num_parents = ARRAY_SIZE(gcc_parents_0), 586 .flags = CLK_SET_RATE_PARENT, 587 .ops = &clk_rcg2_ops, 588 }, 589}; 590 591static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 592 .cmd_rcgr = 0x18278, 593 .mnd_width = 16, 594 .hid_width = 5, 595 .parent_map = gcc_parent_map_0, 596 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 597 .clkr.hw.init = &(struct clk_init_data){ 598 .name = "gcc_qupv3_wrap1_s1_clk_src", 599 .parent_data = gcc_parents_0, 600 .num_parents = ARRAY_SIZE(gcc_parents_0), 601 .flags = CLK_SET_RATE_PARENT, 602 .ops = &clk_rcg2_ops, 603 }, 604}; 605 606static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 607 .cmd_rcgr = 0x183a8, 608 .mnd_width = 16, 609 .hid_width = 5, 610 .parent_map = gcc_parent_map_0, 611 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 612 .clkr.hw.init = &(struct clk_init_data){ 613 .name = "gcc_qupv3_wrap1_s2_clk_src", 614 .parent_data = gcc_parents_0, 615 .num_parents = ARRAY_SIZE(gcc_parents_0), 616 .flags = CLK_SET_RATE_PARENT, 617 .ops = &clk_rcg2_ops, 618 }, 619}; 620 621static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 622 .cmd_rcgr = 0x184d8, 623 .mnd_width = 16, 624 .hid_width = 5, 625 .parent_map = gcc_parent_map_0, 626 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 627 .clkr.hw.init = &(struct clk_init_data){ 628 .name = "gcc_qupv3_wrap1_s3_clk_src", 629 .parent_data = gcc_parents_0, 630 .num_parents = ARRAY_SIZE(gcc_parents_0), 631 .flags = CLK_SET_RATE_PARENT, 632 .ops = &clk_rcg2_ops, 633 }, 634}; 635 636static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 637 .cmd_rcgr = 0x18608, 638 .mnd_width = 16, 639 .hid_width = 5, 640 .parent_map = gcc_parent_map_0, 641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 642 .clkr.hw.init = &(struct clk_init_data){ 643 .name = "gcc_qupv3_wrap1_s4_clk_src", 644 .parent_data = gcc_parents_0, 645 .num_parents = ARRAY_SIZE(gcc_parents_0), 646 .flags = CLK_SET_RATE_PARENT, 647 .ops = &clk_rcg2_ops, 648 }, 649}; 650 651static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 652 .cmd_rcgr = 0x18738, 653 .mnd_width = 16, 654 .hid_width = 5, 655 .parent_map = gcc_parent_map_0, 656 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 657 .clkr.hw.init = &(struct clk_init_data){ 658 .name = "gcc_qupv3_wrap1_s5_clk_src", 659 .parent_data = gcc_parents_0, 660 .num_parents = ARRAY_SIZE(gcc_parents_0), 661 .flags = CLK_SET_RATE_PARENT, 662 .ops = &clk_rcg2_ops, 663 }, 664}; 665 666static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 667 .cmd_rcgr = 0x1e148, 668 .mnd_width = 16, 669 .hid_width = 5, 670 .parent_map = gcc_parent_map_0, 671 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 672 .clkr.hw.init = &(struct clk_init_data){ 673 .name = "gcc_qupv3_wrap2_s0_clk_src", 674 .parent_data = gcc_parents_0, 675 .num_parents = ARRAY_SIZE(gcc_parents_0), 676 .flags = CLK_SET_RATE_PARENT, 677 .ops = &clk_rcg2_ops, 678 }, 679}; 680 681static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 682 .cmd_rcgr = 0x1e278, 683 .mnd_width = 16, 684 .hid_width = 5, 685 .parent_map = gcc_parent_map_0, 686 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 687 .clkr.hw.init = &(struct clk_init_data){ 688 .name = "gcc_qupv3_wrap2_s1_clk_src", 689 .parent_data = gcc_parents_0, 690 .num_parents = ARRAY_SIZE(gcc_parents_0), 691 .flags = CLK_SET_RATE_PARENT, 692 .ops = &clk_rcg2_ops, 693 }, 694}; 695 696static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 697 .cmd_rcgr = 0x1e3a8, 698 .mnd_width = 16, 699 .hid_width = 5, 700 .parent_map = gcc_parent_map_0, 701 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 702 .clkr.hw.init = &(struct clk_init_data){ 703 .name = "gcc_qupv3_wrap2_s2_clk_src", 704 .parent_data = gcc_parents_0, 705 .num_parents = ARRAY_SIZE(gcc_parents_0), 706 .flags = CLK_SET_RATE_PARENT, 707 .ops = &clk_rcg2_ops, 708 }, 709}; 710 711static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 712 .cmd_rcgr = 0x1e4d8, 713 .mnd_width = 16, 714 .hid_width = 5, 715 .parent_map = gcc_parent_map_0, 716 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 717 .clkr.hw.init = &(struct clk_init_data){ 718 .name = "gcc_qupv3_wrap2_s3_clk_src", 719 .parent_data = gcc_parents_0, 720 .num_parents = ARRAY_SIZE(gcc_parents_0), 721 .flags = CLK_SET_RATE_PARENT, 722 .ops = &clk_rcg2_ops, 723 }, 724}; 725 726static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 727 .cmd_rcgr = 0x1e608, 728 .mnd_width = 16, 729 .hid_width = 5, 730 .parent_map = gcc_parent_map_0, 731 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 732 .clkr.hw.init = &(struct clk_init_data){ 733 .name = "gcc_qupv3_wrap2_s4_clk_src", 734 .parent_data = gcc_parents_0, 735 .num_parents = ARRAY_SIZE(gcc_parents_0), 736 .flags = CLK_SET_RATE_PARENT, 737 .ops = &clk_rcg2_ops, 738 }, 739}; 740 741static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { 742 .cmd_rcgr = 0x1e738, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_parent_map_0, 746 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 747 .clkr.hw.init = &(struct clk_init_data){ 748 .name = "gcc_qupv3_wrap2_s5_clk_src", 749 .parent_data = gcc_parents_0, 750 .num_parents = ARRAY_SIZE(gcc_parents_0), 751 .flags = CLK_SET_RATE_PARENT, 752 .ops = &clk_rcg2_ops, 753 }, 754}; 755 756static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 757 F(400000, P_BI_TCXO, 12, 1, 4), 758 F(9600000, P_BI_TCXO, 2, 0, 0), 759 F(19200000, P_BI_TCXO, 1, 0, 0), 760 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 761 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 762 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 763 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), 764 { } 765}; 766 767static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 768 .cmd_rcgr = 0x1400c, 769 .mnd_width = 8, 770 .hid_width = 5, 771 .parent_map = gcc_parent_map_6, 772 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 773 .clkr.hw.init = &(struct clk_init_data){ 774 .name = "gcc_sdcc2_apps_clk_src", 775 .parent_data = gcc_parents_6, 776 .num_parents = ARRAY_SIZE(gcc_parents_6), 777 .flags = CLK_OPS_PARENT_ENABLE, 778 .ops = &clk_rcg2_floor_ops, 779 }, 780}; 781 782static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 783 F(400000, P_BI_TCXO, 12, 1, 4), 784 F(9600000, P_BI_TCXO, 2, 0, 0), 785 F(19200000, P_BI_TCXO, 1, 0, 0), 786 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 787 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 788 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 789 { } 790}; 791 792static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 793 .cmd_rcgr = 0x1600c, 794 .mnd_width = 8, 795 .hid_width = 5, 796 .parent_map = gcc_parent_map_3, 797 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 798 .clkr.hw.init = &(struct clk_init_data){ 799 .name = "gcc_sdcc4_apps_clk_src", 800 .parent_data = gcc_parents_3, 801 .num_parents = ARRAY_SIZE(gcc_parents_3), 802 .flags = CLK_SET_RATE_PARENT, 803 .ops = &clk_rcg2_floor_ops, 804 }, 805}; 806 807static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { 808 F(105495, P_BI_TCXO, 2, 1, 91), 809 { } 810}; 811 812static struct clk_rcg2 gcc_tsif_ref_clk_src = { 813 .cmd_rcgr = 0x36010, 814 .mnd_width = 8, 815 .hid_width = 5, 816 .parent_map = gcc_parent_map_7, 817 .freq_tbl = ftbl_gcc_tsif_ref_clk_src, 818 .clkr.hw.init = &(struct clk_init_data){ 819 .name = "gcc_tsif_ref_clk_src", 820 .parent_data = gcc_parents_7, 821 .num_parents = ARRAY_SIZE(gcc_parents_7), 822 .flags = CLK_SET_RATE_PARENT, 823 .ops = &clk_rcg2_ops, 824 }, 825}; 826 827static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { 828 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 829 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 830 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 831 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 832 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 833 { } 834}; 835 836static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { 837 .cmd_rcgr = 0x75020, 838 .mnd_width = 8, 839 .hid_width = 5, 840 .parent_map = gcc_parent_map_0, 841 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, 842 .clkr.hw.init = &(struct clk_init_data){ 843 .name = "gcc_ufs_card_axi_clk_src", 844 .parent_data = gcc_parents_0, 845 .num_parents = ARRAY_SIZE(gcc_parents_0), 846 .flags = CLK_SET_RATE_PARENT, 847 .ops = &clk_rcg2_ops, 848 }, 849}; 850 851static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { 852 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 853 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 854 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 855 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 856 { } 857}; 858 859static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { 860 .cmd_rcgr = 0x75060, 861 .mnd_width = 0, 862 .hid_width = 5, 863 .parent_map = gcc_parent_map_0, 864 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 865 .clkr.hw.init = &(struct clk_init_data){ 866 .name = "gcc_ufs_card_ice_core_clk_src", 867 .parent_data = gcc_parents_0, 868 .num_parents = ARRAY_SIZE(gcc_parents_0), 869 .flags = CLK_SET_RATE_PARENT, 870 .ops = &clk_rcg2_ops, 871 }, 872}; 873 874static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { 875 F(19200000, P_BI_TCXO, 1, 0, 0), 876 { } 877}; 878 879static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { 880 .cmd_rcgr = 0x75094, 881 .mnd_width = 0, 882 .hid_width = 5, 883 .parent_map = gcc_parent_map_4, 884 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 885 .clkr.hw.init = &(struct clk_init_data){ 886 .name = "gcc_ufs_card_phy_aux_clk_src", 887 .parent_data = gcc_parents_4, 888 .num_parents = ARRAY_SIZE(gcc_parents_4), 889 .flags = CLK_SET_RATE_PARENT, 890 .ops = &clk_rcg2_ops, 891 }, 892}; 893 894static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { 895 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 896 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 897 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 898 { } 899}; 900 901static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { 902 .cmd_rcgr = 0x75078, 903 .mnd_width = 0, 904 .hid_width = 5, 905 .parent_map = gcc_parent_map_0, 906 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, 907 .clkr.hw.init = &(struct clk_init_data){ 908 .name = "gcc_ufs_card_unipro_core_clk_src", 909 .parent_data = gcc_parents_0, 910 .num_parents = ARRAY_SIZE(gcc_parents_0), 911 .flags = CLK_SET_RATE_PARENT, 912 .ops = &clk_rcg2_ops, 913 }, 914}; 915 916static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 917 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 918 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), 919 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 920 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 921 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 922 { } 923}; 924 925static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 926 .cmd_rcgr = 0x77020, 927 .mnd_width = 8, 928 .hid_width = 5, 929 .parent_map = gcc_parent_map_0, 930 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 931 .clkr.hw.init = &(struct clk_init_data){ 932 .name = "gcc_ufs_phy_axi_clk_src", 933 .parent_data = gcc_parents_0, 934 .num_parents = ARRAY_SIZE(gcc_parents_0), 935 .flags = CLK_SET_RATE_PARENT, 936 .ops = &clk_rcg2_ops, 937 }, 938}; 939 940static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 941 .cmd_rcgr = 0x77060, 942 .mnd_width = 0, 943 .hid_width = 5, 944 .parent_map = gcc_parent_map_0, 945 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 946 .clkr.hw.init = &(struct clk_init_data){ 947 .name = "gcc_ufs_phy_ice_core_clk_src", 948 .parent_data = gcc_parents_0, 949 .num_parents = ARRAY_SIZE(gcc_parents_0), 950 .flags = CLK_SET_RATE_PARENT, 951 .ops = &clk_rcg2_ops, 952 }, 953}; 954 955static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 956 .cmd_rcgr = 0x77094, 957 .mnd_width = 0, 958 .hid_width = 5, 959 .parent_map = gcc_parent_map_4, 960 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 961 .clkr.hw.init = &(struct clk_init_data){ 962 .name = "gcc_ufs_phy_phy_aux_clk_src", 963 .parent_data = gcc_parents_4, 964 .num_parents = ARRAY_SIZE(gcc_parents_4), 965 .flags = CLK_SET_RATE_PARENT, 966 .ops = &clk_rcg2_ops, 967 }, 968}; 969 970static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 971 .cmd_rcgr = 0x77078, 972 .mnd_width = 0, 973 .hid_width = 5, 974 .parent_map = gcc_parent_map_0, 975 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, 976 .clkr.hw.init = &(struct clk_init_data){ 977 .name = "gcc_ufs_phy_unipro_core_clk_src", 978 .parent_data = gcc_parents_0, 979 .num_parents = ARRAY_SIZE(gcc_parents_0), 980 .flags = CLK_SET_RATE_PARENT, 981 .ops = &clk_rcg2_ops, 982 }, 983}; 984 985static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 986 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 987 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), 988 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), 989 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 990 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 991 { } 992}; 993 994static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 995 .cmd_rcgr = 0xf01c, 996 .mnd_width = 8, 997 .hid_width = 5, 998 .parent_map = gcc_parent_map_0, 999 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1000 .clkr.hw.init = &(struct clk_init_data){ 1001 .name = "gcc_usb30_prim_master_clk_src", 1002 .parent_data = gcc_parents_0, 1003 .num_parents = ARRAY_SIZE(gcc_parents_0), 1004 .flags = CLK_SET_RATE_PARENT, 1005 .ops = &clk_rcg2_ops, 1006 }, 1007}; 1008 1009static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { 1010 F(19200000, P_BI_TCXO, 1, 0, 0), 1011 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), 1012 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), 1013 { } 1014}; 1015 1016static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1017 .cmd_rcgr = 0xf034, 1018 .mnd_width = 0, 1019 .hid_width = 5, 1020 .parent_map = gcc_parent_map_0, 1021 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1022 .clkr.hw.init = &(struct clk_init_data){ 1023 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1024 .parent_data = gcc_parents_0, 1025 .num_parents = ARRAY_SIZE(gcc_parents_0), 1026 .flags = CLK_SET_RATE_PARENT, 1027 .ops = &clk_rcg2_ops, 1028 }, 1029}; 1030 1031static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { 1032 .cmd_rcgr = 0x1001c, 1033 .mnd_width = 8, 1034 .hid_width = 5, 1035 .parent_map = gcc_parent_map_0, 1036 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1037 .clkr.hw.init = &(struct clk_init_data){ 1038 .name = "gcc_usb30_sec_master_clk_src", 1039 .parent_data = gcc_parents_0, 1040 .num_parents = ARRAY_SIZE(gcc_parents_0), 1041 .flags = CLK_SET_RATE_PARENT, 1042 .ops = &clk_rcg2_ops, 1043 }, 1044}; 1045 1046static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { 1047 .cmd_rcgr = 0x10034, 1048 .mnd_width = 0, 1049 .hid_width = 5, 1050 .parent_map = gcc_parent_map_0, 1051 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, 1052 .clkr.hw.init = &(struct clk_init_data){ 1053 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1054 .parent_data = gcc_parents_0, 1055 .num_parents = ARRAY_SIZE(gcc_parents_0), 1056 .flags = CLK_SET_RATE_PARENT, 1057 .ops = &clk_rcg2_ops, 1058 }, 1059}; 1060 1061static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1062 .cmd_rcgr = 0xf060, 1063 .mnd_width = 0, 1064 .hid_width = 5, 1065 .parent_map = gcc_parent_map_2, 1066 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1067 .clkr.hw.init = &(struct clk_init_data){ 1068 .name = "gcc_usb3_prim_phy_aux_clk_src", 1069 .parent_data = gcc_parents_2, 1070 .num_parents = ARRAY_SIZE(gcc_parents_2), 1071 .flags = CLK_SET_RATE_PARENT, 1072 .ops = &clk_rcg2_ops, 1073 }, 1074}; 1075 1076static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { 1077 .cmd_rcgr = 0x10060, 1078 .mnd_width = 0, 1079 .hid_width = 5, 1080 .parent_map = gcc_parent_map_2, 1081 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, 1082 .clkr.hw.init = &(struct clk_init_data){ 1083 .name = "gcc_usb3_sec_phy_aux_clk_src", 1084 .parent_data = gcc_parents_2, 1085 .num_parents = ARRAY_SIZE(gcc_parents_2), 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_rcg2_ops, 1088 }, 1089}; 1090 1091static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 1092 .halt_reg = 0x90018, 1093 .halt_check = BRANCH_HALT, 1094 .clkr = { 1095 .enable_reg = 0x90018, 1096 .enable_mask = BIT(0), 1097 .hw.init = &(struct clk_init_data){ 1098 .name = "gcc_aggre_noc_pcie_tbu_clk", 1099 .ops = &clk_branch2_ops, 1100 }, 1101 }, 1102}; 1103 1104static struct clk_branch gcc_aggre_ufs_card_axi_clk = { 1105 .halt_reg = 0x750c0, 1106 .halt_check = BRANCH_HALT, 1107 .hwcg_reg = 0x750c0, 1108 .hwcg_bit = 1, 1109 .clkr = { 1110 .enable_reg = 0x750c0, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(struct clk_init_data){ 1113 .name = "gcc_aggre_ufs_card_axi_clk", 1114 .parent_hws = (const struct clk_hw *[]){ 1115 &gcc_ufs_card_axi_clk_src.clkr.hw }, 1116 .num_parents = 1, 1117 .flags = CLK_SET_RATE_PARENT, 1118 .ops = &clk_branch2_ops, 1119 }, 1120 }, 1121}; 1122 1123static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { 1124 .halt_reg = 0x750c0, 1125 .halt_check = BRANCH_HALT, 1126 .hwcg_reg = 0x750c0, 1127 .hwcg_bit = 1, 1128 .clkr = { 1129 .enable_reg = 0x750c0, 1130 .enable_mask = BIT(1), 1131 .hw.init = &(struct clk_init_data){ 1132 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", 1133 .parent_hws = (const struct clk_hw *[]){ 1134 &gcc_aggre_ufs_card_axi_clk.clkr.hw }, 1135 .num_parents = 1, 1136 .flags = CLK_SET_RATE_PARENT, 1137 .ops = &clk_branch_simple_ops, 1138 }, 1139 }, 1140}; 1141 1142static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1143 .halt_reg = 0x770c0, 1144 .halt_check = BRANCH_HALT, 1145 .hwcg_reg = 0x770c0, 1146 .hwcg_bit = 1, 1147 .clkr = { 1148 .enable_reg = 0x770c0, 1149 .enable_mask = BIT(0), 1150 .hw.init = &(struct clk_init_data){ 1151 .name = "gcc_aggre_ufs_phy_axi_clk", 1152 .parent_hws = (const struct clk_hw *[]){ 1153 &gcc_ufs_phy_axi_clk_src.clkr.hw }, 1154 .num_parents = 1, 1155 .flags = CLK_SET_RATE_PARENT, 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159}; 1160 1161static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { 1162 .halt_reg = 0x770c0, 1163 .halt_check = BRANCH_HALT, 1164 .hwcg_reg = 0x770c0, 1165 .hwcg_bit = 1, 1166 .clkr = { 1167 .enable_reg = 0x770c0, 1168 .enable_mask = BIT(1), 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", 1171 .parent_hws = (const struct clk_hw *[]){ 1172 &gcc_aggre_ufs_phy_axi_clk.clkr.hw }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch_simple_ops, 1176 }, 1177 }, 1178}; 1179 1180static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1181 .halt_reg = 0xf07c, 1182 .halt_check = BRANCH_HALT, 1183 .clkr = { 1184 .enable_reg = 0xf07c, 1185 .enable_mask = BIT(0), 1186 .hw.init = &(struct clk_init_data){ 1187 .name = "gcc_aggre_usb3_prim_axi_clk", 1188 .parent_hws = (const struct clk_hw *[]){ 1189 &gcc_usb30_prim_master_clk_src.clkr.hw }, 1190 .num_parents = 1, 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_branch2_ops, 1193 }, 1194 }, 1195}; 1196 1197static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { 1198 .halt_reg = 0x1007c, 1199 .halt_check = BRANCH_HALT, 1200 .clkr = { 1201 .enable_reg = 0x1007c, 1202 .enable_mask = BIT(0), 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "gcc_aggre_usb3_sec_axi_clk", 1205 .parent_hws = (const struct clk_hw *[]){ 1206 &gcc_usb30_sec_master_clk_src.clkr.hw }, 1207 .num_parents = 1, 1208 .flags = CLK_SET_RATE_PARENT, 1209 .ops = &clk_branch2_ops, 1210 }, 1211 }, 1212}; 1213 1214static struct clk_branch gcc_boot_rom_ahb_clk = { 1215 .halt_reg = 0x38004, 1216 .halt_check = BRANCH_HALT_VOTED, 1217 .hwcg_reg = 0x38004, 1218 .hwcg_bit = 1, 1219 .clkr = { 1220 .enable_reg = 0x52004, 1221 .enable_mask = BIT(10), 1222 .hw.init = &(struct clk_init_data){ 1223 .name = "gcc_boot_rom_ahb_clk", 1224 .ops = &clk_branch2_ops, 1225 }, 1226 }, 1227}; 1228 1229/* 1230 * Clock ON depends on external parent 'config noc', so cant poll 1231 * delay and also mark as crtitical for camss boot 1232 */ 1233static struct clk_branch gcc_camera_ahb_clk = { 1234 .halt_reg = 0xb008, 1235 .halt_check = BRANCH_HALT_DELAY, 1236 .hwcg_reg = 0xb008, 1237 .hwcg_bit = 1, 1238 .clkr = { 1239 .enable_reg = 0xb008, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(struct clk_init_data){ 1242 .name = "gcc_camera_ahb_clk", 1243 .flags = CLK_IS_CRITICAL, 1244 .ops = &clk_branch2_ops, 1245 }, 1246 }, 1247}; 1248 1249static struct clk_branch gcc_camera_hf_axi_clk = { 1250 .halt_reg = 0xb030, 1251 .halt_check = BRANCH_HALT, 1252 .clkr = { 1253 .enable_reg = 0xb030, 1254 .enable_mask = BIT(0), 1255 .hw.init = &(struct clk_init_data){ 1256 .name = "gcc_camera_hf_axi_clk", 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260}; 1261 1262static struct clk_branch gcc_camera_sf_axi_clk = { 1263 .halt_reg = 0xb034, 1264 .halt_check = BRANCH_HALT, 1265 .clkr = { 1266 .enable_reg = 0xb034, 1267 .enable_mask = BIT(0), 1268 .hw.init = &(struct clk_init_data){ 1269 .name = "gcc_camera_sf_axi_clk", 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273}; 1274 1275/* XO critical input to camss, so no need to poll */ 1276static struct clk_branch gcc_camera_xo_clk = { 1277 .halt_reg = 0xb044, 1278 .halt_check = BRANCH_HALT_DELAY, 1279 .clkr = { 1280 .enable_reg = 0xb044, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "gcc_camera_xo_clk", 1284 .flags = CLK_IS_CRITICAL, 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288}; 1289 1290static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1291 .halt_reg = 0xf078, 1292 .halt_check = BRANCH_HALT, 1293 .clkr = { 1294 .enable_reg = 0xf078, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1298 .parent_hws = (const struct clk_hw *[]){ 1299 &gcc_usb30_prim_master_clk_src.clkr.hw }, 1300 .num_parents = 1, 1301 .flags = CLK_SET_RATE_PARENT, 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305}; 1306 1307static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { 1308 .halt_reg = 0x10078, 1309 .halt_check = BRANCH_HALT, 1310 .clkr = { 1311 .enable_reg = 0x10078, 1312 .enable_mask = BIT(0), 1313 .hw.init = &(struct clk_init_data){ 1314 .name = "gcc_cfg_noc_usb3_sec_axi_clk", 1315 .parent_hws = (const struct clk_hw *[]){ 1316 &gcc_usb30_sec_master_clk_src.clkr.hw }, 1317 .num_parents = 1, 1318 .flags = CLK_SET_RATE_PARENT, 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322}; 1323 1324static struct clk_branch gcc_cpuss_ahb_clk = { 1325 .halt_reg = 0x48000, 1326 .halt_check = BRANCH_HALT_VOTED, 1327 .clkr = { 1328 .enable_reg = 0x52004, 1329 .enable_mask = BIT(21), 1330 .hw.init = &(struct clk_init_data){ 1331 .name = "gcc_cpuss_ahb_clk", 1332 .parent_hws = (const struct clk_hw *[]){ 1333 &gcc_cpuss_ahb_clk_src.clkr.hw }, 1334 .num_parents = 1, 1335 /* required for cpuss */ 1336 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340}; 1341 1342static struct clk_branch gcc_cpuss_dvm_bus_clk = { 1343 .halt_reg = 0x48190, 1344 .halt_check = BRANCH_HALT, 1345 .clkr = { 1346 .enable_reg = 0x48190, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(struct clk_init_data){ 1349 .name = "gcc_cpuss_dvm_bus_clk", 1350 /* required for cpuss */ 1351 .flags = CLK_IS_CRITICAL, 1352 .ops = &clk_branch2_ops, 1353 }, 1354 }, 1355}; 1356 1357static struct clk_branch gcc_cpuss_gnoc_clk = { 1358 .halt_reg = 0x48004, 1359 .halt_check = BRANCH_HALT_VOTED, 1360 .hwcg_reg = 0x48004, 1361 .hwcg_bit = 1, 1362 .clkr = { 1363 .enable_reg = 0x52004, 1364 .enable_mask = BIT(22), 1365 .hw.init = &(struct clk_init_data){ 1366 .name = "gcc_cpuss_gnoc_clk", 1367 /* required for cpuss */ 1368 .flags = CLK_IS_CRITICAL, 1369 .ops = &clk_branch2_ops, 1370 }, 1371 }, 1372}; 1373 1374static struct clk_branch gcc_cpuss_rbcpr_clk = { 1375 .halt_reg = 0x48008, 1376 .halt_check = BRANCH_HALT, 1377 .clkr = { 1378 .enable_reg = 0x48008, 1379 .enable_mask = BIT(0), 1380 .hw.init = &(struct clk_init_data){ 1381 .name = "gcc_cpuss_rbcpr_clk", 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385}; 1386 1387static struct clk_branch gcc_ddrss_gpu_axi_clk = { 1388 .halt_reg = 0x71154, 1389 .halt_check = BRANCH_VOTED, 1390 .clkr = { 1391 .enable_reg = 0x71154, 1392 .enable_mask = BIT(0), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "gcc_ddrss_gpu_axi_clk", 1395 .ops = &clk_branch2_ops, 1396 }, 1397 }, 1398}; 1399 1400/* 1401 * Clock ON depends on external parent 'config noc', so cant poll 1402 * delay and also mark as crtitical for disp boot 1403 */ 1404static struct clk_branch gcc_disp_ahb_clk = { 1405 .halt_reg = 0xb00c, 1406 .halt_check = BRANCH_HALT_DELAY, 1407 .hwcg_reg = 0xb00c, 1408 .hwcg_bit = 1, 1409 .clkr = { 1410 .enable_reg = 0xb00c, 1411 .enable_mask = BIT(0), 1412 .hw.init = &(struct clk_init_data){ 1413 .name = "gcc_disp_ahb_clk", 1414 .flags = CLK_IS_CRITICAL, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418}; 1419 1420static struct clk_branch gcc_disp_hf_axi_clk = { 1421 .halt_reg = 0xb038, 1422 .halt_check = BRANCH_HALT, 1423 .clkr = { 1424 .enable_reg = 0xb038, 1425 .enable_mask = BIT(0), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "gcc_disp_hf_axi_clk", 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431}; 1432 1433static struct clk_branch gcc_disp_sf_axi_clk = { 1434 .halt_reg = 0xb03c, 1435 .halt_check = BRANCH_HALT, 1436 .clkr = { 1437 .enable_reg = 0xb03c, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "gcc_disp_sf_axi_clk", 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444}; 1445 1446/* XO critical input to disp, so no need to poll */ 1447static struct clk_branch gcc_disp_xo_clk = { 1448 .halt_reg = 0xb048, 1449 .halt_check = BRANCH_HALT_DELAY, 1450 .clkr = { 1451 .enable_reg = 0xb048, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_disp_xo_clk", 1455 .flags = CLK_IS_CRITICAL, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459}; 1460 1461static struct clk_branch gcc_emac_axi_clk = { 1462 .halt_reg = 0x6010, 1463 .halt_check = BRANCH_HALT, 1464 .clkr = { 1465 .enable_reg = 0x6010, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(struct clk_init_data){ 1468 .name = "gcc_emac_axi_clk", 1469 .ops = &clk_branch2_ops, 1470 }, 1471 }, 1472}; 1473 1474static struct clk_branch gcc_emac_ptp_clk = { 1475 .halt_reg = 0x6034, 1476 .halt_check = BRANCH_HALT, 1477 .clkr = { 1478 .enable_reg = 0x6034, 1479 .enable_mask = BIT(0), 1480 .hw.init = &(struct clk_init_data){ 1481 .name = "gcc_emac_ptp_clk", 1482 .parent_hws = (const struct clk_hw *[]){ 1483 &gcc_emac_ptp_clk_src.clkr.hw }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489}; 1490 1491static struct clk_branch gcc_emac_rgmii_clk = { 1492 .halt_reg = 0x6018, 1493 .halt_check = BRANCH_HALT, 1494 .clkr = { 1495 .enable_reg = 0x6018, 1496 .enable_mask = BIT(0), 1497 .hw.init = &(struct clk_init_data){ 1498 .name = "gcc_emac_rgmii_clk", 1499 .parent_hws = (const struct clk_hw *[]){ 1500 &gcc_emac_rgmii_clk_src.clkr.hw }, 1501 .num_parents = 1, 1502 .flags = CLK_SET_RATE_PARENT, 1503 .ops = &clk_branch2_ops, 1504 }, 1505 }, 1506}; 1507 1508static struct clk_branch gcc_emac_slv_ahb_clk = { 1509 .halt_reg = 0x6014, 1510 .halt_check = BRANCH_HALT, 1511 .hwcg_reg = 0x6014, 1512 .hwcg_bit = 1, 1513 .clkr = { 1514 .enable_reg = 0x6014, 1515 .enable_mask = BIT(0), 1516 .hw.init = &(struct clk_init_data){ 1517 .name = "gcc_emac_slv_ahb_clk", 1518 .ops = &clk_branch2_ops, 1519 }, 1520 }, 1521}; 1522 1523static struct clk_branch gcc_gp1_clk = { 1524 .halt_reg = 0x64000, 1525 .halt_check = BRANCH_HALT, 1526 .clkr = { 1527 .enable_reg = 0x64000, 1528 .enable_mask = BIT(0), 1529 .hw.init = &(struct clk_init_data){ 1530 .name = "gcc_gp1_clk", 1531 .parent_hws = (const struct clk_hw *[]){ 1532 &gcc_gp1_clk_src.clkr.hw }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538}; 1539 1540static struct clk_branch gcc_gp2_clk = { 1541 .halt_reg = 0x65000, 1542 .halt_check = BRANCH_HALT, 1543 .clkr = { 1544 .enable_reg = 0x65000, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(struct clk_init_data){ 1547 .name = "gcc_gp2_clk", 1548 .parent_hws = (const struct clk_hw *[]){ 1549 &gcc_gp2_clk_src.clkr.hw }, 1550 .num_parents = 1, 1551 .flags = CLK_SET_RATE_PARENT, 1552 .ops = &clk_branch2_ops, 1553 }, 1554 }, 1555}; 1556 1557static struct clk_branch gcc_gp3_clk = { 1558 .halt_reg = 0x66000, 1559 .halt_check = BRANCH_HALT, 1560 .clkr = { 1561 .enable_reg = 0x66000, 1562 .enable_mask = BIT(0), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "gcc_gp3_clk", 1565 .parent_hws = (const struct clk_hw *[]){ 1566 &gcc_gp3_clk_src.clkr.hw }, 1567 .num_parents = 1, 1568 .flags = CLK_SET_RATE_PARENT, 1569 .ops = &clk_branch2_ops, 1570 }, 1571 }, 1572}; 1573 1574static struct clk_branch gcc_gpu_cfg_ahb_clk = { 1575 .halt_reg = 0x71004, 1576 .halt_check = BRANCH_HALT, 1577 .hwcg_reg = 0x71004, 1578 .hwcg_bit = 1, 1579 .clkr = { 1580 .enable_reg = 0x71004, 1581 .enable_mask = BIT(0), 1582 .hw.init = &(struct clk_init_data){ 1583 .name = "gcc_gpu_cfg_ahb_clk", 1584 /* required for gpu */ 1585 .flags = CLK_IS_CRITICAL, 1586 .ops = &clk_branch2_ops, 1587 }, 1588 }, 1589}; 1590 1591static struct clk_branch gcc_gpu_gpll0_clk_src = { 1592 .halt_check = BRANCH_HALT_SKIP, 1593 .clkr = { 1594 .enable_reg = 0x52004, 1595 .enable_mask = BIT(15), 1596 .hw.init = &(struct clk_init_data){ 1597 .name = "gcc_gpu_gpll0_clk_src", 1598 .parent_hws = (const struct clk_hw *[]){ 1599 &gpll0.clkr.hw }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605}; 1606 1607static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1608 .halt_check = BRANCH_HALT_SKIP, 1609 .clkr = { 1610 .enable_reg = 0x52004, 1611 .enable_mask = BIT(16), 1612 .hw.init = &(struct clk_init_data){ 1613 .name = "gcc_gpu_gpll0_div_clk_src", 1614 .parent_hws = (const struct clk_hw *[]){ 1615 &gpll0_out_even.clkr.hw }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621}; 1622 1623static struct clk_branch gcc_gpu_iref_clk = { 1624 .halt_reg = 0x8c010, 1625 .halt_check = BRANCH_HALT, 1626 .clkr = { 1627 .enable_reg = 0x8c010, 1628 .enable_mask = BIT(0), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "gcc_gpu_iref_clk", 1631 .ops = &clk_branch2_ops, 1632 }, 1633 }, 1634}; 1635 1636static struct clk_branch gcc_gpu_memnoc_gfx_clk = { 1637 .halt_reg = 0x7100c, 1638 .halt_check = BRANCH_VOTED, 1639 .clkr = { 1640 .enable_reg = 0x7100c, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(struct clk_init_data){ 1643 .name = "gcc_gpu_memnoc_gfx_clk", 1644 .ops = &clk_branch2_ops, 1645 }, 1646 }, 1647}; 1648 1649static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 1650 .halt_reg = 0x71018, 1651 .halt_check = BRANCH_HALT, 1652 .clkr = { 1653 .enable_reg = 0x71018, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "gcc_gpu_snoc_dvm_gfx_clk", 1657 .ops = &clk_branch2_ops, 1658 }, 1659 }, 1660}; 1661 1662static struct clk_branch gcc_npu_at_clk = { 1663 .halt_reg = 0x4d010, 1664 .halt_check = BRANCH_VOTED, 1665 .clkr = { 1666 .enable_reg = 0x4d010, 1667 .enable_mask = BIT(0), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "gcc_npu_at_clk", 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673}; 1674 1675static struct clk_branch gcc_npu_axi_clk = { 1676 .halt_reg = 0x4d008, 1677 .halt_check = BRANCH_VOTED, 1678 .clkr = { 1679 .enable_reg = 0x4d008, 1680 .enable_mask = BIT(0), 1681 .hw.init = &(struct clk_init_data){ 1682 .name = "gcc_npu_axi_clk", 1683 .ops = &clk_branch2_ops, 1684 }, 1685 }, 1686}; 1687 1688static struct clk_branch gcc_npu_cfg_ahb_clk = { 1689 .halt_reg = 0x4d004, 1690 .halt_check = BRANCH_HALT, 1691 .hwcg_reg = 0x4d004, 1692 .hwcg_bit = 1, 1693 .clkr = { 1694 .enable_reg = 0x4d004, 1695 .enable_mask = BIT(0), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "gcc_npu_cfg_ahb_clk", 1698 /* required for npu */ 1699 .flags = CLK_IS_CRITICAL, 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703}; 1704 1705static struct clk_branch gcc_npu_gpll0_clk_src = { 1706 .halt_check = BRANCH_HALT_SKIP, 1707 .clkr = { 1708 .enable_reg = 0x52004, 1709 .enable_mask = BIT(18), 1710 .hw.init = &(struct clk_init_data){ 1711 .name = "gcc_npu_gpll0_clk_src", 1712 .parent_hws = (const struct clk_hw *[]){ 1713 &gpll0.clkr.hw }, 1714 .num_parents = 1, 1715 .flags = CLK_SET_RATE_PARENT, 1716 .ops = &clk_branch2_ops, 1717 }, 1718 }, 1719}; 1720 1721static struct clk_branch gcc_npu_gpll0_div_clk_src = { 1722 .halt_check = BRANCH_HALT_SKIP, 1723 .clkr = { 1724 .enable_reg = 0x52004, 1725 .enable_mask = BIT(19), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "gcc_npu_gpll0_div_clk_src", 1728 .parent_hws = (const struct clk_hw *[]){ 1729 &gpll0_out_even.clkr.hw }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735}; 1736 1737static struct clk_branch gcc_npu_trig_clk = { 1738 .halt_reg = 0x4d00c, 1739 .halt_check = BRANCH_VOTED, 1740 .clkr = { 1741 .enable_reg = 0x4d00c, 1742 .enable_mask = BIT(0), 1743 .hw.init = &(struct clk_init_data){ 1744 .name = "gcc_npu_trig_clk", 1745 .ops = &clk_branch2_ops, 1746 }, 1747 }, 1748}; 1749 1750static struct clk_branch gcc_pcie0_phy_refgen_clk = { 1751 .halt_reg = 0x6f02c, 1752 .halt_check = BRANCH_HALT, 1753 .clkr = { 1754 .enable_reg = 0x6f02c, 1755 .enable_mask = BIT(0), 1756 .hw.init = &(struct clk_init_data){ 1757 .name = "gcc_pcie0_phy_refgen_clk", 1758 .parent_hws = (const struct clk_hw *[]){ 1759 &gcc_pcie_phy_refgen_clk_src.clkr.hw }, 1760 .num_parents = 1, 1761 .flags = CLK_SET_RATE_PARENT, 1762 .ops = &clk_branch2_ops, 1763 }, 1764 }, 1765}; 1766 1767static struct clk_branch gcc_pcie1_phy_refgen_clk = { 1768 .halt_reg = 0x6f030, 1769 .halt_check = BRANCH_HALT, 1770 .clkr = { 1771 .enable_reg = 0x6f030, 1772 .enable_mask = BIT(0), 1773 .hw.init = &(struct clk_init_data){ 1774 .name = "gcc_pcie1_phy_refgen_clk", 1775 .parent_hws = (const struct clk_hw *[]){ 1776 &gcc_pcie_phy_refgen_clk_src.clkr.hw }, 1777 .num_parents = 1, 1778 .flags = CLK_SET_RATE_PARENT, 1779 .ops = &clk_branch2_ops, 1780 }, 1781 }, 1782}; 1783 1784static struct clk_branch gcc_pcie_0_aux_clk = { 1785 .halt_reg = 0x6b020, 1786 .halt_check = BRANCH_HALT_VOTED, 1787 .clkr = { 1788 .enable_reg = 0x5200c, 1789 .enable_mask = BIT(3), 1790 .hw.init = &(struct clk_init_data){ 1791 .name = "gcc_pcie_0_aux_clk", 1792 .parent_hws = (const struct clk_hw *[]){ 1793 &gcc_pcie_0_aux_clk_src.clkr.hw }, 1794 .num_parents = 1, 1795 .flags = CLK_SET_RATE_PARENT, 1796 .ops = &clk_branch2_ops, 1797 }, 1798 }, 1799}; 1800 1801static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1802 .halt_reg = 0x6b01c, 1803 .halt_check = BRANCH_HALT_VOTED, 1804 .hwcg_reg = 0x6b01c, 1805 .hwcg_bit = 1, 1806 .clkr = { 1807 .enable_reg = 0x5200c, 1808 .enable_mask = BIT(2), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "gcc_pcie_0_cfg_ahb_clk", 1811 .ops = &clk_branch2_ops, 1812 }, 1813 }, 1814}; 1815 1816static struct clk_branch gcc_pcie_0_clkref_clk = { 1817 .halt_reg = 0x8c00c, 1818 .halt_check = BRANCH_HALT, 1819 .clkr = { 1820 .enable_reg = 0x8c00c, 1821 .enable_mask = BIT(0), 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "gcc_pcie_0_clkref_clk", 1824 .ops = &clk_branch2_ops, 1825 }, 1826 }, 1827}; 1828 1829static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1830 .halt_reg = 0x6b018, 1831 .halt_check = BRANCH_HALT_VOTED, 1832 .clkr = { 1833 .enable_reg = 0x5200c, 1834 .enable_mask = BIT(1), 1835 .hw.init = &(struct clk_init_data){ 1836 .name = "gcc_pcie_0_mstr_axi_clk", 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840}; 1841 1842/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ 1843static struct clk_branch gcc_pcie_0_pipe_clk = { 1844 .halt_reg = 0x6b024, 1845 .halt_check = BRANCH_HALT_DELAY, 1846 .clkr = { 1847 .enable_reg = 0x5200c, 1848 .enable_mask = BIT(4), 1849 .hw.init = &(struct clk_init_data){ 1850 .name = "gcc_pcie_0_pipe_clk", 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854}; 1855 1856static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1857 .halt_reg = 0x6b014, 1858 .halt_check = BRANCH_HALT_VOTED, 1859 .hwcg_reg = 0x6b014, 1860 .hwcg_bit = 1, 1861 .clkr = { 1862 .enable_reg = 0x5200c, 1863 .enable_mask = BIT(0), 1864 .hw.init = &(struct clk_init_data){ 1865 .name = "gcc_pcie_0_slv_axi_clk", 1866 .ops = &clk_branch2_ops, 1867 }, 1868 }, 1869}; 1870 1871static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1872 .halt_reg = 0x6b010, 1873 .halt_check = BRANCH_HALT_VOTED, 1874 .clkr = { 1875 .enable_reg = 0x5200c, 1876 .enable_mask = BIT(5), 1877 .hw.init = &(struct clk_init_data){ 1878 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1879 .ops = &clk_branch2_ops, 1880 }, 1881 }, 1882}; 1883 1884static struct clk_branch gcc_pcie_1_aux_clk = { 1885 .halt_reg = 0x8d020, 1886 .halt_check = BRANCH_HALT_VOTED, 1887 .clkr = { 1888 .enable_reg = 0x52004, 1889 .enable_mask = BIT(29), 1890 .hw.init = &(struct clk_init_data){ 1891 .name = "gcc_pcie_1_aux_clk", 1892 .parent_hws = (const struct clk_hw *[]){ 1893 &gcc_pcie_1_aux_clk_src.clkr.hw }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899}; 1900 1901static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1902 .halt_reg = 0x8d01c, 1903 .halt_check = BRANCH_HALT_VOTED, 1904 .hwcg_reg = 0x8d01c, 1905 .hwcg_bit = 1, 1906 .clkr = { 1907 .enable_reg = 0x52004, 1908 .enable_mask = BIT(28), 1909 .hw.init = &(struct clk_init_data){ 1910 .name = "gcc_pcie_1_cfg_ahb_clk", 1911 .ops = &clk_branch2_ops, 1912 }, 1913 }, 1914}; 1915 1916static struct clk_branch gcc_pcie_1_clkref_clk = { 1917 .halt_reg = 0x8c02c, 1918 .halt_check = BRANCH_HALT, 1919 .clkr = { 1920 .enable_reg = 0x8c02c, 1921 .enable_mask = BIT(0), 1922 .hw.init = &(struct clk_init_data){ 1923 .name = "gcc_pcie_1_clkref_clk", 1924 .ops = &clk_branch2_ops, 1925 }, 1926 }, 1927}; 1928 1929static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1930 .halt_reg = 0x8d018, 1931 .halt_check = BRANCH_HALT_VOTED, 1932 .clkr = { 1933 .enable_reg = 0x52004, 1934 .enable_mask = BIT(27), 1935 .hw.init = &(struct clk_init_data){ 1936 .name = "gcc_pcie_1_mstr_axi_clk", 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940}; 1941 1942/* Clock ON depends on external parent 'PIPE' clock, so dont poll */ 1943static struct clk_branch gcc_pcie_1_pipe_clk = { 1944 .halt_reg = 0x8d024, 1945 .halt_check = BRANCH_HALT_DELAY, 1946 .clkr = { 1947 .enable_reg = 0x52004, 1948 .enable_mask = BIT(30), 1949 .hw.init = &(struct clk_init_data){ 1950 .name = "gcc_pcie_1_pipe_clk", 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954}; 1955 1956static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1957 .halt_reg = 0x8d014, 1958 .halt_check = BRANCH_HALT_VOTED, 1959 .hwcg_reg = 0x8d014, 1960 .hwcg_bit = 1, 1961 .clkr = { 1962 .enable_reg = 0x52004, 1963 .enable_mask = BIT(26), 1964 .hw.init = &(struct clk_init_data){ 1965 .name = "gcc_pcie_1_slv_axi_clk", 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969}; 1970 1971static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1972 .halt_reg = 0x8d010, 1973 .halt_check = BRANCH_HALT_VOTED, 1974 .clkr = { 1975 .enable_reg = 0x52004, 1976 .enable_mask = BIT(25), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "gcc_pcie_1_slv_q2a_axi_clk", 1979 .ops = &clk_branch2_ops, 1980 }, 1981 }, 1982}; 1983 1984static struct clk_branch gcc_pcie_phy_aux_clk = { 1985 .halt_reg = 0x6f004, 1986 .halt_check = BRANCH_HALT, 1987 .clkr = { 1988 .enable_reg = 0x6f004, 1989 .enable_mask = BIT(0), 1990 .hw.init = &(struct clk_init_data){ 1991 .name = "gcc_pcie_phy_aux_clk", 1992 .parent_hws = (const struct clk_hw *[]){ 1993 &gcc_pcie_0_aux_clk_src.clkr.hw }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999}; 2000 2001static struct clk_branch gcc_pdm2_clk = { 2002 .halt_reg = 0x3300c, 2003 .halt_check = BRANCH_HALT, 2004 .clkr = { 2005 .enable_reg = 0x3300c, 2006 .enable_mask = BIT(0), 2007 .hw.init = &(struct clk_init_data){ 2008 .name = "gcc_pdm2_clk", 2009 .parent_hws = (const struct clk_hw *[]){ 2010 &gcc_pdm2_clk_src.clkr.hw }, 2011 .num_parents = 1, 2012 .flags = CLK_SET_RATE_PARENT, 2013 .ops = &clk_branch2_ops, 2014 }, 2015 }, 2016}; 2017 2018static struct clk_branch gcc_pdm_ahb_clk = { 2019 .halt_reg = 0x33004, 2020 .halt_check = BRANCH_HALT, 2021 .hwcg_reg = 0x33004, 2022 .hwcg_bit = 1, 2023 .clkr = { 2024 .enable_reg = 0x33004, 2025 .enable_mask = BIT(0), 2026 .hw.init = &(struct clk_init_data){ 2027 .name = "gcc_pdm_ahb_clk", 2028 .ops = &clk_branch2_ops, 2029 }, 2030 }, 2031}; 2032 2033static struct clk_branch gcc_pdm_xo4_clk = { 2034 .halt_reg = 0x33008, 2035 .halt_check = BRANCH_HALT, 2036 .clkr = { 2037 .enable_reg = 0x33008, 2038 .enable_mask = BIT(0), 2039 .hw.init = &(struct clk_init_data){ 2040 .name = "gcc_pdm_xo4_clk", 2041 .ops = &clk_branch2_ops, 2042 }, 2043 }, 2044}; 2045 2046static struct clk_branch gcc_prng_ahb_clk = { 2047 .halt_reg = 0x34004, 2048 .halt_check = BRANCH_HALT_VOTED, 2049 .clkr = { 2050 .enable_reg = 0x52004, 2051 .enable_mask = BIT(13), 2052 .hw.init = &(struct clk_init_data){ 2053 .name = "gcc_prng_ahb_clk", 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057}; 2058 2059static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 2060 .halt_reg = 0xb018, 2061 .halt_check = BRANCH_HALT, 2062 .hwcg_reg = 0xb018, 2063 .hwcg_bit = 1, 2064 .clkr = { 2065 .enable_reg = 0xb018, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "gcc_qmip_camera_nrt_ahb_clk", 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072}; 2073 2074static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 2075 .halt_reg = 0xb01c, 2076 .halt_check = BRANCH_HALT, 2077 .hwcg_reg = 0xb01c, 2078 .hwcg_bit = 1, 2079 .clkr = { 2080 .enable_reg = 0xb01c, 2081 .enable_mask = BIT(0), 2082 .hw.init = &(struct clk_init_data){ 2083 .name = "gcc_qmip_camera_rt_ahb_clk", 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087}; 2088 2089static struct clk_branch gcc_qmip_disp_ahb_clk = { 2090 .halt_reg = 0xb020, 2091 .halt_check = BRANCH_HALT, 2092 .hwcg_reg = 0xb020, 2093 .hwcg_bit = 1, 2094 .clkr = { 2095 .enable_reg = 0xb020, 2096 .enable_mask = BIT(0), 2097 .hw.init = &(struct clk_init_data){ 2098 .name = "gcc_qmip_disp_ahb_clk", 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102}; 2103 2104static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 2105 .halt_reg = 0xb010, 2106 .halt_check = BRANCH_HALT, 2107 .hwcg_reg = 0xb010, 2108 .hwcg_bit = 1, 2109 .clkr = { 2110 .enable_reg = 0xb010, 2111 .enable_mask = BIT(0), 2112 .hw.init = &(struct clk_init_data){ 2113 .name = "gcc_qmip_video_cvp_ahb_clk", 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117}; 2118 2119static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 2120 .halt_reg = 0xb014, 2121 .halt_check = BRANCH_HALT, 2122 .hwcg_reg = 0xb014, 2123 .hwcg_bit = 1, 2124 .clkr = { 2125 .enable_reg = 0xb014, 2126 .enable_mask = BIT(0), 2127 .hw.init = &(struct clk_init_data){ 2128 .name = "gcc_qmip_video_vcodec_ahb_clk", 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132}; 2133 2134static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { 2135 .halt_reg = 0x4b000, 2136 .halt_check = BRANCH_HALT, 2137 .clkr = { 2138 .enable_reg = 0x4b000, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(struct clk_init_data){ 2141 .name = "gcc_qspi_cnoc_periph_ahb_clk", 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145}; 2146 2147static struct clk_branch gcc_qspi_core_clk = { 2148 .halt_reg = 0x4b004, 2149 .halt_check = BRANCH_HALT, 2150 .clkr = { 2151 .enable_reg = 0x4b004, 2152 .enable_mask = BIT(0), 2153 .hw.init = &(struct clk_init_data){ 2154 .name = "gcc_qspi_core_clk", 2155 .parent_hws = (const struct clk_hw *[]){ 2156 &gcc_qspi_core_clk_src.clkr.hw }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162}; 2163 2164static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2165 .halt_reg = 0x17144, 2166 .halt_check = BRANCH_HALT_VOTED, 2167 .clkr = { 2168 .enable_reg = 0x5200c, 2169 .enable_mask = BIT(10), 2170 .hw.init = &(struct clk_init_data){ 2171 .name = "gcc_qupv3_wrap0_s0_clk", 2172 .parent_hws = (const struct clk_hw *[]){ 2173 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179}; 2180 2181static struct clk_branch gcc_qupv3_wrap0_s1_clk = { 2182 .halt_reg = 0x17274, 2183 .halt_check = BRANCH_HALT_VOTED, 2184 .clkr = { 2185 .enable_reg = 0x5200c, 2186 .enable_mask = BIT(11), 2187 .hw.init = &(struct clk_init_data){ 2188 .name = "gcc_qupv3_wrap0_s1_clk", 2189 .parent_hws = (const struct clk_hw *[]){ 2190 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw }, 2191 .num_parents = 1, 2192 .flags = CLK_SET_RATE_PARENT, 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196}; 2197 2198static struct clk_branch gcc_qupv3_wrap0_s2_clk = { 2199 .halt_reg = 0x173a4, 2200 .halt_check = BRANCH_HALT_VOTED, 2201 .clkr = { 2202 .enable_reg = 0x5200c, 2203 .enable_mask = BIT(12), 2204 .hw.init = &(struct clk_init_data){ 2205 .name = "gcc_qupv3_wrap0_s2_clk", 2206 .parent_hws = (const struct clk_hw *[]){ 2207 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213}; 2214 2215static struct clk_branch gcc_qupv3_wrap0_s3_clk = { 2216 .halt_reg = 0x174d4, 2217 .halt_check = BRANCH_HALT_VOTED, 2218 .clkr = { 2219 .enable_reg = 0x5200c, 2220 .enable_mask = BIT(13), 2221 .hw.init = &(struct clk_init_data){ 2222 .name = "gcc_qupv3_wrap0_s3_clk", 2223 .parent_hws = (const struct clk_hw *[]){ 2224 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw }, 2225 .num_parents = 1, 2226 .flags = CLK_SET_RATE_PARENT, 2227 .ops = &clk_branch2_ops, 2228 }, 2229 }, 2230}; 2231 2232static struct clk_branch gcc_qupv3_wrap0_s4_clk = { 2233 .halt_reg = 0x17604, 2234 .halt_check = BRANCH_HALT_VOTED, 2235 .clkr = { 2236 .enable_reg = 0x5200c, 2237 .enable_mask = BIT(14), 2238 .hw.init = &(struct clk_init_data){ 2239 .name = "gcc_qupv3_wrap0_s4_clk", 2240 .parent_hws = (const struct clk_hw *[]){ 2241 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw }, 2242 .num_parents = 1, 2243 .flags = CLK_SET_RATE_PARENT, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247}; 2248 2249static struct clk_branch gcc_qupv3_wrap0_s5_clk = { 2250 .halt_reg = 0x17734, 2251 .halt_check = BRANCH_HALT_VOTED, 2252 .clkr = { 2253 .enable_reg = 0x5200c, 2254 .enable_mask = BIT(15), 2255 .hw.init = &(struct clk_init_data){ 2256 .name = "gcc_qupv3_wrap0_s5_clk", 2257 .parent_hws = (const struct clk_hw *[]){ 2258 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw }, 2259 .num_parents = 1, 2260 .flags = CLK_SET_RATE_PARENT, 2261 .ops = &clk_branch2_ops, 2262 }, 2263 }, 2264}; 2265 2266static struct clk_branch gcc_qupv3_wrap0_s6_clk = { 2267 .halt_reg = 0x17864, 2268 .halt_check = BRANCH_HALT_VOTED, 2269 .clkr = { 2270 .enable_reg = 0x5200c, 2271 .enable_mask = BIT(16), 2272 .hw.init = &(struct clk_init_data){ 2273 .name = "gcc_qupv3_wrap0_s6_clk", 2274 .parent_hws = (const struct clk_hw *[]){ 2275 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281}; 2282 2283static struct clk_branch gcc_qupv3_wrap0_s7_clk = { 2284 .halt_reg = 0x17994, 2285 .halt_check = BRANCH_HALT_VOTED, 2286 .clkr = { 2287 .enable_reg = 0x5200c, 2288 .enable_mask = BIT(17), 2289 .hw.init = &(struct clk_init_data){ 2290 .name = "gcc_qupv3_wrap0_s7_clk", 2291 .parent_hws = (const struct clk_hw *[]){ 2292 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298}; 2299 2300static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2301 .halt_reg = 0x18144, 2302 .halt_check = BRANCH_HALT_VOTED, 2303 .clkr = { 2304 .enable_reg = 0x5200c, 2305 .enable_mask = BIT(22), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "gcc_qupv3_wrap1_s0_clk", 2308 .parent_hws = (const struct clk_hw *[]){ 2309 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315}; 2316 2317static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2318 .halt_reg = 0x18274, 2319 .halt_check = BRANCH_HALT_VOTED, 2320 .clkr = { 2321 .enable_reg = 0x5200c, 2322 .enable_mask = BIT(23), 2323 .hw.init = &(struct clk_init_data){ 2324 .name = "gcc_qupv3_wrap1_s1_clk", 2325 .parent_hws = (const struct clk_hw *[]){ 2326 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332}; 2333 2334static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2335 .halt_reg = 0x183a4, 2336 .halt_check = BRANCH_HALT_VOTED, 2337 .clkr = { 2338 .enable_reg = 0x5200c, 2339 .enable_mask = BIT(24), 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "gcc_qupv3_wrap1_s2_clk", 2342 .parent_hws = (const struct clk_hw *[]){ 2343 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw }, 2344 .num_parents = 1, 2345 .flags = CLK_SET_RATE_PARENT, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349}; 2350 2351static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2352 .halt_reg = 0x184d4, 2353 .halt_check = BRANCH_HALT_VOTED, 2354 .clkr = { 2355 .enable_reg = 0x5200c, 2356 .enable_mask = BIT(25), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_qupv3_wrap1_s3_clk", 2359 .parent_hws = (const struct clk_hw *[]){ 2360 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366}; 2367 2368static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2369 .halt_reg = 0x18604, 2370 .halt_check = BRANCH_HALT_VOTED, 2371 .clkr = { 2372 .enable_reg = 0x5200c, 2373 .enable_mask = BIT(26), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_qupv3_wrap1_s4_clk", 2376 .parent_hws = (const struct clk_hw *[]){ 2377 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383}; 2384 2385static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2386 .halt_reg = 0x18734, 2387 .halt_check = BRANCH_HALT_VOTED, 2388 .clkr = { 2389 .enable_reg = 0x5200c, 2390 .enable_mask = BIT(27), 2391 .hw.init = &(struct clk_init_data){ 2392 .name = "gcc_qupv3_wrap1_s5_clk", 2393 .parent_hws = (const struct clk_hw *[]){ 2394 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw }, 2395 .num_parents = 1, 2396 .flags = CLK_SET_RATE_PARENT, 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400}; 2401 2402static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2403 .halt_reg = 0x1e144, 2404 .halt_check = BRANCH_HALT_VOTED, 2405 .clkr = { 2406 .enable_reg = 0x52014, 2407 .enable_mask = BIT(4), 2408 .hw.init = &(struct clk_init_data){ 2409 .name = "gcc_qupv3_wrap2_s0_clk", 2410 .parent_hws = (const struct clk_hw *[]){ 2411 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw }, 2412 .num_parents = 1, 2413 .flags = CLK_SET_RATE_PARENT, 2414 .ops = &clk_branch2_ops, 2415 }, 2416 }, 2417}; 2418 2419static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2420 .halt_reg = 0x1e274, 2421 .halt_check = BRANCH_HALT_VOTED, 2422 .clkr = { 2423 .enable_reg = 0x52014, 2424 .enable_mask = BIT(5), 2425 .hw.init = &(struct clk_init_data){ 2426 .name = "gcc_qupv3_wrap2_s1_clk", 2427 .parent_hws = (const struct clk_hw *[]){ 2428 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw }, 2429 .num_parents = 1, 2430 .flags = CLK_SET_RATE_PARENT, 2431 .ops = &clk_branch2_ops, 2432 }, 2433 }, 2434}; 2435 2436static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2437 .halt_reg = 0x1e3a4, 2438 .halt_check = BRANCH_HALT_VOTED, 2439 .clkr = { 2440 .enable_reg = 0x52014, 2441 .enable_mask = BIT(6), 2442 .hw.init = &(struct clk_init_data){ 2443 .name = "gcc_qupv3_wrap2_s2_clk", 2444 .parent_hws = (const struct clk_hw *[]){ 2445 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw }, 2446 .num_parents = 1, 2447 .flags = CLK_SET_RATE_PARENT, 2448 .ops = &clk_branch2_ops, 2449 }, 2450 }, 2451}; 2452 2453static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2454 .halt_reg = 0x1e4d4, 2455 .halt_check = BRANCH_HALT_VOTED, 2456 .clkr = { 2457 .enable_reg = 0x52014, 2458 .enable_mask = BIT(7), 2459 .hw.init = &(struct clk_init_data){ 2460 .name = "gcc_qupv3_wrap2_s3_clk", 2461 .parent_hws = (const struct clk_hw *[]){ 2462 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw }, 2463 .num_parents = 1, 2464 .flags = CLK_SET_RATE_PARENT, 2465 .ops = &clk_branch2_ops, 2466 }, 2467 }, 2468}; 2469 2470static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2471 .halt_reg = 0x1e604, 2472 .halt_check = BRANCH_HALT_VOTED, 2473 .clkr = { 2474 .enable_reg = 0x52014, 2475 .enable_mask = BIT(8), 2476 .hw.init = &(struct clk_init_data){ 2477 .name = "gcc_qupv3_wrap2_s4_clk", 2478 .parent_hws = (const struct clk_hw *[]){ 2479 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw }, 2480 .num_parents = 1, 2481 .flags = CLK_SET_RATE_PARENT, 2482 .ops = &clk_branch2_ops, 2483 }, 2484 }, 2485}; 2486 2487static struct clk_branch gcc_qupv3_wrap2_s5_clk = { 2488 .halt_reg = 0x1e734, 2489 .halt_check = BRANCH_HALT_VOTED, 2490 .clkr = { 2491 .enable_reg = 0x52014, 2492 .enable_mask = BIT(9), 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "gcc_qupv3_wrap2_s5_clk", 2495 .parent_hws = (const struct clk_hw *[]){ 2496 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT, 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502}; 2503 2504static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { 2505 .halt_reg = 0x17004, 2506 .halt_check = BRANCH_HALT_VOTED, 2507 .clkr = { 2508 .enable_reg = 0x5200c, 2509 .enable_mask = BIT(6), 2510 .hw.init = &(struct clk_init_data){ 2511 .name = "gcc_qupv3_wrap_0_m_ahb_clk", 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515}; 2516 2517static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { 2518 .halt_reg = 0x17008, 2519 .halt_check = BRANCH_HALT_VOTED, 2520 .hwcg_reg = 0x17008, 2521 .hwcg_bit = 1, 2522 .clkr = { 2523 .enable_reg = 0x5200c, 2524 .enable_mask = BIT(7), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "gcc_qupv3_wrap_0_s_ahb_clk", 2527 .ops = &clk_branch2_ops, 2528 }, 2529 }, 2530}; 2531 2532static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { 2533 .halt_reg = 0x18004, 2534 .halt_check = BRANCH_HALT_VOTED, 2535 .clkr = { 2536 .enable_reg = 0x5200c, 2537 .enable_mask = BIT(20), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gcc_qupv3_wrap_1_m_ahb_clk", 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543}; 2544 2545static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2546 .halt_reg = 0x18008, 2547 .halt_check = BRANCH_HALT_VOTED, 2548 .hwcg_reg = 0x18008, 2549 .hwcg_bit = 1, 2550 .clkr = { 2551 .enable_reg = 0x5200c, 2552 .enable_mask = BIT(21), 2553 .hw.init = &(struct clk_init_data){ 2554 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2555 .ops = &clk_branch2_ops, 2556 }, 2557 }, 2558}; 2559 2560static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2561 .halt_reg = 0x1e004, 2562 .halt_check = BRANCH_HALT_VOTED, 2563 .clkr = { 2564 .enable_reg = 0x52014, 2565 .enable_mask = BIT(2), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571}; 2572 2573static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2574 .halt_reg = 0x1e008, 2575 .halt_check = BRANCH_HALT_VOTED, 2576 .hwcg_reg = 0x1e008, 2577 .hwcg_bit = 1, 2578 .clkr = { 2579 .enable_reg = 0x52014, 2580 .enable_mask = BIT(1), 2581 .hw.init = &(struct clk_init_data){ 2582 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2583 .ops = &clk_branch2_ops, 2584 }, 2585 }, 2586}; 2587 2588static struct clk_branch gcc_sdcc2_ahb_clk = { 2589 .halt_reg = 0x14008, 2590 .halt_check = BRANCH_HALT, 2591 .clkr = { 2592 .enable_reg = 0x14008, 2593 .enable_mask = BIT(0), 2594 .hw.init = &(struct clk_init_data){ 2595 .name = "gcc_sdcc2_ahb_clk", 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599}; 2600 2601static struct clk_branch gcc_sdcc2_apps_clk = { 2602 .halt_reg = 0x14004, 2603 .halt_check = BRANCH_HALT, 2604 .clkr = { 2605 .enable_reg = 0x14004, 2606 .enable_mask = BIT(0), 2607 .hw.init = &(struct clk_init_data){ 2608 .name = "gcc_sdcc2_apps_clk", 2609 .parent_hws = (const struct clk_hw *[]){ 2610 &gcc_sdcc2_apps_clk_src.clkr.hw }, 2611 .num_parents = 1, 2612 .flags = CLK_SET_RATE_PARENT, 2613 .ops = &clk_branch2_ops, 2614 }, 2615 }, 2616}; 2617 2618static struct clk_branch gcc_sdcc4_ahb_clk = { 2619 .halt_reg = 0x16008, 2620 .halt_check = BRANCH_HALT, 2621 .clkr = { 2622 .enable_reg = 0x16008, 2623 .enable_mask = BIT(0), 2624 .hw.init = &(struct clk_init_data){ 2625 .name = "gcc_sdcc4_ahb_clk", 2626 .ops = &clk_branch2_ops, 2627 }, 2628 }, 2629}; 2630 2631static struct clk_branch gcc_sdcc4_apps_clk = { 2632 .halt_reg = 0x16004, 2633 .halt_check = BRANCH_HALT, 2634 .clkr = { 2635 .enable_reg = 0x16004, 2636 .enable_mask = BIT(0), 2637 .hw.init = &(struct clk_init_data){ 2638 .name = "gcc_sdcc4_apps_clk", 2639 .parent_hws = (const struct clk_hw *[]){ 2640 &gcc_sdcc4_apps_clk_src.clkr.hw }, 2641 .num_parents = 1, 2642 .flags = CLK_SET_RATE_PARENT, 2643 .ops = &clk_branch2_ops, 2644 }, 2645 }, 2646}; 2647 2648static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 2649 .halt_reg = 0x4819c, 2650 .halt_check = BRANCH_HALT_VOTED, 2651 .clkr = { 2652 .enable_reg = 0x52004, 2653 .enable_mask = BIT(0), 2654 .hw.init = &(struct clk_init_data){ 2655 .name = "gcc_sys_noc_cpuss_ahb_clk", 2656 .parent_hws = (const struct clk_hw *[]){ 2657 &gcc_cpuss_ahb_clk_src.clkr.hw }, 2658 .num_parents = 1, 2659 /* required for cpuss */ 2660 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 2661 .ops = &clk_branch2_ops, 2662 }, 2663 }, 2664}; 2665 2666static struct clk_branch gcc_tsif_ahb_clk = { 2667 .halt_reg = 0x36004, 2668 .halt_check = BRANCH_HALT, 2669 .clkr = { 2670 .enable_reg = 0x36004, 2671 .enable_mask = BIT(0), 2672 .hw.init = &(struct clk_init_data){ 2673 .name = "gcc_tsif_ahb_clk", 2674 .ops = &clk_branch2_ops, 2675 }, 2676 }, 2677}; 2678 2679static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2680 .halt_reg = 0x3600c, 2681 .halt_check = BRANCH_HALT, 2682 .clkr = { 2683 .enable_reg = 0x3600c, 2684 .enable_mask = BIT(0), 2685 .hw.init = &(struct clk_init_data){ 2686 .name = "gcc_tsif_inactivity_timers_clk", 2687 .ops = &clk_branch2_ops, 2688 }, 2689 }, 2690}; 2691 2692static struct clk_branch gcc_tsif_ref_clk = { 2693 .halt_reg = 0x36008, 2694 .halt_check = BRANCH_HALT, 2695 .clkr = { 2696 .enable_reg = 0x36008, 2697 .enable_mask = BIT(0), 2698 .hw.init = &(struct clk_init_data){ 2699 .name = "gcc_tsif_ref_clk", 2700 .parent_hws = (const struct clk_hw *[]){ 2701 &gcc_tsif_ref_clk_src.clkr.hw }, 2702 .num_parents = 1, 2703 .flags = CLK_SET_RATE_PARENT, 2704 .ops = &clk_branch2_ops, 2705 }, 2706 }, 2707}; 2708 2709static struct clk_branch gcc_ufs_card_ahb_clk = { 2710 .halt_reg = 0x75014, 2711 .halt_check = BRANCH_HALT, 2712 .hwcg_reg = 0x75014, 2713 .hwcg_bit = 1, 2714 .clkr = { 2715 .enable_reg = 0x75014, 2716 .enable_mask = BIT(0), 2717 .hw.init = &(struct clk_init_data){ 2718 .name = "gcc_ufs_card_ahb_clk", 2719 .ops = &clk_branch2_ops, 2720 }, 2721 }, 2722}; 2723 2724static struct clk_branch gcc_ufs_card_axi_clk = { 2725 .halt_reg = 0x75010, 2726 .halt_check = BRANCH_HALT, 2727 .hwcg_reg = 0x75010, 2728 .hwcg_bit = 1, 2729 .clkr = { 2730 .enable_reg = 0x75010, 2731 .enable_mask = BIT(0), 2732 .hw.init = &(struct clk_init_data){ 2733 .name = "gcc_ufs_card_axi_clk", 2734 .parent_hws = (const struct clk_hw *[]){ 2735 &gcc_ufs_card_axi_clk_src.clkr.hw }, 2736 .num_parents = 1, 2737 .flags = CLK_SET_RATE_PARENT, 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741}; 2742 2743static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { 2744 .halt_reg = 0x75010, 2745 .halt_check = BRANCH_HALT, 2746 .hwcg_reg = 0x75010, 2747 .hwcg_bit = 1, 2748 .clkr = { 2749 .enable_reg = 0x75010, 2750 .enable_mask = BIT(1), 2751 .hw.init = &(struct clk_init_data){ 2752 .name = "gcc_ufs_card_axi_hw_ctl_clk", 2753 .parent_hws = (const struct clk_hw *[]){ 2754 &gcc_ufs_card_axi_clk.clkr.hw }, 2755 .num_parents = 1, 2756 .flags = CLK_SET_RATE_PARENT, 2757 .ops = &clk_branch_simple_ops, 2758 }, 2759 }, 2760}; 2761 2762static struct clk_branch gcc_ufs_card_clkref_clk = { 2763 .halt_reg = 0x8c004, 2764 .halt_check = BRANCH_HALT, 2765 .clkr = { 2766 .enable_reg = 0x8c004, 2767 .enable_mask = BIT(0), 2768 .hw.init = &(struct clk_init_data){ 2769 .name = "gcc_ufs_card_clkref_clk", 2770 .ops = &clk_branch2_ops, 2771 }, 2772 }, 2773}; 2774 2775static struct clk_branch gcc_ufs_card_ice_core_clk = { 2776 .halt_reg = 0x7505c, 2777 .halt_check = BRANCH_HALT, 2778 .hwcg_reg = 0x7505c, 2779 .hwcg_bit = 1, 2780 .clkr = { 2781 .enable_reg = 0x7505c, 2782 .enable_mask = BIT(0), 2783 .hw.init = &(struct clk_init_data){ 2784 .name = "gcc_ufs_card_ice_core_clk", 2785 .parent_hws = (const struct clk_hw *[]){ 2786 &gcc_ufs_card_ice_core_clk_src.clkr.hw }, 2787 .num_parents = 1, 2788 .flags = CLK_SET_RATE_PARENT, 2789 .ops = &clk_branch2_ops, 2790 }, 2791 }, 2792}; 2793 2794static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { 2795 .halt_reg = 0x7505c, 2796 .halt_check = BRANCH_HALT, 2797 .hwcg_reg = 0x7505c, 2798 .hwcg_bit = 1, 2799 .clkr = { 2800 .enable_reg = 0x7505c, 2801 .enable_mask = BIT(1), 2802 .hw.init = &(struct clk_init_data){ 2803 .name = "gcc_ufs_card_ice_core_hw_ctl_clk", 2804 .parent_hws = (const struct clk_hw *[]){ 2805 &gcc_ufs_card_ice_core_clk.clkr.hw }, 2806 .num_parents = 1, 2807 .flags = CLK_SET_RATE_PARENT, 2808 .ops = &clk_branch_simple_ops, 2809 }, 2810 }, 2811}; 2812 2813static struct clk_branch gcc_ufs_card_phy_aux_clk = { 2814 .halt_reg = 0x75090, 2815 .halt_check = BRANCH_HALT, 2816 .hwcg_reg = 0x75090, 2817 .hwcg_bit = 1, 2818 .clkr = { 2819 .enable_reg = 0x75090, 2820 .enable_mask = BIT(0), 2821 .hw.init = &(struct clk_init_data){ 2822 .name = "gcc_ufs_card_phy_aux_clk", 2823 .parent_hws = (const struct clk_hw *[]){ 2824 &gcc_ufs_card_phy_aux_clk_src.clkr.hw }, 2825 .num_parents = 1, 2826 .flags = CLK_SET_RATE_PARENT, 2827 .ops = &clk_branch2_ops, 2828 }, 2829 }, 2830}; 2831 2832static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { 2833 .halt_reg = 0x75090, 2834 .halt_check = BRANCH_HALT, 2835 .hwcg_reg = 0x75090, 2836 .hwcg_bit = 1, 2837 .clkr = { 2838 .enable_reg = 0x75090, 2839 .enable_mask = BIT(1), 2840 .hw.init = &(struct clk_init_data){ 2841 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", 2842 .parent_hws = (const struct clk_hw *[]){ 2843 &gcc_ufs_card_phy_aux_clk.clkr.hw }, 2844 .num_parents = 1, 2845 .flags = CLK_SET_RATE_PARENT, 2846 .ops = &clk_branch_simple_ops, 2847 }, 2848 }, 2849}; 2850 2851/* external clocks so add BRANCH_HALT_SKIP */ 2852static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { 2853 .halt_check = BRANCH_HALT_SKIP, 2854 .clkr = { 2855 .enable_reg = 0x7501c, 2856 .enable_mask = BIT(0), 2857 .hw.init = &(struct clk_init_data){ 2858 .name = "gcc_ufs_card_rx_symbol_0_clk", 2859 .ops = &clk_branch2_ops, 2860 }, 2861 }, 2862}; 2863 2864/* external clocks so add BRANCH_HALT_SKIP */ 2865static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { 2866 .halt_check = BRANCH_HALT_SKIP, 2867 .clkr = { 2868 .enable_reg = 0x750ac, 2869 .enable_mask = BIT(0), 2870 .hw.init = &(struct clk_init_data){ 2871 .name = "gcc_ufs_card_rx_symbol_1_clk", 2872 .ops = &clk_branch2_ops, 2873 }, 2874 }, 2875}; 2876 2877/* external clocks so add BRANCH_HALT_SKIP */ 2878static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { 2879 .halt_check = BRANCH_HALT_SKIP, 2880 .clkr = { 2881 .enable_reg = 0x75018, 2882 .enable_mask = BIT(0), 2883 .hw.init = &(struct clk_init_data){ 2884 .name = "gcc_ufs_card_tx_symbol_0_clk", 2885 .ops = &clk_branch2_ops, 2886 }, 2887 }, 2888}; 2889 2890static struct clk_branch gcc_ufs_card_unipro_core_clk = { 2891 .halt_reg = 0x75058, 2892 .halt_check = BRANCH_HALT, 2893 .hwcg_reg = 0x75058, 2894 .hwcg_bit = 1, 2895 .clkr = { 2896 .enable_reg = 0x75058, 2897 .enable_mask = BIT(0), 2898 .hw.init = &(struct clk_init_data){ 2899 .name = "gcc_ufs_card_unipro_core_clk", 2900 .parent_hws = (const struct clk_hw *[]){ 2901 &gcc_ufs_card_unipro_core_clk_src.clkr.hw }, 2902 .num_parents = 1, 2903 .flags = CLK_SET_RATE_PARENT, 2904 .ops = &clk_branch2_ops, 2905 }, 2906 }, 2907}; 2908 2909static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { 2910 .halt_reg = 0x75058, 2911 .halt_check = BRANCH_HALT, 2912 .hwcg_reg = 0x75058, 2913 .hwcg_bit = 1, 2914 .clkr = { 2915 .enable_reg = 0x75058, 2916 .enable_mask = BIT(1), 2917 .hw.init = &(struct clk_init_data){ 2918 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", 2919 .parent_hws = (const struct clk_hw *[]){ 2920 &gcc_ufs_card_unipro_core_clk.clkr.hw }, 2921 .num_parents = 1, 2922 .flags = CLK_SET_RATE_PARENT, 2923 .ops = &clk_branch_simple_ops, 2924 }, 2925 }, 2926}; 2927 2928static struct clk_branch gcc_ufs_mem_clkref_clk = { 2929 .halt_reg = 0x8c000, 2930 .halt_check = BRANCH_HALT, 2931 .clkr = { 2932 .enable_reg = 0x8c000, 2933 .enable_mask = BIT(0), 2934 .hw.init = &(struct clk_init_data){ 2935 .name = "gcc_ufs_mem_clkref_clk", 2936 .ops = &clk_branch2_ops, 2937 }, 2938 }, 2939}; 2940 2941static struct clk_branch gcc_ufs_phy_ahb_clk = { 2942 .halt_reg = 0x77014, 2943 .halt_check = BRANCH_HALT, 2944 .hwcg_reg = 0x77014, 2945 .hwcg_bit = 1, 2946 .clkr = { 2947 .enable_reg = 0x77014, 2948 .enable_mask = BIT(0), 2949 .hw.init = &(struct clk_init_data){ 2950 .name = "gcc_ufs_phy_ahb_clk", 2951 .ops = &clk_branch2_ops, 2952 }, 2953 }, 2954}; 2955 2956static struct clk_branch gcc_ufs_phy_axi_clk = { 2957 .halt_reg = 0x77010, 2958 .halt_check = BRANCH_HALT, 2959 .hwcg_reg = 0x77010, 2960 .hwcg_bit = 1, 2961 .clkr = { 2962 .enable_reg = 0x77010, 2963 .enable_mask = BIT(0), 2964 .hw.init = &(struct clk_init_data){ 2965 .name = "gcc_ufs_phy_axi_clk", 2966 .parent_hws = (const struct clk_hw *[]){ 2967 &gcc_ufs_phy_axi_clk_src.clkr.hw }, 2968 .num_parents = 1, 2969 .flags = CLK_SET_RATE_PARENT, 2970 .ops = &clk_branch2_ops, 2971 }, 2972 }, 2973}; 2974 2975static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { 2976 .halt_reg = 0x77010, 2977 .halt_check = BRANCH_HALT, 2978 .hwcg_reg = 0x77010, 2979 .hwcg_bit = 1, 2980 .clkr = { 2981 .enable_reg = 0x77010, 2982 .enable_mask = BIT(1), 2983 .hw.init = &(struct clk_init_data){ 2984 .name = "gcc_ufs_phy_axi_hw_ctl_clk", 2985 .parent_hws = (const struct clk_hw *[]){ 2986 &gcc_ufs_phy_axi_clk.clkr.hw }, 2987 .num_parents = 1, 2988 .flags = CLK_SET_RATE_PARENT, 2989 .ops = &clk_branch_simple_ops, 2990 }, 2991 }, 2992}; 2993 2994static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2995 .halt_reg = 0x7705c, 2996 .halt_check = BRANCH_HALT, 2997 .hwcg_reg = 0x7705c, 2998 .hwcg_bit = 1, 2999 .clkr = { 3000 .enable_reg = 0x7705c, 3001 .enable_mask = BIT(0), 3002 .hw.init = &(struct clk_init_data){ 3003 .name = "gcc_ufs_phy_ice_core_clk", 3004 .parent_hws = (const struct clk_hw *[]){ 3005 &gcc_ufs_phy_ice_core_clk_src.clkr.hw }, 3006 .num_parents = 1, 3007 .flags = CLK_SET_RATE_PARENT, 3008 .ops = &clk_branch2_ops, 3009 }, 3010 }, 3011}; 3012 3013static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { 3014 .halt_reg = 0x7705c, 3015 .halt_check = BRANCH_HALT, 3016 .hwcg_reg = 0x7705c, 3017 .hwcg_bit = 1, 3018 .clkr = { 3019 .enable_reg = 0x7705c, 3020 .enable_mask = BIT(1), 3021 .hw.init = &(struct clk_init_data){ 3022 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", 3023 .parent_hws = (const struct clk_hw *[]){ 3024 &gcc_ufs_phy_ice_core_clk.clkr.hw }, 3025 .num_parents = 1, 3026 .flags = CLK_SET_RATE_PARENT, 3027 .ops = &clk_branch_simple_ops, 3028 }, 3029 }, 3030}; 3031 3032static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 3033 .halt_reg = 0x77090, 3034 .halt_check = BRANCH_HALT, 3035 .hwcg_reg = 0x77090, 3036 .hwcg_bit = 1, 3037 .clkr = { 3038 .enable_reg = 0x77090, 3039 .enable_mask = BIT(0), 3040 .hw.init = &(struct clk_init_data){ 3041 .name = "gcc_ufs_phy_phy_aux_clk", 3042 .parent_hws = (const struct clk_hw *[]){ 3043 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw }, 3044 .num_parents = 1, 3045 .flags = CLK_SET_RATE_PARENT, 3046 .ops = &clk_branch2_ops, 3047 }, 3048 }, 3049}; 3050 3051static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 3052 .halt_reg = 0x77090, 3053 .halt_check = BRANCH_HALT, 3054 .hwcg_reg = 0x77090, 3055 .hwcg_bit = 1, 3056 .clkr = { 3057 .enable_reg = 0x77090, 3058 .enable_mask = BIT(1), 3059 .hw.init = &(struct clk_init_data){ 3060 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", 3061 .parent_hws = (const struct clk_hw *[]){ 3062 &gcc_ufs_phy_phy_aux_clk.clkr.hw }, 3063 .num_parents = 1, 3064 .flags = CLK_SET_RATE_PARENT, 3065 .ops = &clk_branch_simple_ops, 3066 }, 3067 }, 3068}; 3069 3070/* external clocks so add BRANCH_HALT_SKIP */ 3071static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3072 .halt_check = BRANCH_HALT_SKIP, 3073 .clkr = { 3074 .enable_reg = 0x7701c, 3075 .enable_mask = BIT(0), 3076 .hw.init = &(struct clk_init_data){ 3077 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3078 .ops = &clk_branch2_ops, 3079 }, 3080 }, 3081}; 3082 3083/* external clocks so add BRANCH_HALT_SKIP */ 3084static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3085 .halt_check = BRANCH_HALT_SKIP, 3086 .clkr = { 3087 .enable_reg = 0x770ac, 3088 .enable_mask = BIT(0), 3089 .hw.init = &(struct clk_init_data){ 3090 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3091 .ops = &clk_branch2_ops, 3092 }, 3093 }, 3094}; 3095 3096/* external clocks so add BRANCH_HALT_SKIP */ 3097static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3098 .halt_check = BRANCH_HALT_SKIP, 3099 .clkr = { 3100 .enable_reg = 0x77018, 3101 .enable_mask = BIT(0), 3102 .hw.init = &(struct clk_init_data){ 3103 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3104 .ops = &clk_branch2_ops, 3105 }, 3106 }, 3107}; 3108 3109static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 3110 .halt_reg = 0x77058, 3111 .halt_check = BRANCH_HALT, 3112 .hwcg_reg = 0x77058, 3113 .hwcg_bit = 1, 3114 .clkr = { 3115 .enable_reg = 0x77058, 3116 .enable_mask = BIT(0), 3117 .hw.init = &(struct clk_init_data){ 3118 .name = "gcc_ufs_phy_unipro_core_clk", 3119 .parent_hws = (const struct clk_hw *[]){ 3120 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw }, 3121 .num_parents = 1, 3122 .flags = CLK_SET_RATE_PARENT, 3123 .ops = &clk_branch2_ops, 3124 }, 3125 }, 3126}; 3127 3128static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { 3129 .halt_reg = 0x77058, 3130 .halt_check = BRANCH_HALT, 3131 .hwcg_reg = 0x77058, 3132 .hwcg_bit = 1, 3133 .clkr = { 3134 .enable_reg = 0x77058, 3135 .enable_mask = BIT(1), 3136 .hw.init = &(struct clk_init_data){ 3137 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", 3138 .parent_hws = (const struct clk_hw *[]){ 3139 &gcc_ufs_phy_unipro_core_clk.clkr.hw }, 3140 .num_parents = 1, 3141 .flags = CLK_SET_RATE_PARENT, 3142 .ops = &clk_branch_simple_ops, 3143 }, 3144 }, 3145}; 3146 3147static struct clk_branch gcc_usb30_prim_master_clk = { 3148 .halt_reg = 0xf010, 3149 .halt_check = BRANCH_HALT, 3150 .clkr = { 3151 .enable_reg = 0xf010, 3152 .enable_mask = BIT(0), 3153 .hw.init = &(struct clk_init_data){ 3154 .name = "gcc_usb30_prim_master_clk", 3155 .parent_hws = (const struct clk_hw *[]){ 3156 &gcc_usb30_prim_master_clk_src.clkr.hw }, 3157 .num_parents = 1, 3158 .flags = CLK_SET_RATE_PARENT, 3159 .ops = &clk_branch2_ops, 3160 }, 3161 }, 3162}; 3163 3164static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3165 .halt_reg = 0xf018, 3166 .halt_check = BRANCH_HALT, 3167 .clkr = { 3168 .enable_reg = 0xf018, 3169 .enable_mask = BIT(0), 3170 .hw.init = &(struct clk_init_data){ 3171 .name = "gcc_usb30_prim_mock_utmi_clk", 3172 .parent_hws = (const struct clk_hw *[]){ 3173 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw }, 3174 .num_parents = 1, 3175 .flags = CLK_SET_RATE_PARENT, 3176 .ops = &clk_branch2_ops, 3177 }, 3178 }, 3179}; 3180 3181static struct clk_branch gcc_usb30_prim_sleep_clk = { 3182 .halt_reg = 0xf014, 3183 .halt_check = BRANCH_HALT, 3184 .clkr = { 3185 .enable_reg = 0xf014, 3186 .enable_mask = BIT(0), 3187 .hw.init = &(struct clk_init_data){ 3188 .name = "gcc_usb30_prim_sleep_clk", 3189 .ops = &clk_branch2_ops, 3190 }, 3191 }, 3192}; 3193 3194static struct clk_branch gcc_usb30_sec_master_clk = { 3195 .halt_reg = 0x10010, 3196 .halt_check = BRANCH_HALT, 3197 .clkr = { 3198 .enable_reg = 0x10010, 3199 .enable_mask = BIT(0), 3200 .hw.init = &(struct clk_init_data){ 3201 .name = "gcc_usb30_sec_master_clk", 3202 .parent_hws = (const struct clk_hw *[]){ 3203 &gcc_usb30_sec_master_clk_src.clkr.hw }, 3204 .num_parents = 1, 3205 .flags = CLK_SET_RATE_PARENT, 3206 .ops = &clk_branch2_ops, 3207 }, 3208 }, 3209}; 3210 3211static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { 3212 .halt_reg = 0x10018, 3213 .halt_check = BRANCH_HALT, 3214 .clkr = { 3215 .enable_reg = 0x10018, 3216 .enable_mask = BIT(0), 3217 .hw.init = &(struct clk_init_data){ 3218 .name = "gcc_usb30_sec_mock_utmi_clk", 3219 .parent_hws = (const struct clk_hw *[]){ 3220 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw }, 3221 .num_parents = 1, 3222 .flags = CLK_SET_RATE_PARENT, 3223 .ops = &clk_branch2_ops, 3224 }, 3225 }, 3226}; 3227 3228static struct clk_branch gcc_usb30_sec_sleep_clk = { 3229 .halt_reg = 0x10014, 3230 .halt_check = BRANCH_HALT, 3231 .clkr = { 3232 .enable_reg = 0x10014, 3233 .enable_mask = BIT(0), 3234 .hw.init = &(struct clk_init_data){ 3235 .name = "gcc_usb30_sec_sleep_clk", 3236 .ops = &clk_branch2_ops, 3237 }, 3238 }, 3239}; 3240 3241static struct clk_branch gcc_usb3_prim_clkref_clk = { 3242 .halt_reg = 0x8c008, 3243 .halt_check = BRANCH_HALT, 3244 .clkr = { 3245 .enable_reg = 0x8c008, 3246 .enable_mask = BIT(0), 3247 .hw.init = &(struct clk_init_data){ 3248 .name = "gcc_usb3_prim_clkref_clk", 3249 .ops = &clk_branch2_ops, 3250 }, 3251 }, 3252}; 3253 3254static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3255 .halt_reg = 0xf050, 3256 .halt_check = BRANCH_HALT, 3257 .clkr = { 3258 .enable_reg = 0xf050, 3259 .enable_mask = BIT(0), 3260 .hw.init = &(struct clk_init_data){ 3261 .name = "gcc_usb3_prim_phy_aux_clk", 3262 .parent_hws = (const struct clk_hw *[]){ 3263 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 3264 .num_parents = 1, 3265 .flags = CLK_SET_RATE_PARENT, 3266 .ops = &clk_branch2_ops, 3267 }, 3268 }, 3269}; 3270 3271static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3272 .halt_reg = 0xf054, 3273 .halt_check = BRANCH_HALT, 3274 .clkr = { 3275 .enable_reg = 0xf054, 3276 .enable_mask = BIT(0), 3277 .hw.init = &(struct clk_init_data){ 3278 .name = "gcc_usb3_prim_phy_com_aux_clk", 3279 .parent_hws = (const struct clk_hw *[]){ 3280 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw }, 3281 .num_parents = 1, 3282 .flags = CLK_SET_RATE_PARENT, 3283 .ops = &clk_branch2_ops, 3284 }, 3285 }, 3286}; 3287 3288static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3289 .halt_check = BRANCH_HALT_SKIP, 3290 .clkr = { 3291 .enable_reg = 0xf058, 3292 .enable_mask = BIT(0), 3293 .hw.init = &(struct clk_init_data){ 3294 .name = "gcc_usb3_prim_phy_pipe_clk", 3295 .ops = &clk_branch2_ops, 3296 }, 3297 }, 3298}; 3299 3300static struct clk_branch gcc_usb3_sec_clkref_clk = { 3301 .halt_reg = 0x8c028, 3302 .halt_check = BRANCH_HALT, 3303 .clkr = { 3304 .enable_reg = 0x8c028, 3305 .enable_mask = BIT(0), 3306 .hw.init = &(struct clk_init_data){ 3307 .name = "gcc_usb3_sec_clkref_clk", 3308 .ops = &clk_branch2_ops, 3309 }, 3310 }, 3311}; 3312 3313static struct clk_branch gcc_usb3_sec_phy_aux_clk = { 3314 .halt_reg = 0x10050, 3315 .halt_check = BRANCH_HALT, 3316 .clkr = { 3317 .enable_reg = 0x10050, 3318 .enable_mask = BIT(0), 3319 .hw.init = &(struct clk_init_data){ 3320 .name = "gcc_usb3_sec_phy_aux_clk", 3321 .parent_hws = (const struct clk_hw *[]){ 3322 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, 3323 .num_parents = 1, 3324 .flags = CLK_SET_RATE_PARENT, 3325 .ops = &clk_branch2_ops, 3326 }, 3327 }, 3328}; 3329 3330static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { 3331 .halt_reg = 0x10054, 3332 .halt_check = BRANCH_HALT, 3333 .clkr = { 3334 .enable_reg = 0x10054, 3335 .enable_mask = BIT(0), 3336 .hw.init = &(struct clk_init_data){ 3337 .name = "gcc_usb3_sec_phy_com_aux_clk", 3338 .parent_hws = (const struct clk_hw *[]){ 3339 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw }, 3340 .num_parents = 1, 3341 .flags = CLK_SET_RATE_PARENT, 3342 .ops = &clk_branch2_ops, 3343 }, 3344 }, 3345}; 3346 3347static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { 3348 .halt_check = BRANCH_HALT_SKIP, 3349 .clkr = { 3350 .enable_reg = 0x10058, 3351 .enable_mask = BIT(0), 3352 .hw.init = &(struct clk_init_data){ 3353 .name = "gcc_usb3_sec_phy_pipe_clk", 3354 .ops = &clk_branch2_ops, 3355 }, 3356 }, 3357}; 3358 3359/* 3360 * Clock ON depends on external parent 'config noc', so cant poll 3361 * delay and also mark as crtitical for video boot 3362 */ 3363static struct clk_branch gcc_video_ahb_clk = { 3364 .halt_reg = 0xb004, 3365 .halt_check = BRANCH_HALT_DELAY, 3366 .hwcg_reg = 0xb004, 3367 .hwcg_bit = 1, 3368 .clkr = { 3369 .enable_reg = 0xb004, 3370 .enable_mask = BIT(0), 3371 .hw.init = &(struct clk_init_data){ 3372 .name = "gcc_video_ahb_clk", 3373 .flags = CLK_IS_CRITICAL, 3374 .ops = &clk_branch2_ops, 3375 }, 3376 }, 3377}; 3378 3379static struct clk_branch gcc_video_axi0_clk = { 3380 .halt_reg = 0xb024, 3381 .halt_check = BRANCH_HALT, 3382 .clkr = { 3383 .enable_reg = 0xb024, 3384 .enable_mask = BIT(0), 3385 .hw.init = &(struct clk_init_data){ 3386 .name = "gcc_video_axi0_clk", 3387 .ops = &clk_branch2_ops, 3388 }, 3389 }, 3390}; 3391 3392static struct clk_branch gcc_video_axi1_clk = { 3393 .halt_reg = 0xb028, 3394 .halt_check = BRANCH_HALT, 3395 .clkr = { 3396 .enable_reg = 0xb028, 3397 .enable_mask = BIT(0), 3398 .hw.init = &(struct clk_init_data){ 3399 .name = "gcc_video_axi1_clk", 3400 .ops = &clk_branch2_ops, 3401 }, 3402 }, 3403}; 3404 3405static struct clk_branch gcc_video_axic_clk = { 3406 .halt_reg = 0xb02c, 3407 .halt_check = BRANCH_HALT, 3408 .clkr = { 3409 .enable_reg = 0xb02c, 3410 .enable_mask = BIT(0), 3411 .hw.init = &(struct clk_init_data){ 3412 .name = "gcc_video_axic_clk", 3413 .ops = &clk_branch2_ops, 3414 }, 3415 }, 3416}; 3417 3418/* XO critical input to video, so no need to poll */ 3419static struct clk_branch gcc_video_xo_clk = { 3420 .halt_reg = 0xb040, 3421 .halt_check = BRANCH_HALT_DELAY, 3422 .clkr = { 3423 .enable_reg = 0xb040, 3424 .enable_mask = BIT(0), 3425 .hw.init = &(struct clk_init_data){ 3426 .name = "gcc_video_xo_clk", 3427 .flags = CLK_IS_CRITICAL, 3428 .ops = &clk_branch2_ops, 3429 }, 3430 }, 3431}; 3432 3433static struct gdsc pcie_0_gdsc = { 3434 .gdscr = 0x6b004, 3435 .pd = { 3436 .name = "pcie_0_gdsc", 3437 }, 3438 .pwrsts = PWRSTS_OFF_ON, 3439 .flags = POLL_CFG_GDSCR, 3440}; 3441 3442static struct gdsc pcie_1_gdsc = { 3443 .gdscr = 0x8d004, 3444 .pd = { 3445 .name = "pcie_1_gdsc", 3446 }, 3447 .pwrsts = PWRSTS_OFF_ON, 3448 .flags = POLL_CFG_GDSCR, 3449}; 3450 3451static struct gdsc ufs_card_gdsc = { 3452 .gdscr = 0x75004, 3453 .pd = { 3454 .name = "ufs_card_gdsc", 3455 }, 3456 .pwrsts = PWRSTS_OFF_ON, 3457 .flags = POLL_CFG_GDSCR, 3458}; 3459 3460static struct gdsc ufs_phy_gdsc = { 3461 .gdscr = 0x77004, 3462 .pd = { 3463 .name = "ufs_phy_gdsc", 3464 }, 3465 .pwrsts = PWRSTS_OFF_ON, 3466 .flags = POLL_CFG_GDSCR, 3467}; 3468 3469static struct gdsc emac_gdsc = { 3470 .gdscr = 0x6004, 3471 .pd = { 3472 .name = "emac_gdsc", 3473 }, 3474 .pwrsts = PWRSTS_OFF_ON, 3475 .flags = POLL_CFG_GDSCR, 3476}; 3477 3478static struct gdsc usb30_prim_gdsc = { 3479 .gdscr = 0xf004, 3480 .pd = { 3481 .name = "usb30_prim_gdsc", 3482 }, 3483 .pwrsts = PWRSTS_OFF_ON, 3484 .flags = POLL_CFG_GDSCR, 3485}; 3486 3487static struct gdsc usb30_sec_gdsc = { 3488 .gdscr = 0x10004, 3489 .pd = { 3490 .name = "usb30_sec_gdsc", 3491 }, 3492 .pwrsts = PWRSTS_OFF_ON, 3493 .flags = POLL_CFG_GDSCR, 3494}; 3495 3496static struct clk_regmap *gcc_sm8150_clocks[] = { 3497 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3498 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, 3499 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = 3500 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, 3501 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3502 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = 3503 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, 3504 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3505 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, 3506 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3507 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3508 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3509 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3510 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3511 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3512 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 3513 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3514 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3515 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, 3516 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3517 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 3518 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3519 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3520 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3521 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3522 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3523 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr, 3524 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr, 3525 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, 3526 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr, 3527 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr, 3528 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr, 3529 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3530 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3531 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3532 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3533 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3534 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3535 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3536 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3537 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3538 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3539 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3540 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3541 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, 3542 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, 3543 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, 3544 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, 3545 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, 3546 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, 3547 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, 3548 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr, 3549 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3550 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3551 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3552 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, 3553 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3554 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3555 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3556 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3557 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3558 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3559 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3560 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, 3561 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3562 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3563 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3564 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3565 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3566 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, 3567 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3568 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3569 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3570 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3571 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3572 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3573 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3574 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3575 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3576 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3577 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3578 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3579 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3580 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3581 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3582 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3583 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3584 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3585 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3586 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3587 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3588 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3589 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3590 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3591 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3592 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3593 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3594 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3595 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3596 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3597 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3598 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3599 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3600 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3601 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3602 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3603 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3604 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3605 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3606 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3607 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3608 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3609 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3610 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3611 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3612 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3613 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3614 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3615 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3616 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3617 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3618 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr, 3619 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr, 3620 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3621 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3622 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3623 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3624 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3625 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3626 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3627 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3628 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3629 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3630 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3631 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3632 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3633 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3634 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3635 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3636 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3637 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, 3638 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, 3639 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, 3640 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, 3641 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, 3642 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, 3643 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, 3644 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = 3645 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, 3646 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, 3647 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, 3648 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = 3649 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, 3650 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, 3651 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, 3652 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, 3653 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, 3654 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = 3655 &gcc_ufs_card_unipro_core_clk_src.clkr, 3656 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = 3657 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, 3658 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3659 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3660 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3661 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3662 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, 3663 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3664 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3665 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = 3666 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, 3667 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3668 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3669 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, 3670 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3671 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3672 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3673 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3674 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3675 &gcc_ufs_phy_unipro_core_clk_src.clkr, 3676 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = 3677 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, 3678 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3679 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3680 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3681 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3682 &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3683 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3684 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, 3685 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, 3686 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, 3687 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = 3688 &gcc_usb30_sec_mock_utmi_clk_src.clkr, 3689 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, 3690 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3691 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3692 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3693 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3694 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3695 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, 3696 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, 3697 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, 3698 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, 3699 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, 3700 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3701 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3702 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3703 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr, 3704 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3705 [GPLL0] = &gpll0.clkr, 3706 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3707 [GPLL7] = &gpll7.clkr, 3708 [GPLL9] = &gpll9.clkr, 3709}; 3710 3711static const struct qcom_reset_map gcc_sm8150_resets[] = { 3712 [GCC_EMAC_BCR] = { 0x6000 }, 3713 [GCC_GPU_BCR] = { 0x71000 }, 3714 [GCC_MMSS_BCR] = { 0xb000 }, 3715 [GCC_NPU_BCR] = { 0x4d000 }, 3716 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3717 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3718 [GCC_PCIE_1_BCR] = { 0x8d000 }, 3719 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3720 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3721 [GCC_PDM_BCR] = { 0x33000 }, 3722 [GCC_PRNG_BCR] = { 0x34000 }, 3723 [GCC_QSPI_BCR] = { 0x24008 }, 3724 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 3725 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3726 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3727 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3728 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3729 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3730 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3731 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3732 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3733 [GCC_SDCC2_BCR] = { 0x14000 }, 3734 [GCC_SDCC4_BCR] = { 0x16000 }, 3735 [GCC_TSIF_BCR] = { 0x36000 }, 3736 [GCC_UFS_CARD_BCR] = { 0x75000 }, 3737 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3738 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 3739 [GCC_USB30_SEC_BCR] = { 0x10000 }, 3740 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3741}; 3742 3743static struct gdsc *gcc_sm8150_gdscs[] = { 3744 [EMAC_GDSC] = &emac_gdsc, 3745 [PCIE_0_GDSC] = &pcie_0_gdsc, 3746 [PCIE_1_GDSC] = &pcie_1_gdsc, 3747 [UFS_CARD_GDSC] = &ufs_card_gdsc, 3748 [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3749 [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3750 [USB30_SEC_GDSC] = &usb30_sec_gdsc, 3751}; 3752 3753static const struct regmap_config gcc_sm8150_regmap_config = { 3754 .reg_bits = 32, 3755 .reg_stride = 4, 3756 .val_bits = 32, 3757 .max_register = 0x9c040, 3758 .fast_io = true, 3759}; 3760 3761static const struct qcom_cc_desc gcc_sm8150_desc = { 3762 .config = &gcc_sm8150_regmap_config, 3763 .clks = gcc_sm8150_clocks, 3764 .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), 3765 .resets = gcc_sm8150_resets, 3766 .num_resets = ARRAY_SIZE(gcc_sm8150_resets), 3767 .gdscs = gcc_sm8150_gdscs, 3768 .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), 3769}; 3770 3771static const struct of_device_id gcc_sm8150_match_table[] = { 3772 { .compatible = "qcom,gcc-sm8150" }, 3773 { } 3774}; 3775MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table); 3776 3777static int gcc_sm8150_probe(struct platform_device *pdev) 3778{ 3779 struct regmap *regmap; 3780 3781 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc); 3782 if (IS_ERR(regmap)) 3783 return PTR_ERR(regmap); 3784 3785 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 3786 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3787 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3788 3789 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); 3790} 3791 3792static struct platform_driver gcc_sm8150_driver = { 3793 .probe = gcc_sm8150_probe, 3794 .driver = { 3795 .name = "gcc-sm8150", 3796 .of_match_table = gcc_sm8150_match_table, 3797 }, 3798}; 3799 3800static int __init gcc_sm8150_init(void) 3801{ 3802 return platform_driver_register(&gcc_sm8150_driver); 3803} 3804subsys_initcall(gcc_sm8150_init); 3805 3806static void __exit gcc_sm8150_exit(void) 3807{ 3808 platform_driver_unregister(&gcc_sm8150_driver); 3809} 3810module_exit(gcc_sm8150_exit); 3811 3812MODULE_DESCRIPTION("QTI GCC SM8150 Driver"); 3813MODULE_LICENSE("GPL v2"); 3814