1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2015 Linaro Limited 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/clk-provider.h> 13#include <linux/regmap.h> 14#include <linux/reset-controller.h> 15 16#include <dt-bindings/clock/qcom,gcc-msm8916.h> 17#include <dt-bindings/reset/qcom,gcc-msm8916.h> 18 19#include "common.h" 20#include "clk-regmap.h" 21#include "clk-pll.h" 22#include "clk-rcg.h" 23#include "clk-branch.h" 24#include "reset.h" 25#include "gdsc.h" 26 27enum { 28 P_XO, 29 P_GPLL0, 30 P_GPLL0_AUX, 31 P_BIMC, 32 P_GPLL1, 33 P_GPLL1_AUX, 34 P_GPLL2, 35 P_GPLL2_AUX, 36 P_SLEEP_CLK, 37 P_DSI0_PHYPLL_BYTE, 38 P_DSI0_PHYPLL_DSI, 39 P_EXT_PRI_I2S, 40 P_EXT_SEC_I2S, 41 P_EXT_MCLK, 42}; 43 44static struct clk_pll gpll0 = { 45 .l_reg = 0x21004, 46 .m_reg = 0x21008, 47 .n_reg = 0x2100c, 48 .config_reg = 0x21010, 49 .mode_reg = 0x21000, 50 .status_reg = 0x2101c, 51 .status_bit = 17, 52 .clkr.hw.init = &(struct clk_init_data){ 53 .name = "gpll0", 54 .parent_data = &(const struct clk_parent_data){ 55 .fw_name = "xo", .name = "xo_board", 56 }, 57 .num_parents = 1, 58 .ops = &clk_pll_ops, 59 }, 60}; 61 62static struct clk_regmap gpll0_vote = { 63 .enable_reg = 0x45000, 64 .enable_mask = BIT(0), 65 .hw.init = &(struct clk_init_data){ 66 .name = "gpll0_vote", 67 .parent_hws = (const struct clk_hw*[]){ 68 &gpll0.clkr.hw, 69 }, 70 .num_parents = 1, 71 .ops = &clk_pll_vote_ops, 72 }, 73}; 74 75static struct clk_pll gpll1 = { 76 .l_reg = 0x20004, 77 .m_reg = 0x20008, 78 .n_reg = 0x2000c, 79 .config_reg = 0x20010, 80 .mode_reg = 0x20000, 81 .status_reg = 0x2001c, 82 .status_bit = 17, 83 .clkr.hw.init = &(struct clk_init_data){ 84 .name = "gpll1", 85 .parent_data = &(const struct clk_parent_data){ 86 .fw_name = "xo", .name = "xo_board", 87 }, 88 .num_parents = 1, 89 .ops = &clk_pll_ops, 90 }, 91}; 92 93static struct clk_regmap gpll1_vote = { 94 .enable_reg = 0x45000, 95 .enable_mask = BIT(1), 96 .hw.init = &(struct clk_init_data){ 97 .name = "gpll1_vote", 98 .parent_hws = (const struct clk_hw*[]){ 99 &gpll1.clkr.hw, 100 }, 101 .num_parents = 1, 102 .ops = &clk_pll_vote_ops, 103 }, 104}; 105 106static struct clk_pll gpll2 = { 107 .l_reg = 0x4a004, 108 .m_reg = 0x4a008, 109 .n_reg = 0x4a00c, 110 .config_reg = 0x4a010, 111 .mode_reg = 0x4a000, 112 .status_reg = 0x4a01c, 113 .status_bit = 17, 114 .clkr.hw.init = &(struct clk_init_data){ 115 .name = "gpll2", 116 .parent_data = &(const struct clk_parent_data){ 117 .fw_name = "xo", .name = "xo_board", 118 }, 119 .num_parents = 1, 120 .ops = &clk_pll_ops, 121 }, 122}; 123 124static struct clk_regmap gpll2_vote = { 125 .enable_reg = 0x45000, 126 .enable_mask = BIT(2), 127 .hw.init = &(struct clk_init_data){ 128 .name = "gpll2_vote", 129 .parent_hws = (const struct clk_hw*[]){ 130 &gpll2.clkr.hw, 131 }, 132 .num_parents = 1, 133 .ops = &clk_pll_vote_ops, 134 }, 135}; 136 137static struct clk_pll bimc_pll = { 138 .l_reg = 0x23004, 139 .m_reg = 0x23008, 140 .n_reg = 0x2300c, 141 .config_reg = 0x23010, 142 .mode_reg = 0x23000, 143 .status_reg = 0x2301c, 144 .status_bit = 17, 145 .clkr.hw.init = &(struct clk_init_data){ 146 .name = "bimc_pll", 147 .parent_data = &(const struct clk_parent_data){ 148 .fw_name = "xo", .name = "xo_board", 149 }, 150 .num_parents = 1, 151 .ops = &clk_pll_ops, 152 }, 153}; 154 155static struct clk_regmap bimc_pll_vote = { 156 .enable_reg = 0x45000, 157 .enable_mask = BIT(3), 158 .hw.init = &(struct clk_init_data){ 159 .name = "bimc_pll_vote", 160 .parent_hws = (const struct clk_hw*[]){ 161 &bimc_pll.clkr.hw, 162 }, 163 .num_parents = 1, 164 .ops = &clk_pll_vote_ops, 165 }, 166}; 167 168static const struct parent_map gcc_xo_gpll0_map[] = { 169 { P_XO, 0 }, 170 { P_GPLL0, 1 }, 171}; 172 173static const struct clk_parent_data gcc_xo_gpll0[] = { 174 { .fw_name = "xo", .name = "xo_board" }, 175 { .hw = &gpll0_vote.hw }, 176}; 177 178static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 179 { P_XO, 0 }, 180 { P_GPLL0, 1 }, 181 { P_BIMC, 2 }, 182}; 183 184static const struct clk_parent_data gcc_xo_gpll0_bimc[] = { 185 { .fw_name = "xo", .name = "xo_board" }, 186 { .hw = &gpll0_vote.hw }, 187 { .hw = &bimc_pll_vote.hw }, 188}; 189 190static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { 191 { P_XO, 0 }, 192 { P_GPLL0_AUX, 3 }, 193 { P_GPLL1, 1 }, 194 { P_GPLL2_AUX, 2 }, 195}; 196 197static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2a[] = { 198 { .fw_name = "xo", .name = "xo_board" }, 199 { .hw = &gpll0_vote.hw }, 200 { .hw = &gpll1_vote.hw }, 201 { .hw = &gpll2_vote.hw }, 202}; 203 204static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 205 { P_XO, 0 }, 206 { P_GPLL0, 1 }, 207 { P_GPLL2, 2 }, 208}; 209 210static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { 211 { .fw_name = "xo", .name = "xo_board" }, 212 { .hw = &gpll0_vote.hw }, 213 { .hw = &gpll2_vote.hw }, 214}; 215 216static const struct parent_map gcc_xo_gpll0a_map[] = { 217 { P_XO, 0 }, 218 { P_GPLL0_AUX, 2 }, 219}; 220 221static const struct clk_parent_data gcc_xo_gpll0a[] = { 222 { .fw_name = "xo", .name = "xo_board" }, 223 { .hw = &gpll0_vote.hw }, 224}; 225 226static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { 227 { P_XO, 0 }, 228 { P_GPLL0, 1 }, 229 { P_GPLL1_AUX, 2 }, 230 { P_SLEEP_CLK, 6 }, 231}; 232 233static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep[] = { 234 { .fw_name = "xo", .name = "xo_board" }, 235 { .hw = &gpll0_vote.hw }, 236 { .hw = &gpll1_vote.hw }, 237 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 238}; 239 240static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { 241 { P_XO, 0 }, 242 { P_GPLL0, 1 }, 243 { P_GPLL1_AUX, 2 }, 244}; 245 246static const struct clk_parent_data gcc_xo_gpll0_gpll1a[] = { 247 { .fw_name = "xo", .name = "xo_board" }, 248 { .hw = &gpll0_vote.hw }, 249 { .hw = &gpll1_vote.hw }, 250}; 251 252static const struct parent_map gcc_xo_dsibyte_map[] = { 253 { P_XO, 0, }, 254 { P_DSI0_PHYPLL_BYTE, 2 }, 255}; 256 257static const struct clk_parent_data gcc_xo_dsibyte[] = { 258 { .fw_name = "xo", .name = "xo_board" }, 259 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 260}; 261 262static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { 263 { P_XO, 0 }, 264 { P_GPLL0_AUX, 2 }, 265 { P_DSI0_PHYPLL_BYTE, 1 }, 266}; 267 268static const struct clk_parent_data gcc_xo_gpll0a_dsibyte[] = { 269 { .fw_name = "xo", .name = "xo_board" }, 270 { .hw = &gpll0_vote.hw }, 271 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 272}; 273 274static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { 275 { P_XO, 0 }, 276 { P_GPLL0, 1 }, 277 { P_DSI0_PHYPLL_DSI, 2 }, 278}; 279 280static const struct clk_parent_data gcc_xo_gpll0_dsiphy[] = { 281 { .fw_name = "xo", .name = "xo_board" }, 282 { .hw = &gpll0_vote.hw }, 283 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 284}; 285 286static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { 287 { P_XO, 0 }, 288 { P_GPLL0_AUX, 2 }, 289 { P_DSI0_PHYPLL_DSI, 1 }, 290}; 291 292static const struct clk_parent_data gcc_xo_gpll0a_dsiphy[] = { 293 { .fw_name = "xo", .name = "xo_board" }, 294 { .hw = &gpll0_vote.hw }, 295 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 296}; 297 298static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { 299 { P_XO, 0 }, 300 { P_GPLL0_AUX, 1 }, 301 { P_GPLL1, 3 }, 302 { P_GPLL2, 2 }, 303}; 304 305static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2[] = { 306 { .fw_name = "xo", .name = "xo_board" }, 307 { .hw = &gpll0_vote.hw }, 308 { .hw = &gpll1_vote.hw }, 309 { .hw = &gpll2_vote.hw }, 310}; 311 312static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 313 { P_XO, 0 }, 314 { P_GPLL0, 1 }, 315 { P_GPLL1, 2 }, 316 { P_SLEEP_CLK, 6 } 317}; 318 319static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = { 320 { .fw_name = "xo", .name = "xo_board" }, 321 { .hw = &gpll0_vote.hw }, 322 { .hw = &gpll1_vote.hw }, 323 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 324}; 325 326static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { 327 { P_XO, 0 }, 328 { P_GPLL1, 1 }, 329 { P_EXT_PRI_I2S, 2 }, 330 { P_EXT_MCLK, 3 }, 331 { P_SLEEP_CLK, 6 } 332}; 333 334static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep[] = { 335 { .fw_name = "xo", .name = "xo_board" }, 336 { .hw = &gpll1_vote.hw }, 337 { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" }, 338 { .fw_name = "ext_mclk", .name = "ext_mclk" }, 339 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 340}; 341 342static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { 343 { P_XO, 0 }, 344 { P_GPLL1, 1 }, 345 { P_EXT_SEC_I2S, 2 }, 346 { P_EXT_MCLK, 3 }, 347 { P_SLEEP_CLK, 6 } 348}; 349 350static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep[] = { 351 { .fw_name = "xo", .name = "xo_board" }, 352 { .hw = &gpll1_vote.hw }, 353 { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" }, 354 { .fw_name = "ext_mclk", .name = "ext_mclk" }, 355 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 356}; 357 358static const struct parent_map gcc_xo_sleep_map[] = { 359 { P_XO, 0 }, 360 { P_SLEEP_CLK, 6 } 361}; 362 363static const struct clk_parent_data gcc_xo_sleep[] = { 364 { .fw_name = "xo", .name = "xo_board" }, 365 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 366}; 367 368static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { 369 { P_XO, 0 }, 370 { P_GPLL1, 1 }, 371 { P_EXT_MCLK, 2 }, 372 { P_SLEEP_CLK, 6 } 373}; 374 375static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep[] = { 376 { .fw_name = "xo", .name = "xo_board" }, 377 { .hw = &gpll1_vote.hw }, 378 { .fw_name = "ext_mclk", .name = "ext_mclk" }, 379 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 380}; 381 382static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 383 .cmd_rcgr = 0x27000, 384 .hid_width = 5, 385 .parent_map = gcc_xo_gpll0_bimc_map, 386 .clkr.hw.init = &(struct clk_init_data){ 387 .name = "pcnoc_bfdcd_clk_src", 388 .parent_data = gcc_xo_gpll0_bimc, 389 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 390 .ops = &clk_rcg2_ops, 391 }, 392}; 393 394static struct clk_rcg2 system_noc_bfdcd_clk_src = { 395 .cmd_rcgr = 0x26004, 396 .hid_width = 5, 397 .parent_map = gcc_xo_gpll0_bimc_map, 398 .clkr.hw.init = &(struct clk_init_data){ 399 .name = "system_noc_bfdcd_clk_src", 400 .parent_data = gcc_xo_gpll0_bimc, 401 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 402 .ops = &clk_rcg2_ops, 403 }, 404}; 405 406static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { 407 F(40000000, P_GPLL0, 10, 1, 2), 408 F(80000000, P_GPLL0, 10, 0, 0), 409 { } 410}; 411 412static struct clk_rcg2 camss_ahb_clk_src = { 413 .cmd_rcgr = 0x5a000, 414 .mnd_width = 8, 415 .hid_width = 5, 416 .parent_map = gcc_xo_gpll0_map, 417 .freq_tbl = ftbl_gcc_camss_ahb_clk, 418 .clkr.hw.init = &(struct clk_init_data){ 419 .name = "camss_ahb_clk_src", 420 .parent_data = gcc_xo_gpll0, 421 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 422 .ops = &clk_rcg2_ops, 423 }, 424}; 425 426static const struct freq_tbl ftbl_apss_ahb_clk[] = { 427 F(19200000, P_XO, 1, 0, 0), 428 F(50000000, P_GPLL0, 16, 0, 0), 429 F(100000000, P_GPLL0, 8, 0, 0), 430 F(133330000, P_GPLL0, 6, 0, 0), 431 { } 432}; 433 434static struct clk_rcg2 apss_ahb_clk_src = { 435 .cmd_rcgr = 0x46000, 436 .hid_width = 5, 437 .parent_map = gcc_xo_gpll0_map, 438 .freq_tbl = ftbl_apss_ahb_clk, 439 .clkr.hw.init = &(struct clk_init_data){ 440 .name = "apss_ahb_clk_src", 441 .parent_data = gcc_xo_gpll0, 442 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 443 .ops = &clk_rcg2_ops, 444 }, 445}; 446 447static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = { 448 F(100000000, P_GPLL0, 8, 0, 0), 449 F(200000000, P_GPLL0, 4, 0, 0), 450 { } 451}; 452 453static struct clk_rcg2 csi0_clk_src = { 454 .cmd_rcgr = 0x4e020, 455 .hid_width = 5, 456 .parent_map = gcc_xo_gpll0_map, 457 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 458 .clkr.hw.init = &(struct clk_init_data){ 459 .name = "csi0_clk_src", 460 .parent_data = gcc_xo_gpll0, 461 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 462 .ops = &clk_rcg2_ops, 463 }, 464}; 465 466static struct clk_rcg2 csi1_clk_src = { 467 .cmd_rcgr = 0x4f020, 468 .hid_width = 5, 469 .parent_map = gcc_xo_gpll0_map, 470 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 471 .clkr.hw.init = &(struct clk_init_data){ 472 .name = "csi1_clk_src", 473 .parent_data = gcc_xo_gpll0, 474 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 475 .ops = &clk_rcg2_ops, 476 }, 477}; 478 479static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { 480 F(19200000, P_XO, 1, 0, 0), 481 F(50000000, P_GPLL0_AUX, 16, 0, 0), 482 F(80000000, P_GPLL0_AUX, 10, 0, 0), 483 F(100000000, P_GPLL0_AUX, 8, 0, 0), 484 F(160000000, P_GPLL0_AUX, 5, 0, 0), 485 F(177780000, P_GPLL0_AUX, 4.5, 0, 0), 486 F(200000000, P_GPLL0_AUX, 4, 0, 0), 487 F(266670000, P_GPLL0_AUX, 3, 0, 0), 488 F(294912000, P_GPLL1, 3, 0, 0), 489 F(310000000, P_GPLL2, 3, 0, 0), 490 F(400000000, P_GPLL0_AUX, 2, 0, 0), 491 { } 492}; 493 494static struct clk_rcg2 gfx3d_clk_src = { 495 .cmd_rcgr = 0x59000, 496 .hid_width = 5, 497 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map, 498 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 499 .clkr.hw.init = &(struct clk_init_data){ 500 .name = "gfx3d_clk_src", 501 .parent_data = gcc_xo_gpll0a_gpll1_gpll2a, 502 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a), 503 .ops = &clk_rcg2_ops, 504 }, 505}; 506 507static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 508 F(50000000, P_GPLL0, 16, 0, 0), 509 F(80000000, P_GPLL0, 10, 0, 0), 510 F(100000000, P_GPLL0, 8, 0, 0), 511 F(160000000, P_GPLL0, 5, 0, 0), 512 F(177780000, P_GPLL0, 4.5, 0, 0), 513 F(200000000, P_GPLL0, 4, 0, 0), 514 F(266670000, P_GPLL0, 3, 0, 0), 515 F(320000000, P_GPLL0, 2.5, 0, 0), 516 F(400000000, P_GPLL0, 2, 0, 0), 517 F(465000000, P_GPLL2, 2, 0, 0), 518 { } 519}; 520 521static struct clk_rcg2 vfe0_clk_src = { 522 .cmd_rcgr = 0x58000, 523 .hid_width = 5, 524 .parent_map = gcc_xo_gpll0_gpll2_map, 525 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 526 .clkr.hw.init = &(struct clk_init_data){ 527 .name = "vfe0_clk_src", 528 .parent_data = gcc_xo_gpll0_gpll2, 529 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 530 .ops = &clk_rcg2_ops, 531 }, 532}; 533 534static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 535 F(19200000, P_XO, 1, 0, 0), 536 F(50000000, P_GPLL0, 16, 0, 0), 537 { } 538}; 539 540static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 541 .cmd_rcgr = 0x0200c, 542 .hid_width = 5, 543 .parent_map = gcc_xo_gpll0_map, 544 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 545 .clkr.hw.init = &(struct clk_init_data){ 546 .name = "blsp1_qup1_i2c_apps_clk_src", 547 .parent_data = gcc_xo_gpll0, 548 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 549 .ops = &clk_rcg2_ops, 550 }, 551}; 552 553static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 554 F(100000, P_XO, 16, 2, 24), 555 F(250000, P_XO, 16, 5, 24), 556 F(500000, P_XO, 8, 5, 24), 557 F(960000, P_XO, 10, 1, 2), 558 F(1000000, P_XO, 4, 5, 24), 559 F(4800000, P_XO, 4, 0, 0), 560 F(9600000, P_XO, 2, 0, 0), 561 F(16000000, P_GPLL0, 10, 1, 5), 562 F(19200000, P_XO, 1, 0, 0), 563 F(25000000, P_GPLL0, 16, 1, 2), 564 F(50000000, P_GPLL0, 16, 0, 0), 565 { } 566}; 567 568static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 569 .cmd_rcgr = 0x02024, 570 .mnd_width = 8, 571 .hid_width = 5, 572 .parent_map = gcc_xo_gpll0_map, 573 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "blsp1_qup1_spi_apps_clk_src", 576 .parent_data = gcc_xo_gpll0, 577 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 578 .ops = &clk_rcg2_ops, 579 }, 580}; 581 582static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 583 .cmd_rcgr = 0x03000, 584 .hid_width = 5, 585 .parent_map = gcc_xo_gpll0_map, 586 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 587 .clkr.hw.init = &(struct clk_init_data){ 588 .name = "blsp1_qup2_i2c_apps_clk_src", 589 .parent_data = gcc_xo_gpll0, 590 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 591 .ops = &clk_rcg2_ops, 592 }, 593}; 594 595static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 596 .cmd_rcgr = 0x03014, 597 .mnd_width = 8, 598 .hid_width = 5, 599 .parent_map = gcc_xo_gpll0_map, 600 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 601 .clkr.hw.init = &(struct clk_init_data){ 602 .name = "blsp1_qup2_spi_apps_clk_src", 603 .parent_data = gcc_xo_gpll0, 604 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 605 .ops = &clk_rcg2_ops, 606 }, 607}; 608 609static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 610 .cmd_rcgr = 0x04000, 611 .hid_width = 5, 612 .parent_map = gcc_xo_gpll0_map, 613 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 614 .clkr.hw.init = &(struct clk_init_data){ 615 .name = "blsp1_qup3_i2c_apps_clk_src", 616 .parent_data = gcc_xo_gpll0, 617 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 618 .ops = &clk_rcg2_ops, 619 }, 620}; 621 622static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 623 .cmd_rcgr = 0x04024, 624 .mnd_width = 8, 625 .hid_width = 5, 626 .parent_map = gcc_xo_gpll0_map, 627 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "blsp1_qup3_spi_apps_clk_src", 630 .parent_data = gcc_xo_gpll0, 631 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 632 .ops = &clk_rcg2_ops, 633 }, 634}; 635 636static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 637 .cmd_rcgr = 0x05000, 638 .hid_width = 5, 639 .parent_map = gcc_xo_gpll0_map, 640 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "blsp1_qup4_i2c_apps_clk_src", 643 .parent_data = gcc_xo_gpll0, 644 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 645 .ops = &clk_rcg2_ops, 646 }, 647}; 648 649static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 650 .cmd_rcgr = 0x05024, 651 .mnd_width = 8, 652 .hid_width = 5, 653 .parent_map = gcc_xo_gpll0_map, 654 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 655 .clkr.hw.init = &(struct clk_init_data){ 656 .name = "blsp1_qup4_spi_apps_clk_src", 657 .parent_data = gcc_xo_gpll0, 658 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 659 .ops = &clk_rcg2_ops, 660 }, 661}; 662 663static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 664 .cmd_rcgr = 0x06000, 665 .hid_width = 5, 666 .parent_map = gcc_xo_gpll0_map, 667 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 668 .clkr.hw.init = &(struct clk_init_data){ 669 .name = "blsp1_qup5_i2c_apps_clk_src", 670 .parent_data = gcc_xo_gpll0, 671 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 672 .ops = &clk_rcg2_ops, 673 }, 674}; 675 676static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 677 .cmd_rcgr = 0x06024, 678 .mnd_width = 8, 679 .hid_width = 5, 680 .parent_map = gcc_xo_gpll0_map, 681 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 682 .clkr.hw.init = &(struct clk_init_data){ 683 .name = "blsp1_qup5_spi_apps_clk_src", 684 .parent_data = gcc_xo_gpll0, 685 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 686 .ops = &clk_rcg2_ops, 687 }, 688}; 689 690static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 691 .cmd_rcgr = 0x07000, 692 .hid_width = 5, 693 .parent_map = gcc_xo_gpll0_map, 694 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 695 .clkr.hw.init = &(struct clk_init_data){ 696 .name = "blsp1_qup6_i2c_apps_clk_src", 697 .parent_data = gcc_xo_gpll0, 698 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 699 .ops = &clk_rcg2_ops, 700 }, 701}; 702 703static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 704 .cmd_rcgr = 0x07024, 705 .mnd_width = 8, 706 .hid_width = 5, 707 .parent_map = gcc_xo_gpll0_map, 708 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 709 .clkr.hw.init = &(struct clk_init_data){ 710 .name = "blsp1_qup6_spi_apps_clk_src", 711 .parent_data = gcc_xo_gpll0, 712 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 713 .ops = &clk_rcg2_ops, 714 }, 715}; 716 717static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 718 F(3686400, P_GPLL0, 1, 72, 15625), 719 F(7372800, P_GPLL0, 1, 144, 15625), 720 F(14745600, P_GPLL0, 1, 288, 15625), 721 F(16000000, P_GPLL0, 10, 1, 5), 722 F(19200000, P_XO, 1, 0, 0), 723 F(24000000, P_GPLL0, 1, 3, 100), 724 F(25000000, P_GPLL0, 16, 1, 2), 725 F(32000000, P_GPLL0, 1, 1, 25), 726 F(40000000, P_GPLL0, 1, 1, 20), 727 F(46400000, P_GPLL0, 1, 29, 500), 728 F(48000000, P_GPLL0, 1, 3, 50), 729 F(51200000, P_GPLL0, 1, 8, 125), 730 F(56000000, P_GPLL0, 1, 7, 100), 731 F(58982400, P_GPLL0, 1, 1152, 15625), 732 F(60000000, P_GPLL0, 1, 3, 40), 733 { } 734}; 735 736static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 737 .cmd_rcgr = 0x02044, 738 .mnd_width = 16, 739 .hid_width = 5, 740 .parent_map = gcc_xo_gpll0_map, 741 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 742 .clkr.hw.init = &(struct clk_init_data){ 743 .name = "blsp1_uart1_apps_clk_src", 744 .parent_data = gcc_xo_gpll0, 745 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 746 .ops = &clk_rcg2_ops, 747 }, 748}; 749 750static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 751 .cmd_rcgr = 0x03034, 752 .mnd_width = 16, 753 .hid_width = 5, 754 .parent_map = gcc_xo_gpll0_map, 755 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "blsp1_uart2_apps_clk_src", 758 .parent_data = gcc_xo_gpll0, 759 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 760 .ops = &clk_rcg2_ops, 761 }, 762}; 763 764static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { 765 F(19200000, P_XO, 1, 0, 0), 766 { } 767}; 768 769static struct clk_rcg2 cci_clk_src = { 770 .cmd_rcgr = 0x51000, 771 .mnd_width = 8, 772 .hid_width = 5, 773 .parent_map = gcc_xo_gpll0a_map, 774 .freq_tbl = ftbl_gcc_camss_cci_clk, 775 .clkr.hw.init = &(struct clk_init_data){ 776 .name = "cci_clk_src", 777 .parent_data = gcc_xo_gpll0a, 778 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a), 779 .ops = &clk_rcg2_ops, 780 }, 781}; 782 783/* 784 * This is a frequency table for "General Purpose" clocks. 785 * These clocks can be muxed to the SoC pins and may be used by 786 * external devices. They're often used as PWM source. 787 * 788 * See comment at ftbl_gcc_gp1_3_clk. 789 */ 790static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { 791 F(10000, P_XO, 16, 1, 120), 792 F(100000, P_XO, 16, 1, 12), 793 F(500000, P_GPLL0, 16, 1, 100), 794 F(1000000, P_GPLL0, 16, 1, 50), 795 F(2500000, P_GPLL0, 16, 1, 20), 796 F(5000000, P_GPLL0, 16, 1, 10), 797 F(100000000, P_GPLL0, 8, 0, 0), 798 F(200000000, P_GPLL0, 4, 0, 0), 799 { } 800}; 801 802static struct clk_rcg2 camss_gp0_clk_src = { 803 .cmd_rcgr = 0x54000, 804 .mnd_width = 8, 805 .hid_width = 5, 806 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 807 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 808 .clkr.hw.init = &(struct clk_init_data){ 809 .name = "camss_gp0_clk_src", 810 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 811 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 812 .ops = &clk_rcg2_ops, 813 }, 814}; 815 816static struct clk_rcg2 camss_gp1_clk_src = { 817 .cmd_rcgr = 0x55000, 818 .mnd_width = 8, 819 .hid_width = 5, 820 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 821 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 822 .clkr.hw.init = &(struct clk_init_data){ 823 .name = "camss_gp1_clk_src", 824 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 825 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 826 .ops = &clk_rcg2_ops, 827 }, 828}; 829 830static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { 831 F(133330000, P_GPLL0, 6, 0, 0), 832 F(266670000, P_GPLL0, 3, 0, 0), 833 F(320000000, P_GPLL0, 2.5, 0, 0), 834 { } 835}; 836 837static struct clk_rcg2 jpeg0_clk_src = { 838 .cmd_rcgr = 0x57000, 839 .hid_width = 5, 840 .parent_map = gcc_xo_gpll0_map, 841 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 842 .clkr.hw.init = &(struct clk_init_data){ 843 .name = "jpeg0_clk_src", 844 .parent_data = gcc_xo_gpll0, 845 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 846 .ops = &clk_rcg2_ops, 847 }, 848}; 849 850static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { 851 F(9600000, P_XO, 2, 0, 0), 852 F(23880000, P_GPLL0, 1, 2, 67), 853 F(66670000, P_GPLL0, 12, 0, 0), 854 { } 855}; 856 857static struct clk_rcg2 mclk0_clk_src = { 858 .cmd_rcgr = 0x52000, 859 .mnd_width = 8, 860 .hid_width = 5, 861 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 862 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 863 .clkr.hw.init = &(struct clk_init_data){ 864 .name = "mclk0_clk_src", 865 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 866 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 867 .ops = &clk_rcg2_ops, 868 }, 869}; 870 871static struct clk_rcg2 mclk1_clk_src = { 872 .cmd_rcgr = 0x53000, 873 .mnd_width = 8, 874 .hid_width = 5, 875 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 876 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 877 .clkr.hw.init = &(struct clk_init_data){ 878 .name = "mclk1_clk_src", 879 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 880 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 881 .ops = &clk_rcg2_ops, 882 }, 883}; 884 885static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { 886 F(100000000, P_GPLL0, 8, 0, 0), 887 F(200000000, P_GPLL0, 4, 0, 0), 888 { } 889}; 890 891static struct clk_rcg2 csi0phytimer_clk_src = { 892 .cmd_rcgr = 0x4e000, 893 .hid_width = 5, 894 .parent_map = gcc_xo_gpll0_gpll1a_map, 895 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 896 .clkr.hw.init = &(struct clk_init_data){ 897 .name = "csi0phytimer_clk_src", 898 .parent_data = gcc_xo_gpll0_gpll1a, 899 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a), 900 .ops = &clk_rcg2_ops, 901 }, 902}; 903 904static struct clk_rcg2 csi1phytimer_clk_src = { 905 .cmd_rcgr = 0x4f000, 906 .hid_width = 5, 907 .parent_map = gcc_xo_gpll0_gpll1a_map, 908 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 909 .clkr.hw.init = &(struct clk_init_data){ 910 .name = "csi1phytimer_clk_src", 911 .parent_data = gcc_xo_gpll0_gpll1a, 912 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a), 913 .ops = &clk_rcg2_ops, 914 }, 915}; 916 917static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { 918 F(160000000, P_GPLL0, 5, 0, 0), 919 F(320000000, P_GPLL0, 2.5, 0, 0), 920 F(465000000, P_GPLL2, 2, 0, 0), 921 { } 922}; 923 924static struct clk_rcg2 cpp_clk_src = { 925 .cmd_rcgr = 0x58018, 926 .hid_width = 5, 927 .parent_map = gcc_xo_gpll0_gpll2_map, 928 .freq_tbl = ftbl_gcc_camss_cpp_clk, 929 .clkr.hw.init = &(struct clk_init_data){ 930 .name = "cpp_clk_src", 931 .parent_data = gcc_xo_gpll0_gpll2, 932 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 933 .ops = &clk_rcg2_ops, 934 }, 935}; 936 937static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 938 F(50000000, P_GPLL0, 16, 0, 0), 939 F(80000000, P_GPLL0, 10, 0, 0), 940 F(100000000, P_GPLL0, 8, 0, 0), 941 F(160000000, P_GPLL0, 5, 0, 0), 942 { } 943}; 944 945static struct clk_rcg2 crypto_clk_src = { 946 .cmd_rcgr = 0x16004, 947 .hid_width = 5, 948 .parent_map = gcc_xo_gpll0_map, 949 .freq_tbl = ftbl_gcc_crypto_clk, 950 .clkr.hw.init = &(struct clk_init_data){ 951 .name = "crypto_clk_src", 952 .parent_data = gcc_xo_gpll0, 953 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 954 .ops = &clk_rcg2_ops, 955 }, 956}; 957 958/* 959 * This is a frequency table for "General Purpose" clocks. 960 * These clocks can be muxed to the SoC pins and may be used by 961 * external devices. They're often used as PWM source. 962 * 963 * Please note that MND divider must be enabled for duty-cycle 964 * control to be possible. (M != N) Also since D register is configured 965 * with a value multiplied by 2, and duty cycle is calculated as 966 * (2 * D) % 2^W 967 * DutyCycle = ---------------- 968 * 2 * (N % 2^W) 969 * (where W = .mnd_width) 970 * N must be half or less than maximum value for the register. 971 * Otherwise duty-cycle control would be limited. 972 * (e.g. for 8-bit NMD N should be less than 128) 973 */ 974static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 975 F(10000, P_XO, 16, 1, 120), 976 F(100000, P_XO, 16, 1, 12), 977 F(500000, P_GPLL0, 16, 1, 100), 978 F(1000000, P_GPLL0, 16, 1, 50), 979 F(2500000, P_GPLL0, 16, 1, 20), 980 F(5000000, P_GPLL0, 16, 1, 10), 981 F(19200000, P_XO, 1, 0, 0), 982 { } 983}; 984 985static struct clk_rcg2 gp1_clk_src = { 986 .cmd_rcgr = 0x08004, 987 .mnd_width = 8, 988 .hid_width = 5, 989 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 990 .freq_tbl = ftbl_gcc_gp1_3_clk, 991 .clkr.hw.init = &(struct clk_init_data){ 992 .name = "gp1_clk_src", 993 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 994 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 995 .ops = &clk_rcg2_ops, 996 }, 997}; 998 999static struct clk_rcg2 gp2_clk_src = { 1000 .cmd_rcgr = 0x09004, 1001 .mnd_width = 8, 1002 .hid_width = 5, 1003 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 1004 .freq_tbl = ftbl_gcc_gp1_3_clk, 1005 .clkr.hw.init = &(struct clk_init_data){ 1006 .name = "gp2_clk_src", 1007 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 1008 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 1009 .ops = &clk_rcg2_ops, 1010 }, 1011}; 1012 1013static struct clk_rcg2 gp3_clk_src = { 1014 .cmd_rcgr = 0x0a004, 1015 .mnd_width = 8, 1016 .hid_width = 5, 1017 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 1018 .freq_tbl = ftbl_gcc_gp1_3_clk, 1019 .clkr.hw.init = &(struct clk_init_data){ 1020 .name = "gp3_clk_src", 1021 .parent_data = gcc_xo_gpll0_gpll1a_sleep, 1022 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 1023 .ops = &clk_rcg2_ops, 1024 }, 1025}; 1026 1027static struct clk_rcg2 byte0_clk_src = { 1028 .cmd_rcgr = 0x4d044, 1029 .hid_width = 5, 1030 .parent_map = gcc_xo_gpll0a_dsibyte_map, 1031 .clkr.hw.init = &(struct clk_init_data){ 1032 .name = "byte0_clk_src", 1033 .parent_data = gcc_xo_gpll0a_dsibyte, 1034 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte), 1035 .ops = &clk_byte2_ops, 1036 .flags = CLK_SET_RATE_PARENT, 1037 }, 1038}; 1039 1040static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = { 1041 F(19200000, P_XO, 1, 0, 0), 1042 { } 1043}; 1044 1045static struct clk_rcg2 esc0_clk_src = { 1046 .cmd_rcgr = 0x4d05c, 1047 .hid_width = 5, 1048 .parent_map = gcc_xo_dsibyte_map, 1049 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1050 .clkr.hw.init = &(struct clk_init_data){ 1051 .name = "esc0_clk_src", 1052 .parent_data = gcc_xo_dsibyte, 1053 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte), 1054 .ops = &clk_rcg2_ops, 1055 }, 1056}; 1057 1058static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { 1059 F(50000000, P_GPLL0, 16, 0, 0), 1060 F(80000000, P_GPLL0, 10, 0, 0), 1061 F(100000000, P_GPLL0, 8, 0, 0), 1062 F(160000000, P_GPLL0, 5, 0, 0), 1063 F(177780000, P_GPLL0, 4.5, 0, 0), 1064 F(200000000, P_GPLL0, 4, 0, 0), 1065 F(266670000, P_GPLL0, 3, 0, 0), 1066 F(320000000, P_GPLL0, 2.5, 0, 0), 1067 { } 1068}; 1069 1070static struct clk_rcg2 mdp_clk_src = { 1071 .cmd_rcgr = 0x4d014, 1072 .hid_width = 5, 1073 .parent_map = gcc_xo_gpll0_dsiphy_map, 1074 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1075 .clkr.hw.init = &(struct clk_init_data){ 1076 .name = "mdp_clk_src", 1077 .parent_data = gcc_xo_gpll0_dsiphy, 1078 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy), 1079 .ops = &clk_rcg2_ops, 1080 }, 1081}; 1082 1083static struct clk_rcg2 pclk0_clk_src = { 1084 .cmd_rcgr = 0x4d000, 1085 .mnd_width = 8, 1086 .hid_width = 5, 1087 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1088 .clkr.hw.init = &(struct clk_init_data){ 1089 .name = "pclk0_clk_src", 1090 .parent_data = gcc_xo_gpll0a_dsiphy, 1091 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy), 1092 .ops = &clk_pixel_ops, 1093 .flags = CLK_SET_RATE_PARENT, 1094 }, 1095}; 1096 1097static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { 1098 F(19200000, P_XO, 1, 0, 0), 1099 { } 1100}; 1101 1102static struct clk_rcg2 vsync_clk_src = { 1103 .cmd_rcgr = 0x4d02c, 1104 .hid_width = 5, 1105 .parent_map = gcc_xo_gpll0a_map, 1106 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1107 .clkr.hw.init = &(struct clk_init_data){ 1108 .name = "vsync_clk_src", 1109 .parent_data = gcc_xo_gpll0a, 1110 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a), 1111 .ops = &clk_rcg2_ops, 1112 }, 1113}; 1114 1115static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 1116 F(64000000, P_GPLL0, 12.5, 0, 0), 1117 { } 1118}; 1119 1120static struct clk_rcg2 pdm2_clk_src = { 1121 .cmd_rcgr = 0x44010, 1122 .hid_width = 5, 1123 .parent_map = gcc_xo_gpll0_map, 1124 .freq_tbl = ftbl_gcc_pdm2_clk, 1125 .clkr.hw.init = &(struct clk_init_data){ 1126 .name = "pdm2_clk_src", 1127 .parent_data = gcc_xo_gpll0, 1128 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1129 .ops = &clk_rcg2_ops, 1130 }, 1131}; 1132 1133static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 1134 F(144000, P_XO, 16, 3, 25), 1135 F(400000, P_XO, 12, 1, 4), 1136 F(20000000, P_GPLL0, 10, 1, 4), 1137 F(25000000, P_GPLL0, 16, 1, 2), 1138 F(50000000, P_GPLL0, 16, 0, 0), 1139 F(100000000, P_GPLL0, 8, 0, 0), 1140 F(177770000, P_GPLL0, 4.5, 0, 0), 1141 { } 1142}; 1143 1144static struct clk_rcg2 sdcc1_apps_clk_src = { 1145 .cmd_rcgr = 0x42004, 1146 .mnd_width = 8, 1147 .hid_width = 5, 1148 .parent_map = gcc_xo_gpll0_map, 1149 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1150 .clkr.hw.init = &(struct clk_init_data){ 1151 .name = "sdcc1_apps_clk_src", 1152 .parent_data = gcc_xo_gpll0, 1153 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1154 .ops = &clk_rcg2_floor_ops, 1155 }, 1156}; 1157 1158static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { 1159 F(144000, P_XO, 16, 3, 25), 1160 F(400000, P_XO, 12, 1, 4), 1161 F(20000000, P_GPLL0, 10, 1, 4), 1162 F(25000000, P_GPLL0, 16, 1, 2), 1163 F(50000000, P_GPLL0, 16, 0, 0), 1164 F(100000000, P_GPLL0, 8, 0, 0), 1165 F(200000000, P_GPLL0, 4, 0, 0), 1166 { } 1167}; 1168 1169static struct clk_rcg2 sdcc2_apps_clk_src = { 1170 .cmd_rcgr = 0x43004, 1171 .mnd_width = 8, 1172 .hid_width = 5, 1173 .parent_map = gcc_xo_gpll0_map, 1174 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1175 .clkr.hw.init = &(struct clk_init_data){ 1176 .name = "sdcc2_apps_clk_src", 1177 .parent_data = gcc_xo_gpll0, 1178 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1179 .ops = &clk_rcg2_floor_ops, 1180 }, 1181}; 1182 1183static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { 1184 F(155000000, P_GPLL2, 6, 0, 0), 1185 F(310000000, P_GPLL2, 3, 0, 0), 1186 F(400000000, P_GPLL0, 2, 0, 0), 1187 { } 1188}; 1189 1190static struct clk_rcg2 apss_tcu_clk_src = { 1191 .cmd_rcgr = 0x1207c, 1192 .hid_width = 5, 1193 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map, 1194 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1195 .clkr.hw.init = &(struct clk_init_data){ 1196 .name = "apss_tcu_clk_src", 1197 .parent_data = gcc_xo_gpll0a_gpll1_gpll2, 1198 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2), 1199 .ops = &clk_rcg2_ops, 1200 }, 1201}; 1202 1203static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { 1204 F(19200000, P_XO, 1, 0, 0), 1205 F(100000000, P_GPLL0, 8, 0, 0), 1206 F(200000000, P_GPLL0, 4, 0, 0), 1207 F(266500000, P_BIMC, 4, 0, 0), 1208 F(400000000, P_GPLL0, 2, 0, 0), 1209 F(533000000, P_BIMC, 2, 0, 0), 1210 { } 1211}; 1212 1213static struct clk_rcg2 bimc_gpu_clk_src = { 1214 .cmd_rcgr = 0x31028, 1215 .hid_width = 5, 1216 .parent_map = gcc_xo_gpll0_bimc_map, 1217 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1218 .clkr.hw.init = &(struct clk_init_data){ 1219 .name = "bimc_gpu_clk_src", 1220 .parent_data = gcc_xo_gpll0_bimc, 1221 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 1222 .flags = CLK_GET_RATE_NOCACHE, 1223 .ops = &clk_rcg2_ops, 1224 }, 1225}; 1226 1227static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 1228 F(80000000, P_GPLL0, 10, 0, 0), 1229 { } 1230}; 1231 1232static struct clk_rcg2 usb_hs_system_clk_src = { 1233 .cmd_rcgr = 0x41010, 1234 .hid_width = 5, 1235 .parent_map = gcc_xo_gpll0_map, 1236 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1237 .clkr.hw.init = &(struct clk_init_data){ 1238 .name = "usb_hs_system_clk_src", 1239 .parent_data = gcc_xo_gpll0, 1240 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1241 .ops = &clk_rcg2_ops, 1242 }, 1243}; 1244 1245static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { 1246 F(3200000, P_XO, 6, 0, 0), 1247 F(6400000, P_XO, 3, 0, 0), 1248 F(9600000, P_XO, 2, 0, 0), 1249 F(19200000, P_XO, 1, 0, 0), 1250 F(40000000, P_GPLL0, 10, 1, 2), 1251 F(66670000, P_GPLL0, 12, 0, 0), 1252 F(80000000, P_GPLL0, 10, 0, 0), 1253 F(100000000, P_GPLL0, 8, 0, 0), 1254 { } 1255}; 1256 1257static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { 1258 .cmd_rcgr = 0x1c010, 1259 .hid_width = 5, 1260 .mnd_width = 8, 1261 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 1262 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1263 .clkr.hw.init = &(struct clk_init_data){ 1264 .name = "ultaudio_ahbfabric_clk_src", 1265 .parent_data = gcc_xo_gpll0_gpll1_sleep, 1266 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), 1267 .ops = &clk_rcg2_ops, 1268 }, 1269}; 1270 1271static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { 1272 .halt_reg = 0x1c028, 1273 .clkr = { 1274 .enable_reg = 0x1c028, 1275 .enable_mask = BIT(0), 1276 .hw.init = &(struct clk_init_data){ 1277 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1278 .parent_hws = (const struct clk_hw*[]){ 1279 &ultaudio_ahbfabric_clk_src.clkr.hw, 1280 }, 1281 .num_parents = 1, 1282 .flags = CLK_SET_RATE_PARENT, 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286}; 1287 1288static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { 1289 .halt_reg = 0x1c024, 1290 .clkr = { 1291 .enable_reg = 0x1c024, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1295 .parent_hws = (const struct clk_hw*[]){ 1296 &ultaudio_ahbfabric_clk_src.clkr.hw, 1297 }, 1298 .num_parents = 1, 1299 .flags = CLK_SET_RATE_PARENT, 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303}; 1304 1305static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { 1306 F(128000, P_XO, 10, 1, 15), 1307 F(256000, P_XO, 5, 1, 15), 1308 F(384000, P_XO, 5, 1, 10), 1309 F(512000, P_XO, 5, 2, 15), 1310 F(576000, P_XO, 5, 3, 20), 1311 F(705600, P_GPLL1, 16, 1, 80), 1312 F(768000, P_XO, 5, 1, 5), 1313 F(800000, P_XO, 5, 5, 24), 1314 F(1024000, P_XO, 5, 4, 15), 1315 F(1152000, P_XO, 1, 3, 50), 1316 F(1411200, P_GPLL1, 16, 1, 40), 1317 F(1536000, P_XO, 1, 2, 25), 1318 F(1600000, P_XO, 12, 0, 0), 1319 F(1728000, P_XO, 5, 9, 20), 1320 F(2048000, P_XO, 5, 8, 15), 1321 F(2304000, P_XO, 5, 3, 5), 1322 F(2400000, P_XO, 8, 0, 0), 1323 F(2822400, P_GPLL1, 16, 1, 20), 1324 F(3072000, P_XO, 5, 4, 5), 1325 F(4096000, P_GPLL1, 9, 2, 49), 1326 F(4800000, P_XO, 4, 0, 0), 1327 F(5644800, P_GPLL1, 16, 1, 10), 1328 F(6144000, P_GPLL1, 7, 1, 21), 1329 F(8192000, P_GPLL1, 9, 4, 49), 1330 F(9600000, P_XO, 2, 0, 0), 1331 F(11289600, P_GPLL1, 16, 1, 5), 1332 F(12288000, P_GPLL1, 7, 2, 21), 1333 { } 1334}; 1335 1336static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { 1337 .cmd_rcgr = 0x1c054, 1338 .hid_width = 5, 1339 .mnd_width = 8, 1340 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, 1341 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1342 .clkr.hw.init = &(struct clk_init_data){ 1343 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1344 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep, 1345 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep), 1346 .ops = &clk_rcg2_ops, 1347 }, 1348}; 1349 1350static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { 1351 .halt_reg = 0x1c068, 1352 .clkr = { 1353 .enable_reg = 0x1c068, 1354 .enable_mask = BIT(0), 1355 .hw.init = &(struct clk_init_data){ 1356 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1357 .parent_hws = (const struct clk_hw*[]){ 1358 &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw, 1359 }, 1360 .num_parents = 1, 1361 .flags = CLK_SET_RATE_PARENT, 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365}; 1366 1367static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { 1368 .cmd_rcgr = 0x1c06c, 1369 .hid_width = 5, 1370 .mnd_width = 8, 1371 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, 1372 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1373 .clkr.hw.init = &(struct clk_init_data){ 1374 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1375 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep, 1376 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep), 1377 .ops = &clk_rcg2_ops, 1378 }, 1379}; 1380 1381static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { 1382 .halt_reg = 0x1c080, 1383 .clkr = { 1384 .enable_reg = 0x1c080, 1385 .enable_mask = BIT(0), 1386 .hw.init = &(struct clk_init_data){ 1387 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1388 .parent_hws = (const struct clk_hw*[]){ 1389 &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw, 1390 }, 1391 .num_parents = 1, 1392 .flags = CLK_SET_RATE_PARENT, 1393 .ops = &clk_branch2_ops, 1394 }, 1395 }, 1396}; 1397 1398static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { 1399 .cmd_rcgr = 0x1c084, 1400 .hid_width = 5, 1401 .mnd_width = 8, 1402 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1403 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1404 .clkr.hw.init = &(struct clk_init_data){ 1405 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1406 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep, 1407 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep), 1408 .ops = &clk_rcg2_ops, 1409 }, 1410}; 1411 1412static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { 1413 .halt_reg = 0x1c098, 1414 .clkr = { 1415 .enable_reg = 0x1c098, 1416 .enable_mask = BIT(0), 1417 .hw.init = &(struct clk_init_data){ 1418 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1419 .parent_hws = (const struct clk_hw*[]){ 1420 &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw, 1421 }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_branch2_ops, 1425 }, 1426 }, 1427}; 1428 1429static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { 1430 F(19200000, P_XO, 1, 0, 0), 1431 { } 1432}; 1433 1434static struct clk_rcg2 ultaudio_xo_clk_src = { 1435 .cmd_rcgr = 0x1c034, 1436 .hid_width = 5, 1437 .parent_map = gcc_xo_sleep_map, 1438 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1439 .clkr.hw.init = &(struct clk_init_data){ 1440 .name = "ultaudio_xo_clk_src", 1441 .parent_data = gcc_xo_sleep, 1442 .num_parents = ARRAY_SIZE(gcc_xo_sleep), 1443 .ops = &clk_rcg2_ops, 1444 }, 1445}; 1446 1447static struct clk_branch gcc_ultaudio_avsync_xo_clk = { 1448 .halt_reg = 0x1c04c, 1449 .clkr = { 1450 .enable_reg = 0x1c04c, 1451 .enable_mask = BIT(0), 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "gcc_ultaudio_avsync_xo_clk", 1454 .parent_hws = (const struct clk_hw*[]){ 1455 &ultaudio_xo_clk_src.clkr.hw, 1456 }, 1457 .num_parents = 1, 1458 .flags = CLK_SET_RATE_PARENT, 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462}; 1463 1464static struct clk_branch gcc_ultaudio_stc_xo_clk = { 1465 .halt_reg = 0x1c050, 1466 .clkr = { 1467 .enable_reg = 0x1c050, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(struct clk_init_data){ 1470 .name = "gcc_ultaudio_stc_xo_clk", 1471 .parent_hws = (const struct clk_hw*[]){ 1472 &ultaudio_xo_clk_src.clkr.hw, 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479}; 1480 1481static const struct freq_tbl ftbl_codec_clk[] = { 1482 F(9600000, P_XO, 2, 0, 0), 1483 F(12288000, P_XO, 1, 16, 25), 1484 F(19200000, P_XO, 1, 0, 0), 1485 F(11289600, P_EXT_MCLK, 1, 0, 0), 1486 { } 1487}; 1488 1489static struct clk_rcg2 codec_digcodec_clk_src = { 1490 .cmd_rcgr = 0x1c09c, 1491 .mnd_width = 8, 1492 .hid_width = 5, 1493 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1494 .freq_tbl = ftbl_codec_clk, 1495 .clkr.hw.init = &(struct clk_init_data){ 1496 .name = "codec_digcodec_clk_src", 1497 .parent_data = gcc_xo_gpll1_emclk_sleep, 1498 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep), 1499 .ops = &clk_rcg2_ops, 1500 }, 1501}; 1502 1503static struct clk_branch gcc_codec_digcodec_clk = { 1504 .halt_reg = 0x1c0b0, 1505 .clkr = { 1506 .enable_reg = 0x1c0b0, 1507 .enable_mask = BIT(0), 1508 .hw.init = &(struct clk_init_data){ 1509 .name = "gcc_ultaudio_codec_digcodec_clk", 1510 .parent_hws = (const struct clk_hw*[]){ 1511 &codec_digcodec_clk_src.clkr.hw, 1512 }, 1513 .num_parents = 1, 1514 .flags = CLK_SET_RATE_PARENT, 1515 .ops = &clk_branch2_ops, 1516 }, 1517 }, 1518}; 1519 1520static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { 1521 .halt_reg = 0x1c000, 1522 .clkr = { 1523 .enable_reg = 0x1c000, 1524 .enable_mask = BIT(0), 1525 .hw.init = &(struct clk_init_data){ 1526 .name = "gcc_ultaudio_pcnoc_mport_clk", 1527 .parent_hws = (const struct clk_hw*[]){ 1528 &pcnoc_bfdcd_clk_src.clkr.hw, 1529 }, 1530 .num_parents = 1, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534}; 1535 1536static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { 1537 .halt_reg = 0x1c004, 1538 .clkr = { 1539 .enable_reg = 0x1c004, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(struct clk_init_data){ 1542 .name = "gcc_ultaudio_pcnoc_sway_clk", 1543 .parent_hws = (const struct clk_hw*[]){ 1544 &pcnoc_bfdcd_clk_src.clkr.hw, 1545 }, 1546 .num_parents = 1, 1547 .ops = &clk_branch2_ops, 1548 }, 1549 }, 1550}; 1551 1552static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { 1553 F(100000000, P_GPLL0, 8, 0, 0), 1554 F(160000000, P_GPLL0, 5, 0, 0), 1555 F(228570000, P_GPLL0, 3.5, 0, 0), 1556 { } 1557}; 1558 1559static struct clk_rcg2 vcodec0_clk_src = { 1560 .cmd_rcgr = 0x4C000, 1561 .mnd_width = 8, 1562 .hid_width = 5, 1563 .parent_map = gcc_xo_gpll0_map, 1564 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1565 .clkr.hw.init = &(struct clk_init_data){ 1566 .name = "vcodec0_clk_src", 1567 .parent_data = gcc_xo_gpll0, 1568 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1569 .ops = &clk_rcg2_ops, 1570 }, 1571}; 1572 1573static struct clk_branch gcc_blsp1_ahb_clk = { 1574 .halt_reg = 0x01008, 1575 .halt_check = BRANCH_HALT_VOTED, 1576 .clkr = { 1577 .enable_reg = 0x45004, 1578 .enable_mask = BIT(10), 1579 .hw.init = &(struct clk_init_data){ 1580 .name = "gcc_blsp1_ahb_clk", 1581 .parent_hws = (const struct clk_hw*[]){ 1582 &pcnoc_bfdcd_clk_src.clkr.hw, 1583 }, 1584 .num_parents = 1, 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588}; 1589 1590static struct clk_branch gcc_blsp1_sleep_clk = { 1591 .halt_reg = 0x01004, 1592 .clkr = { 1593 .enable_reg = 0x01004, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(struct clk_init_data){ 1596 .name = "gcc_blsp1_sleep_clk", 1597 .parent_data = &(const struct clk_parent_data){ 1598 .fw_name = "sleep_clk", .name = "sleep_clk_src", 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605}; 1606 1607static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1608 .halt_reg = 0x02008, 1609 .clkr = { 1610 .enable_reg = 0x02008, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(struct clk_init_data){ 1613 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1614 .parent_hws = (const struct clk_hw*[]){ 1615 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622}; 1623 1624static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1625 .halt_reg = 0x02004, 1626 .clkr = { 1627 .enable_reg = 0x02004, 1628 .enable_mask = BIT(0), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "gcc_blsp1_qup1_spi_apps_clk", 1631 .parent_hws = (const struct clk_hw*[]){ 1632 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639}; 1640 1641static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1642 .halt_reg = 0x03010, 1643 .clkr = { 1644 .enable_reg = 0x03010, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1648 .parent_hws = (const struct clk_hw*[]){ 1649 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656}; 1657 1658static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1659 .halt_reg = 0x0300c, 1660 .clkr = { 1661 .enable_reg = 0x0300c, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(struct clk_init_data){ 1664 .name = "gcc_blsp1_qup2_spi_apps_clk", 1665 .parent_hws = (const struct clk_hw*[]){ 1666 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1667 }, 1668 .num_parents = 1, 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673}; 1674 1675static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1676 .halt_reg = 0x04020, 1677 .clkr = { 1678 .enable_reg = 0x04020, 1679 .enable_mask = BIT(0), 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1682 .parent_hws = (const struct clk_hw*[]){ 1683 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1684 }, 1685 .num_parents = 1, 1686 .flags = CLK_SET_RATE_PARENT, 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690}; 1691 1692static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1693 .halt_reg = 0x0401c, 1694 .clkr = { 1695 .enable_reg = 0x0401c, 1696 .enable_mask = BIT(0), 1697 .hw.init = &(struct clk_init_data){ 1698 .name = "gcc_blsp1_qup3_spi_apps_clk", 1699 .parent_hws = (const struct clk_hw*[]){ 1700 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1701 }, 1702 .num_parents = 1, 1703 .flags = CLK_SET_RATE_PARENT, 1704 .ops = &clk_branch2_ops, 1705 }, 1706 }, 1707}; 1708 1709static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1710 .halt_reg = 0x05020, 1711 .clkr = { 1712 .enable_reg = 0x05020, 1713 .enable_mask = BIT(0), 1714 .hw.init = &(struct clk_init_data){ 1715 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1716 .parent_hws = (const struct clk_hw*[]){ 1717 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1718 }, 1719 .num_parents = 1, 1720 .flags = CLK_SET_RATE_PARENT, 1721 .ops = &clk_branch2_ops, 1722 }, 1723 }, 1724}; 1725 1726static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1727 .halt_reg = 0x0501c, 1728 .clkr = { 1729 .enable_reg = 0x0501c, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(struct clk_init_data){ 1732 .name = "gcc_blsp1_qup4_spi_apps_clk", 1733 .parent_hws = (const struct clk_hw*[]){ 1734 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1735 }, 1736 .num_parents = 1, 1737 .flags = CLK_SET_RATE_PARENT, 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741}; 1742 1743static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1744 .halt_reg = 0x06020, 1745 .clkr = { 1746 .enable_reg = 0x06020, 1747 .enable_mask = BIT(0), 1748 .hw.init = &(struct clk_init_data){ 1749 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1750 .parent_hws = (const struct clk_hw*[]){ 1751 &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758}; 1759 1760static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1761 .halt_reg = 0x0601c, 1762 .clkr = { 1763 .enable_reg = 0x0601c, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(struct clk_init_data){ 1766 .name = "gcc_blsp1_qup5_spi_apps_clk", 1767 .parent_hws = (const struct clk_hw*[]){ 1768 &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775}; 1776 1777static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1778 .halt_reg = 0x07020, 1779 .clkr = { 1780 .enable_reg = 0x07020, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1784 .parent_hws = (const struct clk_hw*[]){ 1785 &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1786 }, 1787 .num_parents = 1, 1788 .flags = CLK_SET_RATE_PARENT, 1789 .ops = &clk_branch2_ops, 1790 }, 1791 }, 1792}; 1793 1794static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1795 .halt_reg = 0x0701c, 1796 .clkr = { 1797 .enable_reg = 0x0701c, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(struct clk_init_data){ 1800 .name = "gcc_blsp1_qup6_spi_apps_clk", 1801 .parent_hws = (const struct clk_hw*[]){ 1802 &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1803 }, 1804 .num_parents = 1, 1805 .flags = CLK_SET_RATE_PARENT, 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809}; 1810 1811static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1812 .halt_reg = 0x0203c, 1813 .clkr = { 1814 .enable_reg = 0x0203c, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "gcc_blsp1_uart1_apps_clk", 1818 .parent_hws = (const struct clk_hw*[]){ 1819 &blsp1_uart1_apps_clk_src.clkr.hw, 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826}; 1827 1828static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1829 .halt_reg = 0x0302c, 1830 .clkr = { 1831 .enable_reg = 0x0302c, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(struct clk_init_data){ 1834 .name = "gcc_blsp1_uart2_apps_clk", 1835 .parent_hws = (const struct clk_hw*[]){ 1836 &blsp1_uart2_apps_clk_src.clkr.hw, 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843}; 1844 1845static struct clk_branch gcc_boot_rom_ahb_clk = { 1846 .halt_reg = 0x1300c, 1847 .halt_check = BRANCH_HALT_VOTED, 1848 .clkr = { 1849 .enable_reg = 0x45004, 1850 .enable_mask = BIT(7), 1851 .hw.init = &(struct clk_init_data){ 1852 .name = "gcc_boot_rom_ahb_clk", 1853 .parent_hws = (const struct clk_hw*[]){ 1854 &pcnoc_bfdcd_clk_src.clkr.hw, 1855 }, 1856 .num_parents = 1, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860}; 1861 1862static struct clk_branch gcc_camss_cci_ahb_clk = { 1863 .halt_reg = 0x5101c, 1864 .clkr = { 1865 .enable_reg = 0x5101c, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "gcc_camss_cci_ahb_clk", 1869 .parent_hws = (const struct clk_hw*[]){ 1870 &camss_ahb_clk_src.clkr.hw, 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877}; 1878 1879static struct clk_branch gcc_camss_cci_clk = { 1880 .halt_reg = 0x51018, 1881 .clkr = { 1882 .enable_reg = 0x51018, 1883 .enable_mask = BIT(0), 1884 .hw.init = &(struct clk_init_data){ 1885 .name = "gcc_camss_cci_clk", 1886 .parent_hws = (const struct clk_hw*[]){ 1887 &cci_clk_src.clkr.hw, 1888 }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894}; 1895 1896static struct clk_branch gcc_camss_csi0_ahb_clk = { 1897 .halt_reg = 0x4e040, 1898 .clkr = { 1899 .enable_reg = 0x4e040, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_camss_csi0_ahb_clk", 1903 .parent_hws = (const struct clk_hw*[]){ 1904 &camss_ahb_clk_src.clkr.hw, 1905 }, 1906 .num_parents = 1, 1907 .flags = CLK_SET_RATE_PARENT, 1908 .ops = &clk_branch2_ops, 1909 }, 1910 }, 1911}; 1912 1913static struct clk_branch gcc_camss_csi0_clk = { 1914 .halt_reg = 0x4e03c, 1915 .clkr = { 1916 .enable_reg = 0x4e03c, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "gcc_camss_csi0_clk", 1920 .parent_hws = (const struct clk_hw*[]){ 1921 &csi0_clk_src.clkr.hw, 1922 }, 1923 .num_parents = 1, 1924 .flags = CLK_SET_RATE_PARENT, 1925 .ops = &clk_branch2_ops, 1926 }, 1927 }, 1928}; 1929 1930static struct clk_branch gcc_camss_csi0phy_clk = { 1931 .halt_reg = 0x4e048, 1932 .clkr = { 1933 .enable_reg = 0x4e048, 1934 .enable_mask = BIT(0), 1935 .hw.init = &(struct clk_init_data){ 1936 .name = "gcc_camss_csi0phy_clk", 1937 .parent_hws = (const struct clk_hw*[]){ 1938 &csi0_clk_src.clkr.hw, 1939 }, 1940 .num_parents = 1, 1941 .flags = CLK_SET_RATE_PARENT, 1942 .ops = &clk_branch2_ops, 1943 }, 1944 }, 1945}; 1946 1947static struct clk_branch gcc_camss_csi0pix_clk = { 1948 .halt_reg = 0x4e058, 1949 .clkr = { 1950 .enable_reg = 0x4e058, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(struct clk_init_data){ 1953 .name = "gcc_camss_csi0pix_clk", 1954 .parent_hws = (const struct clk_hw*[]){ 1955 &csi0_clk_src.clkr.hw, 1956 }, 1957 .num_parents = 1, 1958 .flags = CLK_SET_RATE_PARENT, 1959 .ops = &clk_branch2_ops, 1960 }, 1961 }, 1962}; 1963 1964static struct clk_branch gcc_camss_csi0rdi_clk = { 1965 .halt_reg = 0x4e050, 1966 .clkr = { 1967 .enable_reg = 0x4e050, 1968 .enable_mask = BIT(0), 1969 .hw.init = &(struct clk_init_data){ 1970 .name = "gcc_camss_csi0rdi_clk", 1971 .parent_hws = (const struct clk_hw*[]){ 1972 &csi0_clk_src.clkr.hw, 1973 }, 1974 .num_parents = 1, 1975 .flags = CLK_SET_RATE_PARENT, 1976 .ops = &clk_branch2_ops, 1977 }, 1978 }, 1979}; 1980 1981static struct clk_branch gcc_camss_csi1_ahb_clk = { 1982 .halt_reg = 0x4f040, 1983 .clkr = { 1984 .enable_reg = 0x4f040, 1985 .enable_mask = BIT(0), 1986 .hw.init = &(struct clk_init_data){ 1987 .name = "gcc_camss_csi1_ahb_clk", 1988 .parent_hws = (const struct clk_hw*[]){ 1989 &camss_ahb_clk_src.clkr.hw, 1990 }, 1991 .num_parents = 1, 1992 .flags = CLK_SET_RATE_PARENT, 1993 .ops = &clk_branch2_ops, 1994 }, 1995 }, 1996}; 1997 1998static struct clk_branch gcc_camss_csi1_clk = { 1999 .halt_reg = 0x4f03c, 2000 .clkr = { 2001 .enable_reg = 0x4f03c, 2002 .enable_mask = BIT(0), 2003 .hw.init = &(struct clk_init_data){ 2004 .name = "gcc_camss_csi1_clk", 2005 .parent_hws = (const struct clk_hw*[]){ 2006 &csi1_clk_src.clkr.hw, 2007 }, 2008 .num_parents = 1, 2009 .flags = CLK_SET_RATE_PARENT, 2010 .ops = &clk_branch2_ops, 2011 }, 2012 }, 2013}; 2014 2015static struct clk_branch gcc_camss_csi1phy_clk = { 2016 .halt_reg = 0x4f048, 2017 .clkr = { 2018 .enable_reg = 0x4f048, 2019 .enable_mask = BIT(0), 2020 .hw.init = &(struct clk_init_data){ 2021 .name = "gcc_camss_csi1phy_clk", 2022 .parent_hws = (const struct clk_hw*[]){ 2023 &csi1_clk_src.clkr.hw, 2024 }, 2025 .num_parents = 1, 2026 .flags = CLK_SET_RATE_PARENT, 2027 .ops = &clk_branch2_ops, 2028 }, 2029 }, 2030}; 2031 2032static struct clk_branch gcc_camss_csi1pix_clk = { 2033 .halt_reg = 0x4f058, 2034 .clkr = { 2035 .enable_reg = 0x4f058, 2036 .enable_mask = BIT(0), 2037 .hw.init = &(struct clk_init_data){ 2038 .name = "gcc_camss_csi1pix_clk", 2039 .parent_hws = (const struct clk_hw*[]){ 2040 &csi1_clk_src.clkr.hw, 2041 }, 2042 .num_parents = 1, 2043 .flags = CLK_SET_RATE_PARENT, 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047}; 2048 2049static struct clk_branch gcc_camss_csi1rdi_clk = { 2050 .halt_reg = 0x4f050, 2051 .clkr = { 2052 .enable_reg = 0x4f050, 2053 .enable_mask = BIT(0), 2054 .hw.init = &(struct clk_init_data){ 2055 .name = "gcc_camss_csi1rdi_clk", 2056 .parent_hws = (const struct clk_hw*[]){ 2057 &csi1_clk_src.clkr.hw, 2058 }, 2059 .num_parents = 1, 2060 .flags = CLK_SET_RATE_PARENT, 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064}; 2065 2066static struct clk_branch gcc_camss_csi_vfe0_clk = { 2067 .halt_reg = 0x58050, 2068 .clkr = { 2069 .enable_reg = 0x58050, 2070 .enable_mask = BIT(0), 2071 .hw.init = &(struct clk_init_data){ 2072 .name = "gcc_camss_csi_vfe0_clk", 2073 .parent_hws = (const struct clk_hw*[]){ 2074 &vfe0_clk_src.clkr.hw, 2075 }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081}; 2082 2083static struct clk_branch gcc_camss_gp0_clk = { 2084 .halt_reg = 0x54018, 2085 .clkr = { 2086 .enable_reg = 0x54018, 2087 .enable_mask = BIT(0), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "gcc_camss_gp0_clk", 2090 .parent_hws = (const struct clk_hw*[]){ 2091 &camss_gp0_clk_src.clkr.hw, 2092 }, 2093 .num_parents = 1, 2094 .flags = CLK_SET_RATE_PARENT, 2095 .ops = &clk_branch2_ops, 2096 }, 2097 }, 2098}; 2099 2100static struct clk_branch gcc_camss_gp1_clk = { 2101 .halt_reg = 0x55018, 2102 .clkr = { 2103 .enable_reg = 0x55018, 2104 .enable_mask = BIT(0), 2105 .hw.init = &(struct clk_init_data){ 2106 .name = "gcc_camss_gp1_clk", 2107 .parent_hws = (const struct clk_hw*[]){ 2108 &camss_gp1_clk_src.clkr.hw, 2109 }, 2110 .num_parents = 1, 2111 .flags = CLK_SET_RATE_PARENT, 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115}; 2116 2117static struct clk_branch gcc_camss_ispif_ahb_clk = { 2118 .halt_reg = 0x50004, 2119 .clkr = { 2120 .enable_reg = 0x50004, 2121 .enable_mask = BIT(0), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "gcc_camss_ispif_ahb_clk", 2124 .parent_hws = (const struct clk_hw*[]){ 2125 &camss_ahb_clk_src.clkr.hw, 2126 }, 2127 .num_parents = 1, 2128 .flags = CLK_SET_RATE_PARENT, 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132}; 2133 2134static struct clk_branch gcc_camss_jpeg0_clk = { 2135 .halt_reg = 0x57020, 2136 .clkr = { 2137 .enable_reg = 0x57020, 2138 .enable_mask = BIT(0), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "gcc_camss_jpeg0_clk", 2141 .parent_hws = (const struct clk_hw*[]){ 2142 &jpeg0_clk_src.clkr.hw, 2143 }, 2144 .num_parents = 1, 2145 .flags = CLK_SET_RATE_PARENT, 2146 .ops = &clk_branch2_ops, 2147 }, 2148 }, 2149}; 2150 2151static struct clk_branch gcc_camss_jpeg_ahb_clk = { 2152 .halt_reg = 0x57024, 2153 .clkr = { 2154 .enable_reg = 0x57024, 2155 .enable_mask = BIT(0), 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "gcc_camss_jpeg_ahb_clk", 2158 .parent_hws = (const struct clk_hw*[]){ 2159 &camss_ahb_clk_src.clkr.hw, 2160 }, 2161 .num_parents = 1, 2162 .flags = CLK_SET_RATE_PARENT, 2163 .ops = &clk_branch2_ops, 2164 }, 2165 }, 2166}; 2167 2168static struct clk_branch gcc_camss_jpeg_axi_clk = { 2169 .halt_reg = 0x57028, 2170 .clkr = { 2171 .enable_reg = 0x57028, 2172 .enable_mask = BIT(0), 2173 .hw.init = &(struct clk_init_data){ 2174 .name = "gcc_camss_jpeg_axi_clk", 2175 .parent_hws = (const struct clk_hw*[]){ 2176 &system_noc_bfdcd_clk_src.clkr.hw, 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183}; 2184 2185static struct clk_branch gcc_camss_mclk0_clk = { 2186 .halt_reg = 0x52018, 2187 .clkr = { 2188 .enable_reg = 0x52018, 2189 .enable_mask = BIT(0), 2190 .hw.init = &(struct clk_init_data){ 2191 .name = "gcc_camss_mclk0_clk", 2192 .parent_hws = (const struct clk_hw*[]){ 2193 &mclk0_clk_src.clkr.hw, 2194 }, 2195 .num_parents = 1, 2196 .flags = CLK_SET_RATE_PARENT, 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200}; 2201 2202static struct clk_branch gcc_camss_mclk1_clk = { 2203 .halt_reg = 0x53018, 2204 .clkr = { 2205 .enable_reg = 0x53018, 2206 .enable_mask = BIT(0), 2207 .hw.init = &(struct clk_init_data){ 2208 .name = "gcc_camss_mclk1_clk", 2209 .parent_hws = (const struct clk_hw*[]){ 2210 &mclk1_clk_src.clkr.hw, 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217}; 2218 2219static struct clk_branch gcc_camss_micro_ahb_clk = { 2220 .halt_reg = 0x5600c, 2221 .clkr = { 2222 .enable_reg = 0x5600c, 2223 .enable_mask = BIT(0), 2224 .hw.init = &(struct clk_init_data){ 2225 .name = "gcc_camss_micro_ahb_clk", 2226 .parent_hws = (const struct clk_hw*[]){ 2227 &camss_ahb_clk_src.clkr.hw, 2228 }, 2229 .num_parents = 1, 2230 .flags = CLK_SET_RATE_PARENT, 2231 .ops = &clk_branch2_ops, 2232 }, 2233 }, 2234}; 2235 2236static struct clk_branch gcc_camss_csi0phytimer_clk = { 2237 .halt_reg = 0x4e01c, 2238 .clkr = { 2239 .enable_reg = 0x4e01c, 2240 .enable_mask = BIT(0), 2241 .hw.init = &(struct clk_init_data){ 2242 .name = "gcc_camss_csi0phytimer_clk", 2243 .parent_hws = (const struct clk_hw*[]){ 2244 &csi0phytimer_clk_src.clkr.hw, 2245 }, 2246 .num_parents = 1, 2247 .flags = CLK_SET_RATE_PARENT, 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251}; 2252 2253static struct clk_branch gcc_camss_csi1phytimer_clk = { 2254 .halt_reg = 0x4f01c, 2255 .clkr = { 2256 .enable_reg = 0x4f01c, 2257 .enable_mask = BIT(0), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_camss_csi1phytimer_clk", 2260 .parent_hws = (const struct clk_hw*[]){ 2261 &csi1phytimer_clk_src.clkr.hw, 2262 }, 2263 .num_parents = 1, 2264 .flags = CLK_SET_RATE_PARENT, 2265 .ops = &clk_branch2_ops, 2266 }, 2267 }, 2268}; 2269 2270static struct clk_branch gcc_camss_ahb_clk = { 2271 .halt_reg = 0x5a014, 2272 .clkr = { 2273 .enable_reg = 0x5a014, 2274 .enable_mask = BIT(0), 2275 .hw.init = &(struct clk_init_data){ 2276 .name = "gcc_camss_ahb_clk", 2277 .parent_hws = (const struct clk_hw*[]){ 2278 &camss_ahb_clk_src.clkr.hw, 2279 }, 2280 .num_parents = 1, 2281 .flags = CLK_SET_RATE_PARENT, 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285}; 2286 2287static struct clk_branch gcc_camss_top_ahb_clk = { 2288 .halt_reg = 0x56004, 2289 .clkr = { 2290 .enable_reg = 0x56004, 2291 .enable_mask = BIT(0), 2292 .hw.init = &(struct clk_init_data){ 2293 .name = "gcc_camss_top_ahb_clk", 2294 .parent_hws = (const struct clk_hw*[]){ 2295 &pcnoc_bfdcd_clk_src.clkr.hw, 2296 }, 2297 .num_parents = 1, 2298 .flags = CLK_SET_RATE_PARENT, 2299 .ops = &clk_branch2_ops, 2300 }, 2301 }, 2302}; 2303 2304static struct clk_branch gcc_camss_cpp_ahb_clk = { 2305 .halt_reg = 0x58040, 2306 .clkr = { 2307 .enable_reg = 0x58040, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "gcc_camss_cpp_ahb_clk", 2311 .parent_hws = (const struct clk_hw*[]){ 2312 &camss_ahb_clk_src.clkr.hw, 2313 }, 2314 .num_parents = 1, 2315 .flags = CLK_SET_RATE_PARENT, 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319}; 2320 2321static struct clk_branch gcc_camss_cpp_clk = { 2322 .halt_reg = 0x5803c, 2323 .clkr = { 2324 .enable_reg = 0x5803c, 2325 .enable_mask = BIT(0), 2326 .hw.init = &(struct clk_init_data){ 2327 .name = "gcc_camss_cpp_clk", 2328 .parent_hws = (const struct clk_hw*[]){ 2329 &cpp_clk_src.clkr.hw, 2330 }, 2331 .num_parents = 1, 2332 .flags = CLK_SET_RATE_PARENT, 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336}; 2337 2338static struct clk_branch gcc_camss_vfe0_clk = { 2339 .halt_reg = 0x58038, 2340 .clkr = { 2341 .enable_reg = 0x58038, 2342 .enable_mask = BIT(0), 2343 .hw.init = &(struct clk_init_data){ 2344 .name = "gcc_camss_vfe0_clk", 2345 .parent_hws = (const struct clk_hw*[]){ 2346 &vfe0_clk_src.clkr.hw, 2347 }, 2348 .num_parents = 1, 2349 .flags = CLK_SET_RATE_PARENT, 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353}; 2354 2355static struct clk_branch gcc_camss_vfe_ahb_clk = { 2356 .halt_reg = 0x58044, 2357 .clkr = { 2358 .enable_reg = 0x58044, 2359 .enable_mask = BIT(0), 2360 .hw.init = &(struct clk_init_data){ 2361 .name = "gcc_camss_vfe_ahb_clk", 2362 .parent_hws = (const struct clk_hw*[]){ 2363 &camss_ahb_clk_src.clkr.hw, 2364 }, 2365 .num_parents = 1, 2366 .flags = CLK_SET_RATE_PARENT, 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370}; 2371 2372static struct clk_branch gcc_camss_vfe_axi_clk = { 2373 .halt_reg = 0x58048, 2374 .clkr = { 2375 .enable_reg = 0x58048, 2376 .enable_mask = BIT(0), 2377 .hw.init = &(struct clk_init_data){ 2378 .name = "gcc_camss_vfe_axi_clk", 2379 .parent_hws = (const struct clk_hw*[]){ 2380 &system_noc_bfdcd_clk_src.clkr.hw, 2381 }, 2382 .num_parents = 1, 2383 .flags = CLK_SET_RATE_PARENT, 2384 .ops = &clk_branch2_ops, 2385 }, 2386 }, 2387}; 2388 2389static struct clk_branch gcc_crypto_ahb_clk = { 2390 .halt_reg = 0x16024, 2391 .halt_check = BRANCH_HALT_VOTED, 2392 .clkr = { 2393 .enable_reg = 0x45004, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(struct clk_init_data){ 2396 .name = "gcc_crypto_ahb_clk", 2397 .parent_hws = (const struct clk_hw*[]){ 2398 &pcnoc_bfdcd_clk_src.clkr.hw, 2399 }, 2400 .num_parents = 1, 2401 .flags = CLK_SET_RATE_PARENT, 2402 .ops = &clk_branch2_ops, 2403 }, 2404 }, 2405}; 2406 2407static struct clk_branch gcc_crypto_axi_clk = { 2408 .halt_reg = 0x16020, 2409 .halt_check = BRANCH_HALT_VOTED, 2410 .clkr = { 2411 .enable_reg = 0x45004, 2412 .enable_mask = BIT(1), 2413 .hw.init = &(struct clk_init_data){ 2414 .name = "gcc_crypto_axi_clk", 2415 .parent_hws = (const struct clk_hw*[]){ 2416 &pcnoc_bfdcd_clk_src.clkr.hw, 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT, 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423}; 2424 2425static struct clk_branch gcc_crypto_clk = { 2426 .halt_reg = 0x1601c, 2427 .halt_check = BRANCH_HALT_VOTED, 2428 .clkr = { 2429 .enable_reg = 0x45004, 2430 .enable_mask = BIT(2), 2431 .hw.init = &(struct clk_init_data){ 2432 .name = "gcc_crypto_clk", 2433 .parent_hws = (const struct clk_hw*[]){ 2434 &crypto_clk_src.clkr.hw, 2435 }, 2436 .num_parents = 1, 2437 .flags = CLK_SET_RATE_PARENT, 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441}; 2442 2443static struct clk_branch gcc_oxili_gmem_clk = { 2444 .halt_reg = 0x59024, 2445 .clkr = { 2446 .enable_reg = 0x59024, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(struct clk_init_data){ 2449 .name = "gcc_oxili_gmem_clk", 2450 .parent_hws = (const struct clk_hw*[]){ 2451 &gfx3d_clk_src.clkr.hw, 2452 }, 2453 .num_parents = 1, 2454 .flags = CLK_SET_RATE_PARENT, 2455 .ops = &clk_branch2_ops, 2456 }, 2457 }, 2458}; 2459 2460static struct clk_branch gcc_gp1_clk = { 2461 .halt_reg = 0x08000, 2462 .clkr = { 2463 .enable_reg = 0x08000, 2464 .enable_mask = BIT(0), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "gcc_gp1_clk", 2467 .parent_hws = (const struct clk_hw*[]){ 2468 &gp1_clk_src.clkr.hw, 2469 }, 2470 .num_parents = 1, 2471 .flags = CLK_SET_RATE_PARENT, 2472 .ops = &clk_branch2_ops, 2473 }, 2474 }, 2475}; 2476 2477static struct clk_branch gcc_gp2_clk = { 2478 .halt_reg = 0x09000, 2479 .clkr = { 2480 .enable_reg = 0x09000, 2481 .enable_mask = BIT(0), 2482 .hw.init = &(struct clk_init_data){ 2483 .name = "gcc_gp2_clk", 2484 .parent_hws = (const struct clk_hw*[]){ 2485 &gp2_clk_src.clkr.hw, 2486 }, 2487 .num_parents = 1, 2488 .flags = CLK_SET_RATE_PARENT, 2489 .ops = &clk_branch2_ops, 2490 }, 2491 }, 2492}; 2493 2494static struct clk_branch gcc_gp3_clk = { 2495 .halt_reg = 0x0a000, 2496 .clkr = { 2497 .enable_reg = 0x0a000, 2498 .enable_mask = BIT(0), 2499 .hw.init = &(struct clk_init_data){ 2500 .name = "gcc_gp3_clk", 2501 .parent_hws = (const struct clk_hw*[]){ 2502 &gp3_clk_src.clkr.hw, 2503 }, 2504 .num_parents = 1, 2505 .flags = CLK_SET_RATE_PARENT, 2506 .ops = &clk_branch2_ops, 2507 }, 2508 }, 2509}; 2510 2511static struct clk_branch gcc_mdss_ahb_clk = { 2512 .halt_reg = 0x4d07c, 2513 .clkr = { 2514 .enable_reg = 0x4d07c, 2515 .enable_mask = BIT(0), 2516 .hw.init = &(struct clk_init_data){ 2517 .name = "gcc_mdss_ahb_clk", 2518 .parent_hws = (const struct clk_hw*[]){ 2519 &pcnoc_bfdcd_clk_src.clkr.hw, 2520 }, 2521 .num_parents = 1, 2522 .flags = CLK_SET_RATE_PARENT, 2523 .ops = &clk_branch2_ops, 2524 }, 2525 }, 2526}; 2527 2528static struct clk_branch gcc_mdss_axi_clk = { 2529 .halt_reg = 0x4d080, 2530 .clkr = { 2531 .enable_reg = 0x4d080, 2532 .enable_mask = BIT(0), 2533 .hw.init = &(struct clk_init_data){ 2534 .name = "gcc_mdss_axi_clk", 2535 .parent_hws = (const struct clk_hw*[]){ 2536 &system_noc_bfdcd_clk_src.clkr.hw, 2537 }, 2538 .num_parents = 1, 2539 .flags = CLK_SET_RATE_PARENT, 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543}; 2544 2545static struct clk_branch gcc_mdss_byte0_clk = { 2546 .halt_reg = 0x4d094, 2547 .clkr = { 2548 .enable_reg = 0x4d094, 2549 .enable_mask = BIT(0), 2550 .hw.init = &(struct clk_init_data){ 2551 .name = "gcc_mdss_byte0_clk", 2552 .parent_hws = (const struct clk_hw*[]){ 2553 &byte0_clk_src.clkr.hw, 2554 }, 2555 .num_parents = 1, 2556 .flags = CLK_SET_RATE_PARENT, 2557 .ops = &clk_branch2_ops, 2558 }, 2559 }, 2560}; 2561 2562static struct clk_branch gcc_mdss_esc0_clk = { 2563 .halt_reg = 0x4d098, 2564 .clkr = { 2565 .enable_reg = 0x4d098, 2566 .enable_mask = BIT(0), 2567 .hw.init = &(struct clk_init_data){ 2568 .name = "gcc_mdss_esc0_clk", 2569 .parent_hws = (const struct clk_hw*[]){ 2570 &esc0_clk_src.clkr.hw, 2571 }, 2572 .num_parents = 1, 2573 .flags = CLK_SET_RATE_PARENT, 2574 .ops = &clk_branch2_ops, 2575 }, 2576 }, 2577}; 2578 2579static struct clk_branch gcc_mdss_mdp_clk = { 2580 .halt_reg = 0x4D088, 2581 .clkr = { 2582 .enable_reg = 0x4D088, 2583 .enable_mask = BIT(0), 2584 .hw.init = &(struct clk_init_data){ 2585 .name = "gcc_mdss_mdp_clk", 2586 .parent_hws = (const struct clk_hw*[]){ 2587 &mdp_clk_src.clkr.hw, 2588 }, 2589 .num_parents = 1, 2590 .flags = CLK_SET_RATE_PARENT, 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594}; 2595 2596static struct clk_branch gcc_mdss_pclk0_clk = { 2597 .halt_reg = 0x4d084, 2598 .clkr = { 2599 .enable_reg = 0x4d084, 2600 .enable_mask = BIT(0), 2601 .hw.init = &(struct clk_init_data){ 2602 .name = "gcc_mdss_pclk0_clk", 2603 .parent_hws = (const struct clk_hw*[]){ 2604 &pclk0_clk_src.clkr.hw, 2605 }, 2606 .num_parents = 1, 2607 .flags = CLK_SET_RATE_PARENT, 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611}; 2612 2613static struct clk_branch gcc_mdss_vsync_clk = { 2614 .halt_reg = 0x4d090, 2615 .clkr = { 2616 .enable_reg = 0x4d090, 2617 .enable_mask = BIT(0), 2618 .hw.init = &(struct clk_init_data){ 2619 .name = "gcc_mdss_vsync_clk", 2620 .parent_hws = (const struct clk_hw*[]){ 2621 &vsync_clk_src.clkr.hw, 2622 }, 2623 .num_parents = 1, 2624 .flags = CLK_SET_RATE_PARENT, 2625 .ops = &clk_branch2_ops, 2626 }, 2627 }, 2628}; 2629 2630static struct clk_branch gcc_mss_cfg_ahb_clk = { 2631 .halt_reg = 0x49000, 2632 .clkr = { 2633 .enable_reg = 0x49000, 2634 .enable_mask = BIT(0), 2635 .hw.init = &(struct clk_init_data){ 2636 .name = "gcc_mss_cfg_ahb_clk", 2637 .parent_hws = (const struct clk_hw*[]){ 2638 &pcnoc_bfdcd_clk_src.clkr.hw, 2639 }, 2640 .num_parents = 1, 2641 .flags = CLK_SET_RATE_PARENT, 2642 .ops = &clk_branch2_ops, 2643 }, 2644 }, 2645}; 2646 2647static struct clk_branch gcc_oxili_ahb_clk = { 2648 .halt_reg = 0x59028, 2649 .clkr = { 2650 .enable_reg = 0x59028, 2651 .enable_mask = BIT(0), 2652 .hw.init = &(struct clk_init_data){ 2653 .name = "gcc_oxili_ahb_clk", 2654 .parent_hws = (const struct clk_hw*[]){ 2655 &pcnoc_bfdcd_clk_src.clkr.hw, 2656 }, 2657 .num_parents = 1, 2658 .flags = CLK_SET_RATE_PARENT, 2659 .ops = &clk_branch2_ops, 2660 }, 2661 }, 2662}; 2663 2664static struct clk_branch gcc_oxili_gfx3d_clk = { 2665 .halt_reg = 0x59020, 2666 .clkr = { 2667 .enable_reg = 0x59020, 2668 .enable_mask = BIT(0), 2669 .hw.init = &(struct clk_init_data){ 2670 .name = "gcc_oxili_gfx3d_clk", 2671 .parent_hws = (const struct clk_hw*[]){ 2672 &gfx3d_clk_src.clkr.hw, 2673 }, 2674 .num_parents = 1, 2675 .flags = CLK_SET_RATE_PARENT, 2676 .ops = &clk_branch2_ops, 2677 }, 2678 }, 2679}; 2680 2681static struct clk_branch gcc_pdm2_clk = { 2682 .halt_reg = 0x4400c, 2683 .clkr = { 2684 .enable_reg = 0x4400c, 2685 .enable_mask = BIT(0), 2686 .hw.init = &(struct clk_init_data){ 2687 .name = "gcc_pdm2_clk", 2688 .parent_hws = (const struct clk_hw*[]){ 2689 &pdm2_clk_src.clkr.hw, 2690 }, 2691 .num_parents = 1, 2692 .flags = CLK_SET_RATE_PARENT, 2693 .ops = &clk_branch2_ops, 2694 }, 2695 }, 2696}; 2697 2698static struct clk_branch gcc_pdm_ahb_clk = { 2699 .halt_reg = 0x44004, 2700 .clkr = { 2701 .enable_reg = 0x44004, 2702 .enable_mask = BIT(0), 2703 .hw.init = &(struct clk_init_data){ 2704 .name = "gcc_pdm_ahb_clk", 2705 .parent_hws = (const struct clk_hw*[]){ 2706 &pcnoc_bfdcd_clk_src.clkr.hw, 2707 }, 2708 .num_parents = 1, 2709 .flags = CLK_SET_RATE_PARENT, 2710 .ops = &clk_branch2_ops, 2711 }, 2712 }, 2713}; 2714 2715static struct clk_branch gcc_prng_ahb_clk = { 2716 .halt_reg = 0x13004, 2717 .halt_check = BRANCH_HALT_VOTED, 2718 .clkr = { 2719 .enable_reg = 0x45004, 2720 .enable_mask = BIT(8), 2721 .hw.init = &(struct clk_init_data){ 2722 .name = "gcc_prng_ahb_clk", 2723 .parent_hws = (const struct clk_hw*[]){ 2724 &pcnoc_bfdcd_clk_src.clkr.hw, 2725 }, 2726 .num_parents = 1, 2727 .ops = &clk_branch2_ops, 2728 }, 2729 }, 2730}; 2731 2732static struct clk_branch gcc_sdcc1_ahb_clk = { 2733 .halt_reg = 0x4201c, 2734 .clkr = { 2735 .enable_reg = 0x4201c, 2736 .enable_mask = BIT(0), 2737 .hw.init = &(struct clk_init_data){ 2738 .name = "gcc_sdcc1_ahb_clk", 2739 .parent_hws = (const struct clk_hw*[]){ 2740 &pcnoc_bfdcd_clk_src.clkr.hw, 2741 }, 2742 .num_parents = 1, 2743 .flags = CLK_SET_RATE_PARENT, 2744 .ops = &clk_branch2_ops, 2745 }, 2746 }, 2747}; 2748 2749static struct clk_branch gcc_sdcc1_apps_clk = { 2750 .halt_reg = 0x42018, 2751 .clkr = { 2752 .enable_reg = 0x42018, 2753 .enable_mask = BIT(0), 2754 .hw.init = &(struct clk_init_data){ 2755 .name = "gcc_sdcc1_apps_clk", 2756 .parent_hws = (const struct clk_hw*[]){ 2757 &sdcc1_apps_clk_src.clkr.hw, 2758 }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764}; 2765 2766static struct clk_branch gcc_sdcc2_ahb_clk = { 2767 .halt_reg = 0x4301c, 2768 .clkr = { 2769 .enable_reg = 0x4301c, 2770 .enable_mask = BIT(0), 2771 .hw.init = &(struct clk_init_data){ 2772 .name = "gcc_sdcc2_ahb_clk", 2773 .parent_hws = (const struct clk_hw*[]){ 2774 &pcnoc_bfdcd_clk_src.clkr.hw, 2775 }, 2776 .num_parents = 1, 2777 .flags = CLK_SET_RATE_PARENT, 2778 .ops = &clk_branch2_ops, 2779 }, 2780 }, 2781}; 2782 2783static struct clk_branch gcc_sdcc2_apps_clk = { 2784 .halt_reg = 0x43018, 2785 .clkr = { 2786 .enable_reg = 0x43018, 2787 .enable_mask = BIT(0), 2788 .hw.init = &(struct clk_init_data){ 2789 .name = "gcc_sdcc2_apps_clk", 2790 .parent_hws = (const struct clk_hw*[]){ 2791 &sdcc2_apps_clk_src.clkr.hw, 2792 }, 2793 .num_parents = 1, 2794 .flags = CLK_SET_RATE_PARENT, 2795 .ops = &clk_branch2_ops, 2796 }, 2797 }, 2798}; 2799 2800static struct clk_rcg2 bimc_ddr_clk_src = { 2801 .cmd_rcgr = 0x32004, 2802 .hid_width = 5, 2803 .parent_map = gcc_xo_gpll0_bimc_map, 2804 .clkr.hw.init = &(struct clk_init_data){ 2805 .name = "bimc_ddr_clk_src", 2806 .parent_data = gcc_xo_gpll0_bimc, 2807 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 2808 .ops = &clk_rcg2_ops, 2809 .flags = CLK_GET_RATE_NOCACHE, 2810 }, 2811}; 2812 2813static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 2814 .halt_reg = 0x49004, 2815 .clkr = { 2816 .enable_reg = 0x49004, 2817 .enable_mask = BIT(0), 2818 .hw.init = &(struct clk_init_data){ 2819 .name = "gcc_mss_q6_bimc_axi_clk", 2820 .parent_hws = (const struct clk_hw*[]){ 2821 &bimc_ddr_clk_src.clkr.hw, 2822 }, 2823 .num_parents = 1, 2824 .flags = CLK_SET_RATE_PARENT, 2825 .ops = &clk_branch2_ops, 2826 }, 2827 }, 2828}; 2829 2830static struct clk_branch gcc_apss_tcu_clk = { 2831 .halt_reg = 0x12018, 2832 .clkr = { 2833 .enable_reg = 0x4500c, 2834 .enable_mask = BIT(1), 2835 .hw.init = &(struct clk_init_data){ 2836 .name = "gcc_apss_tcu_clk", 2837 .parent_hws = (const struct clk_hw*[]){ 2838 &bimc_ddr_clk_src.clkr.hw, 2839 }, 2840 .num_parents = 1, 2841 .ops = &clk_branch2_ops, 2842 }, 2843 }, 2844}; 2845 2846static struct clk_branch gcc_gfx_tcu_clk = { 2847 .halt_reg = 0x12020, 2848 .clkr = { 2849 .enable_reg = 0x4500c, 2850 .enable_mask = BIT(2), 2851 .hw.init = &(struct clk_init_data){ 2852 .name = "gcc_gfx_tcu_clk", 2853 .parent_hws = (const struct clk_hw*[]){ 2854 &bimc_ddr_clk_src.clkr.hw, 2855 }, 2856 .num_parents = 1, 2857 .ops = &clk_branch2_ops, 2858 }, 2859 }, 2860}; 2861 2862static struct clk_branch gcc_gtcu_ahb_clk = { 2863 .halt_reg = 0x12044, 2864 .clkr = { 2865 .enable_reg = 0x4500c, 2866 .enable_mask = BIT(13), 2867 .hw.init = &(struct clk_init_data){ 2868 .name = "gcc_gtcu_ahb_clk", 2869 .parent_hws = (const struct clk_hw*[]){ 2870 &pcnoc_bfdcd_clk_src.clkr.hw, 2871 }, 2872 .num_parents = 1, 2873 .flags = CLK_SET_RATE_PARENT, 2874 .ops = &clk_branch2_ops, 2875 }, 2876 }, 2877}; 2878 2879static struct clk_branch gcc_bimc_gfx_clk = { 2880 .halt_reg = 0x31024, 2881 .clkr = { 2882 .enable_reg = 0x31024, 2883 .enable_mask = BIT(0), 2884 .hw.init = &(struct clk_init_data){ 2885 .name = "gcc_bimc_gfx_clk", 2886 .parent_hws = (const struct clk_hw*[]){ 2887 &bimc_gpu_clk_src.clkr.hw, 2888 }, 2889 .num_parents = 1, 2890 .flags = CLK_SET_RATE_PARENT, 2891 .ops = &clk_branch2_ops, 2892 }, 2893 }, 2894}; 2895 2896static struct clk_branch gcc_bimc_gpu_clk = { 2897 .halt_reg = 0x31040, 2898 .clkr = { 2899 .enable_reg = 0x31040, 2900 .enable_mask = BIT(0), 2901 .hw.init = &(struct clk_init_data){ 2902 .name = "gcc_bimc_gpu_clk", 2903 .parent_hws = (const struct clk_hw*[]){ 2904 &bimc_gpu_clk_src.clkr.hw, 2905 }, 2906 .num_parents = 1, 2907 .flags = CLK_SET_RATE_PARENT, 2908 .ops = &clk_branch2_ops, 2909 }, 2910 }, 2911}; 2912 2913static struct clk_branch gcc_jpeg_tbu_clk = { 2914 .halt_reg = 0x12034, 2915 .clkr = { 2916 .enable_reg = 0x4500c, 2917 .enable_mask = BIT(10), 2918 .hw.init = &(struct clk_init_data){ 2919 .name = "gcc_jpeg_tbu_clk", 2920 .parent_hws = (const struct clk_hw*[]){ 2921 &system_noc_bfdcd_clk_src.clkr.hw, 2922 }, 2923 .num_parents = 1, 2924 .flags = CLK_SET_RATE_PARENT, 2925 .ops = &clk_branch2_ops, 2926 }, 2927 }, 2928}; 2929 2930static struct clk_branch gcc_mdp_tbu_clk = { 2931 .halt_reg = 0x1201c, 2932 .clkr = { 2933 .enable_reg = 0x4500c, 2934 .enable_mask = BIT(4), 2935 .hw.init = &(struct clk_init_data){ 2936 .name = "gcc_mdp_tbu_clk", 2937 .parent_hws = (const struct clk_hw*[]){ 2938 &system_noc_bfdcd_clk_src.clkr.hw, 2939 }, 2940 .num_parents = 1, 2941 .flags = CLK_SET_RATE_PARENT, 2942 .ops = &clk_branch2_ops, 2943 }, 2944 }, 2945}; 2946 2947static struct clk_branch gcc_smmu_cfg_clk = { 2948 .halt_reg = 0x12038, 2949 .clkr = { 2950 .enable_reg = 0x4500c, 2951 .enable_mask = BIT(12), 2952 .hw.init = &(struct clk_init_data){ 2953 .name = "gcc_smmu_cfg_clk", 2954 .parent_hws = (const struct clk_hw*[]){ 2955 &pcnoc_bfdcd_clk_src.clkr.hw, 2956 }, 2957 .num_parents = 1, 2958 .flags = CLK_SET_RATE_PARENT, 2959 .ops = &clk_branch2_ops, 2960 }, 2961 }, 2962}; 2963 2964static struct clk_branch gcc_venus_tbu_clk = { 2965 .halt_reg = 0x12014, 2966 .clkr = { 2967 .enable_reg = 0x4500c, 2968 .enable_mask = BIT(5), 2969 .hw.init = &(struct clk_init_data){ 2970 .name = "gcc_venus_tbu_clk", 2971 .parent_hws = (const struct clk_hw*[]){ 2972 &system_noc_bfdcd_clk_src.clkr.hw, 2973 }, 2974 .num_parents = 1, 2975 .flags = CLK_SET_RATE_PARENT, 2976 .ops = &clk_branch2_ops, 2977 }, 2978 }, 2979}; 2980 2981static struct clk_branch gcc_vfe_tbu_clk = { 2982 .halt_reg = 0x1203c, 2983 .clkr = { 2984 .enable_reg = 0x4500c, 2985 .enable_mask = BIT(9), 2986 .hw.init = &(struct clk_init_data){ 2987 .name = "gcc_vfe_tbu_clk", 2988 .parent_hws = (const struct clk_hw*[]){ 2989 &system_noc_bfdcd_clk_src.clkr.hw, 2990 }, 2991 .num_parents = 1, 2992 .flags = CLK_SET_RATE_PARENT, 2993 .ops = &clk_branch2_ops, 2994 }, 2995 }, 2996}; 2997 2998static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2999 .halt_reg = 0x4102c, 3000 .clkr = { 3001 .enable_reg = 0x4102c, 3002 .enable_mask = BIT(0), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_usb2a_phy_sleep_clk", 3005 .parent_data = &(const struct clk_parent_data){ 3006 .fw_name = "sleep_clk", .name = "sleep_clk_src", 3007 }, 3008 .num_parents = 1, 3009 .flags = CLK_SET_RATE_PARENT, 3010 .ops = &clk_branch2_ops, 3011 }, 3012 }, 3013}; 3014 3015static struct clk_branch gcc_usb_hs_ahb_clk = { 3016 .halt_reg = 0x41008, 3017 .clkr = { 3018 .enable_reg = 0x41008, 3019 .enable_mask = BIT(0), 3020 .hw.init = &(struct clk_init_data){ 3021 .name = "gcc_usb_hs_ahb_clk", 3022 .parent_hws = (const struct clk_hw*[]){ 3023 &pcnoc_bfdcd_clk_src.clkr.hw, 3024 }, 3025 .num_parents = 1, 3026 .flags = CLK_SET_RATE_PARENT, 3027 .ops = &clk_branch2_ops, 3028 }, 3029 }, 3030}; 3031 3032static struct clk_branch gcc_usb_hs_system_clk = { 3033 .halt_reg = 0x41004, 3034 .clkr = { 3035 .enable_reg = 0x41004, 3036 .enable_mask = BIT(0), 3037 .hw.init = &(struct clk_init_data){ 3038 .name = "gcc_usb_hs_system_clk", 3039 .parent_hws = (const struct clk_hw*[]){ 3040 &usb_hs_system_clk_src.clkr.hw, 3041 }, 3042 .num_parents = 1, 3043 .flags = CLK_SET_RATE_PARENT, 3044 .ops = &clk_branch2_ops, 3045 }, 3046 }, 3047}; 3048 3049static struct clk_branch gcc_venus0_ahb_clk = { 3050 .halt_reg = 0x4c020, 3051 .clkr = { 3052 .enable_reg = 0x4c020, 3053 .enable_mask = BIT(0), 3054 .hw.init = &(struct clk_init_data){ 3055 .name = "gcc_venus0_ahb_clk", 3056 .parent_hws = (const struct clk_hw*[]){ 3057 &pcnoc_bfdcd_clk_src.clkr.hw, 3058 }, 3059 .num_parents = 1, 3060 .flags = CLK_SET_RATE_PARENT, 3061 .ops = &clk_branch2_ops, 3062 }, 3063 }, 3064}; 3065 3066static struct clk_branch gcc_venus0_axi_clk = { 3067 .halt_reg = 0x4c024, 3068 .clkr = { 3069 .enable_reg = 0x4c024, 3070 .enable_mask = BIT(0), 3071 .hw.init = &(struct clk_init_data){ 3072 .name = "gcc_venus0_axi_clk", 3073 .parent_hws = (const struct clk_hw*[]){ 3074 &system_noc_bfdcd_clk_src.clkr.hw, 3075 }, 3076 .num_parents = 1, 3077 .flags = CLK_SET_RATE_PARENT, 3078 .ops = &clk_branch2_ops, 3079 }, 3080 }, 3081}; 3082 3083static struct clk_branch gcc_venus0_vcodec0_clk = { 3084 .halt_reg = 0x4c01c, 3085 .clkr = { 3086 .enable_reg = 0x4c01c, 3087 .enable_mask = BIT(0), 3088 .hw.init = &(struct clk_init_data){ 3089 .name = "gcc_venus0_vcodec0_clk", 3090 .parent_hws = (const struct clk_hw*[]){ 3091 &vcodec0_clk_src.clkr.hw, 3092 }, 3093 .num_parents = 1, 3094 .flags = CLK_SET_RATE_PARENT, 3095 .ops = &clk_branch2_ops, 3096 }, 3097 }, 3098}; 3099 3100static struct gdsc venus_gdsc = { 3101 .gdscr = 0x4c018, 3102 .pd = { 3103 .name = "venus", 3104 }, 3105 .pwrsts = PWRSTS_OFF_ON, 3106}; 3107 3108static struct gdsc mdss_gdsc = { 3109 .gdscr = 0x4d078, 3110 .pd = { 3111 .name = "mdss", 3112 }, 3113 .pwrsts = PWRSTS_OFF_ON, 3114}; 3115 3116static struct gdsc jpeg_gdsc = { 3117 .gdscr = 0x5701c, 3118 .pd = { 3119 .name = "jpeg", 3120 }, 3121 .pwrsts = PWRSTS_OFF_ON, 3122}; 3123 3124static struct gdsc vfe_gdsc = { 3125 .gdscr = 0x58034, 3126 .pd = { 3127 .name = "vfe", 3128 }, 3129 .pwrsts = PWRSTS_OFF_ON, 3130}; 3131 3132static struct gdsc oxili_gdsc = { 3133 .gdscr = 0x5901c, 3134 .pd = { 3135 .name = "oxili", 3136 }, 3137 .pwrsts = PWRSTS_OFF_ON, 3138}; 3139 3140static struct clk_regmap *gcc_msm8916_clocks[] = { 3141 [GPLL0] = &gpll0.clkr, 3142 [GPLL0_VOTE] = &gpll0_vote, 3143 [BIMC_PLL] = &bimc_pll.clkr, 3144 [BIMC_PLL_VOTE] = &bimc_pll_vote, 3145 [GPLL1] = &gpll1.clkr, 3146 [GPLL1_VOTE] = &gpll1_vote, 3147 [GPLL2] = &gpll2.clkr, 3148 [GPLL2_VOTE] = &gpll2_vote, 3149 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3150 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3151 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, 3152 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3153 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3154 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3155 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3156 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3157 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3158 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3159 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3160 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3161 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3162 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3163 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3164 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3165 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3166 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3167 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3168 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3169 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3170 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3171 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3172 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3173 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3174 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3175 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3176 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3177 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3178 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3179 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3180 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3181 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3182 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3183 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3184 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3185 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3186 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3187 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3188 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3189 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3190 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3191 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3192 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, 3193 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 3194 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3195 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3196 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3197 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3198 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3199 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3200 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3201 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3202 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3203 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3204 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3205 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3206 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3207 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3208 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3209 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3210 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3211 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3212 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, 3213 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, 3214 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 3215 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 3216 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 3217 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 3218 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 3219 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 3220 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 3221 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 3222 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 3223 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 3224 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 3225 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 3226 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 3227 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 3228 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, 3229 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, 3230 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, 3231 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3232 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3233 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, 3234 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3235 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3236 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 3237 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3238 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, 3239 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, 3240 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 3241 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 3242 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 3243 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3244 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3245 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3246 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, 3247 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3248 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3249 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3250 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 3251 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 3252 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 3253 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 3254 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 3255 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 3256 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 3257 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3258 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 3259 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 3260 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3261 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3262 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3263 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3264 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3265 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3266 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3267 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 3268 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, 3269 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 3270 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 3271 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 3272 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 3273 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 3274 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 3275 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 3276 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 3277 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 3278 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 3279 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 3280 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 3281 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 3282 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 3283 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3284 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 3285 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, 3286 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, 3287 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, 3288 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, 3289 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, 3290 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, 3291 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, 3292 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, 3293 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, 3294 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, 3295 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, 3296 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, 3297 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, 3298 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, 3299 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, 3300 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, 3301 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 3302}; 3303 3304static struct gdsc *gcc_msm8916_gdscs[] = { 3305 [VENUS_GDSC] = &venus_gdsc, 3306 [MDSS_GDSC] = &mdss_gdsc, 3307 [JPEG_GDSC] = &jpeg_gdsc, 3308 [VFE_GDSC] = &vfe_gdsc, 3309 [OXILI_GDSC] = &oxili_gdsc, 3310}; 3311 3312static const struct qcom_reset_map gcc_msm8916_resets[] = { 3313 [GCC_BLSP1_BCR] = { 0x01000 }, 3314 [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 3315 [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 3316 [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 3317 [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 3318 [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 3319 [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 3320 [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 3321 [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 3322 [GCC_IMEM_BCR] = { 0x0e000 }, 3323 [GCC_SMMU_BCR] = { 0x12000 }, 3324 [GCC_APSS_TCU_BCR] = { 0x12050 }, 3325 [GCC_SMMU_XPU_BCR] = { 0x12054 }, 3326 [GCC_PCNOC_TBU_BCR] = { 0x12058 }, 3327 [GCC_PRNG_BCR] = { 0x13000 }, 3328 [GCC_BOOT_ROM_BCR] = { 0x13008 }, 3329 [GCC_CRYPTO_BCR] = { 0x16000 }, 3330 [GCC_SEC_CTRL_BCR] = { 0x1a000 }, 3331 [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 3332 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 3333 [GCC_DEHR_BCR] = { 0x1f000 }, 3334 [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, 3335 [GCC_PCNOC_BCR] = { 0x27018 }, 3336 [GCC_TCSR_BCR] = { 0x28000 }, 3337 [GCC_QDSS_BCR] = { 0x29000 }, 3338 [GCC_DCD_BCR] = { 0x2a000 }, 3339 [GCC_MSG_RAM_BCR] = { 0x2b000 }, 3340 [GCC_MPM_BCR] = { 0x2c000 }, 3341 [GCC_SPMI_BCR] = { 0x2e000 }, 3342 [GCC_SPDM_BCR] = { 0x2f000 }, 3343 [GCC_MM_SPDM_BCR] = { 0x2f024 }, 3344 [GCC_BIMC_BCR] = { 0x31000 }, 3345 [GCC_RBCPR_BCR] = { 0x33000 }, 3346 [GCC_TLMM_BCR] = { 0x34000 }, 3347 [GCC_USB_HS_BCR] = { 0x41000 }, 3348 [GCC_USB2A_PHY_BCR] = { 0x41028 }, 3349 [GCC_SDCC1_BCR] = { 0x42000 }, 3350 [GCC_SDCC2_BCR] = { 0x43000 }, 3351 [GCC_PDM_BCR] = { 0x44000 }, 3352 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, 3353 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, 3354 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, 3355 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, 3356 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, 3357 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, 3358 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, 3359 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, 3360 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, 3361 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, 3362 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, 3363 [GCC_MMSS_BCR] = { 0x4b000 }, 3364 [GCC_VENUS0_BCR] = { 0x4c014 }, 3365 [GCC_MDSS_BCR] = { 0x4d074 }, 3366 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 3367 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 3368 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 3369 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 3370 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 3371 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, 3372 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 3373 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 3374 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 3375 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 3376 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 3377 [GCC_CAMSS_CCI_BCR] = { 0x51014 }, 3378 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 3379 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 3380 [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 3381 [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 3382 [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 3383 [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, 3384 [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, 3385 [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 3386 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 3387 [GCC_OXILI_BCR] = { 0x59018 }, 3388 [GCC_GMEM_BCR] = { 0x5902c }, 3389 [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, 3390 [GCC_MDP_TBU_BCR] = { 0x62000 }, 3391 [GCC_GFX_TBU_BCR] = { 0x63000 }, 3392 [GCC_GFX_TCU_BCR] = { 0x64000 }, 3393 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, 3394 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, 3395 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, 3396 [GCC_GTCU_AHB_BCR] = { 0x68000 }, 3397 [GCC_SMMU_CFG_BCR] = { 0x69000 }, 3398 [GCC_VFE_TBU_BCR] = { 0x6a000 }, 3399 [GCC_VENUS_TBU_BCR] = { 0x6b000 }, 3400 [GCC_JPEG_TBU_BCR] = { 0x6c000 }, 3401 [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, 3402 [GCC_SMMU_CATS_BCR] = { 0x7c000 }, 3403}; 3404 3405static const struct regmap_config gcc_msm8916_regmap_config = { 3406 .reg_bits = 32, 3407 .reg_stride = 4, 3408 .val_bits = 32, 3409 .max_register = 0x80000, 3410 .fast_io = true, 3411}; 3412 3413static const struct qcom_cc_desc gcc_msm8916_desc = { 3414 .config = &gcc_msm8916_regmap_config, 3415 .clks = gcc_msm8916_clocks, 3416 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), 3417 .resets = gcc_msm8916_resets, 3418 .num_resets = ARRAY_SIZE(gcc_msm8916_resets), 3419 .gdscs = gcc_msm8916_gdscs, 3420 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), 3421}; 3422 3423static const struct of_device_id gcc_msm8916_match_table[] = { 3424 { .compatible = "qcom,gcc-msm8916" }, 3425 { } 3426}; 3427MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table); 3428 3429static int gcc_msm8916_probe(struct platform_device *pdev) 3430{ 3431 int ret; 3432 struct device *dev = &pdev->dev; 3433 3434 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 3435 if (ret) 3436 return ret; 3437 3438 ret = qcom_cc_register_sleep_clk(dev); 3439 if (ret) 3440 return ret; 3441 3442 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3443} 3444 3445static struct platform_driver gcc_msm8916_driver = { 3446 .probe = gcc_msm8916_probe, 3447 .driver = { 3448 .name = "gcc-msm8916", 3449 .of_match_table = gcc_msm8916_match_table, 3450 }, 3451}; 3452 3453static int __init gcc_msm8916_init(void) 3454{ 3455 return platform_driver_register(&gcc_msm8916_driver); 3456} 3457core_initcall(gcc_msm8916_init); 3458 3459static void __exit gcc_msm8916_exit(void) 3460{ 3461 platform_driver_unregister(&gcc_msm8916_driver); 3462} 3463module_exit(gcc_msm8916_exit); 3464 3465MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver"); 3466MODULE_LICENSE("GPL v2"); 3467MODULE_ALIAS("platform:gcc-msm8916"); 3468