1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Linaro Ltd. 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/err.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/platform_device.h> 14#include <linux/regmap.h> 15#include <linux/pm_runtime.h> 16 17#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 18 19#include "common.h" 20#include "clk-alpha-pll.h" 21#include "clk-branch.h" 22#include "clk-pll.h" 23#include "clk-rcg.h" 24#include "clk-regmap.h" 25#include "clk-regmap-divider.h" 26#include "clk-regmap-mux.h" 27#include "reset.h" 28#include "gdsc.h" 29 30/* Need to match the order of clocks in DT binding */ 31enum { 32 DT_BI_TCXO, 33 DT_BI_TCXO_AO, 34 DT_AHB_CLK, 35 DT_SLEEP_CLK, 36 37 DT_DSI0_PHY_PLL_OUT_BYTECLK, 38 DT_DSI0_PHY_PLL_OUT_DSICLK, 39 DT_DSI1_PHY_PLL_OUT_BYTECLK, 40 DT_DSI1_PHY_PLL_OUT_DSICLK, 41 42 DT_DP0_PHY_PLL_LINK_CLK, 43 DT_DP0_PHY_PLL_VCO_DIV_CLK, 44 DT_DP1_PHY_PLL_LINK_CLK, 45 DT_DP1_PHY_PLL_VCO_DIV_CLK, 46 DT_DP2_PHY_PLL_LINK_CLK, 47 DT_DP2_PHY_PLL_VCO_DIV_CLK, 48 DT_DP3_PHY_PLL_LINK_CLK, 49 DT_DP3_PHY_PLL_VCO_DIV_CLK, 50}; 51 52#define DISP_CC_MISC_CMD 0xF000 53 54enum { 55 P_BI_TCXO, 56 P_DISP_CC_PLL0_OUT_MAIN, 57 P_DISP_CC_PLL1_OUT_EVEN, 58 P_DISP_CC_PLL1_OUT_MAIN, 59 P_DP0_PHY_PLL_LINK_CLK, 60 P_DP0_PHY_PLL_VCO_DIV_CLK, 61 P_DP1_PHY_PLL_LINK_CLK, 62 P_DP1_PHY_PLL_VCO_DIV_CLK, 63 P_DP2_PHY_PLL_LINK_CLK, 64 P_DP2_PHY_PLL_VCO_DIV_CLK, 65 P_DP3_PHY_PLL_LINK_CLK, 66 P_DP3_PHY_PLL_VCO_DIV_CLK, 67 P_DSI0_PHY_PLL_OUT_BYTECLK, 68 P_DSI0_PHY_PLL_OUT_DSICLK, 69 P_DSI1_PHY_PLL_OUT_BYTECLK, 70 P_DSI1_PHY_PLL_OUT_DSICLK, 71 P_SLEEP_CLK, 72}; 73 74static struct pll_vco lucid_ole_vco[] = { 75 { 249600000, 2000000000, 0 }, 76}; 77 78static const struct alpha_pll_config disp_cc_pll0_config = { 79 .l = 0xd, 80 .alpha = 0x6492, 81 .config_ctl_val = 0x20485699, 82 .config_ctl_hi_val = 0x00182261, 83 .config_ctl_hi1_val = 0x82aa299c, 84 .test_ctl_val = 0x00000000, 85 .test_ctl_hi_val = 0x00000003, 86 .test_ctl_hi1_val = 0x00009000, 87 .test_ctl_hi2_val = 0x00000034, 88 .user_ctl_val = 0x00000000, 89 .user_ctl_hi_val = 0x00000005, 90}; 91 92static struct clk_alpha_pll disp_cc_pll0 = { 93 .offset = 0x0, 94 .vco_table = lucid_ole_vco, 95 .num_vco = ARRAY_SIZE(lucid_ole_vco), 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 97 .clkr = { 98 .hw.init = &(struct clk_init_data) { 99 .name = "disp_cc_pll0", 100 .parent_data = &(const struct clk_parent_data) { 101 .index = DT_BI_TCXO, 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 105 }, 106 }, 107}; 108 109static const struct alpha_pll_config disp_cc_pll1_config = { 110 .l = 0x1f, 111 .alpha = 0x4000, 112 .config_ctl_val = 0x20485699, 113 .config_ctl_hi_val = 0x00182261, 114 .config_ctl_hi1_val = 0x82aa299c, 115 .test_ctl_val = 0x00000000, 116 .test_ctl_hi_val = 0x00000003, 117 .test_ctl_hi1_val = 0x00009000, 118 .test_ctl_hi2_val = 0x00000034, 119 .user_ctl_val = 0x00000000, 120 .user_ctl_hi_val = 0x00000005, 121}; 122 123static struct clk_alpha_pll disp_cc_pll1 = { 124 .offset = 0x1000, 125 .vco_table = lucid_ole_vco, 126 .num_vco = ARRAY_SIZE(lucid_ole_vco), 127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 128 .clkr = { 129 .hw.init = &(struct clk_init_data) { 130 .name = "disp_cc_pll1", 131 .parent_data = &(const struct clk_parent_data) { 132 .index = DT_BI_TCXO, 133 }, 134 .num_parents = 1, 135 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 136 }, 137 }, 138}; 139 140static const struct parent_map disp_cc_parent_map_0[] = { 141 { P_BI_TCXO, 0 }, 142}; 143 144static const struct clk_parent_data disp_cc_parent_data_0[] = { 145 { .index = DT_BI_TCXO }, 146}; 147 148static const struct clk_parent_data disp_cc_parent_data_0_ao[] = { 149 { .index = DT_BI_TCXO_AO }, 150}; 151 152static const struct parent_map disp_cc_parent_map_1[] = { 153 { P_BI_TCXO, 0 }, 154 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 155 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 156 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 157}; 158 159static const struct clk_parent_data disp_cc_parent_data_1[] = { 160 { .index = DT_BI_TCXO }, 161 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 162 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 163 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 164}; 165 166static const struct parent_map disp_cc_parent_map_2[] = { 167 { P_BI_TCXO, 0 }, 168 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 169 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 170 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 171 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 172}; 173 174static const struct clk_parent_data disp_cc_parent_data_2[] = { 175 { .index = DT_BI_TCXO }, 176 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 177 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 178 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 179 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 180}; 181 182static const struct parent_map disp_cc_parent_map_3[] = { 183 { P_BI_TCXO, 0 }, 184 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 185 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 186 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 187}; 188 189static const struct clk_parent_data disp_cc_parent_data_3[] = { 190 { .index = DT_BI_TCXO }, 191 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 192 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 193 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 194}; 195 196static const struct parent_map disp_cc_parent_map_4[] = { 197 { P_BI_TCXO, 0 }, 198 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 199 { P_DP1_PHY_PLL_VCO_DIV_CLK, 2 }, 200 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 201 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 202 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 203}; 204 205static const struct clk_parent_data disp_cc_parent_data_4[] = { 206 { .index = DT_BI_TCXO }, 207 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 208 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 209 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 210 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 211 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 212}; 213 214static const struct parent_map disp_cc_parent_map_5[] = { 215 { P_BI_TCXO, 0 }, 216 { P_DSI0_PHY_PLL_OUT_BYTECLK, 4 }, 217 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 218}; 219 220static const struct clk_parent_data disp_cc_parent_data_5[] = { 221 { .index = DT_BI_TCXO }, 222 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 223 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 224}; 225 226static const struct parent_map disp_cc_parent_map_6[] = { 227 { P_BI_TCXO, 0 }, 228 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 229 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 230}; 231 232static const struct clk_parent_data disp_cc_parent_data_6[] = { 233 { .index = DT_BI_TCXO }, 234 { .hw = &disp_cc_pll1.clkr.hw }, 235 { .hw = &disp_cc_pll1.clkr.hw }, 236}; 237 238static const struct parent_map disp_cc_parent_map_7[] = { 239 { P_BI_TCXO, 0 }, 240 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 241 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 242 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 243 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 244}; 245 246static const struct clk_parent_data disp_cc_parent_data_7[] = { 247 { .index = DT_BI_TCXO }, 248 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 249 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 250 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 251 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 252}; 253 254static const struct parent_map disp_cc_parent_map_8[] = { 255 { P_BI_TCXO, 0 }, 256 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 257 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 258 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 259}; 260 261static const struct clk_parent_data disp_cc_parent_data_8[] = { 262 { .index = DT_BI_TCXO }, 263 { .hw = &disp_cc_pll0.clkr.hw }, 264 { .hw = &disp_cc_pll1.clkr.hw }, 265 { .hw = &disp_cc_pll1.clkr.hw }, 266}; 267 268static const struct parent_map disp_cc_parent_map_9[] = { 269 { P_SLEEP_CLK, 0 }, 270}; 271 272static const struct clk_parent_data disp_cc_parent_data_9[] = { 273 { .index = DT_SLEEP_CLK }, 274}; 275 276static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 277 F(19200000, P_BI_TCXO, 1, 0, 0), 278 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 279 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 280 { } 281}; 282 283static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 284 .cmd_rcgr = 0x82e8, 285 .mnd_width = 0, 286 .hid_width = 5, 287 .parent_map = disp_cc_parent_map_6, 288 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 289 .clkr.hw.init = &(struct clk_init_data) { 290 .name = "disp_cc_mdss_ahb_clk_src", 291 .parent_data = disp_cc_parent_data_6, 292 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 293 .flags = CLK_SET_RATE_PARENT, 294 .ops = &clk_rcg2_shared_ops, 295 }, 296}; 297 298static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 299 F(19200000, P_BI_TCXO, 1, 0, 0), 300 { } 301}; 302 303static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 304 .cmd_rcgr = 0x8108, 305 .mnd_width = 0, 306 .hid_width = 5, 307 .parent_map = disp_cc_parent_map_2, 308 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 309 .clkr.hw.init = &(struct clk_init_data) { 310 .name = "disp_cc_mdss_byte0_clk_src", 311 .parent_data = disp_cc_parent_data_2, 312 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 313 .flags = CLK_SET_RATE_PARENT, 314 .ops = &clk_byte2_ops, 315 }, 316}; 317 318static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 319 .cmd_rcgr = 0x8124, 320 .mnd_width = 0, 321 .hid_width = 5, 322 .parent_map = disp_cc_parent_map_2, 323 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 324 .clkr.hw.init = &(struct clk_init_data) { 325 .name = "disp_cc_mdss_byte1_clk_src", 326 .parent_data = disp_cc_parent_data_2, 327 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 328 .flags = CLK_SET_RATE_PARENT, 329 .ops = &clk_byte2_ops, 330 }, 331}; 332 333static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 334 .cmd_rcgr = 0x81bc, 335 .mnd_width = 0, 336 .hid_width = 5, 337 .parent_map = disp_cc_parent_map_0, 338 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 339 .clkr.hw.init = &(struct clk_init_data) { 340 .name = "disp_cc_mdss_dptx0_aux_clk_src", 341 .parent_data = disp_cc_parent_data_0, 342 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 343 .flags = CLK_SET_RATE_PARENT, 344 .ops = &clk_rcg2_ops, 345 }, 346}; 347 348static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { 349 F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 350 F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 351 F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 352 F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 353 { } 354}; 355 356static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 357 .cmd_rcgr = 0x8170, 358 .mnd_width = 0, 359 .hid_width = 5, 360 .parent_map = disp_cc_parent_map_7, 361 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 362 .clkr.hw.init = &(struct clk_init_data) { 363 .name = "disp_cc_mdss_dptx0_link_clk_src", 364 .parent_data = disp_cc_parent_data_7, 365 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 366 .flags = CLK_SET_RATE_PARENT, 367 .ops = &clk_rcg2_ops, 368 }, 369}; 370 371static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 372 .cmd_rcgr = 0x818c, 373 .mnd_width = 16, 374 .hid_width = 5, 375 .parent_map = disp_cc_parent_map_4, 376 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 377 .clkr.hw.init = &(struct clk_init_data) { 378 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 379 .parent_data = disp_cc_parent_data_4, 380 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 381 .flags = CLK_SET_RATE_PARENT, 382 .ops = &clk_dp_ops, 383 }, 384}; 385 386static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 387 .cmd_rcgr = 0x81a4, 388 .mnd_width = 16, 389 .hid_width = 5, 390 .parent_map = disp_cc_parent_map_4, 391 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 392 .clkr.hw.init = &(struct clk_init_data) { 393 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 394 .parent_data = disp_cc_parent_data_4, 395 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 396 .flags = CLK_SET_RATE_PARENT, 397 .ops = &clk_dp_ops, 398 }, 399}; 400 401static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 402 .cmd_rcgr = 0x8220, 403 .mnd_width = 0, 404 .hid_width = 5, 405 .parent_map = disp_cc_parent_map_0, 406 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 407 .clkr.hw.init = &(struct clk_init_data) { 408 .name = "disp_cc_mdss_dptx1_aux_clk_src", 409 .parent_data = disp_cc_parent_data_0, 410 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 411 .flags = CLK_SET_RATE_PARENT, 412 .ops = &clk_dp_ops, 413 }, 414}; 415 416static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 417 .cmd_rcgr = 0x8204, 418 .mnd_width = 0, 419 .hid_width = 5, 420 .parent_map = disp_cc_parent_map_3, 421 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 422 .clkr.hw.init = &(struct clk_init_data) { 423 .name = "disp_cc_mdss_dptx1_link_clk_src", 424 .parent_data = disp_cc_parent_data_3, 425 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 426 .flags = CLK_SET_RATE_PARENT, 427 .ops = &clk_rcg2_ops, 428 }, 429}; 430 431static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 432 .cmd_rcgr = 0x81d4, 433 .mnd_width = 16, 434 .hid_width = 5, 435 .parent_map = disp_cc_parent_map_1, 436 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 437 .clkr.hw.init = &(struct clk_init_data) { 438 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 439 .parent_data = disp_cc_parent_data_1, 440 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 441 .flags = CLK_SET_RATE_PARENT, 442 .ops = &clk_dp_ops, 443 }, 444}; 445 446static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 447 .cmd_rcgr = 0x81ec, 448 .mnd_width = 16, 449 .hid_width = 5, 450 .parent_map = disp_cc_parent_map_1, 451 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 452 .clkr.hw.init = &(struct clk_init_data) { 453 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 454 .parent_data = disp_cc_parent_data_1, 455 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 456 .flags = CLK_SET_RATE_PARENT, 457 .ops = &clk_dp_ops, 458 }, 459}; 460 461static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 462 .cmd_rcgr = 0x8284, 463 .mnd_width = 0, 464 .hid_width = 5, 465 .parent_map = disp_cc_parent_map_0, 466 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 467 .clkr.hw.init = &(struct clk_init_data) { 468 .name = "disp_cc_mdss_dptx2_aux_clk_src", 469 .parent_data = disp_cc_parent_data_0, 470 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 471 .flags = CLK_SET_RATE_PARENT, 472 .ops = &clk_rcg2_ops, 473 }, 474}; 475 476static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 477 .cmd_rcgr = 0x8238, 478 .mnd_width = 0, 479 .hid_width = 5, 480 .parent_map = disp_cc_parent_map_3, 481 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 482 .clkr.hw.init = &(struct clk_init_data) { 483 .name = "disp_cc_mdss_dptx2_link_clk_src", 484 .parent_data = disp_cc_parent_data_3, 485 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 486 .flags = CLK_SET_RATE_PARENT, 487 .ops = &clk_rcg2_ops, 488 }, 489}; 490 491static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 492 .cmd_rcgr = 0x8254, 493 .mnd_width = 16, 494 .hid_width = 5, 495 .parent_map = disp_cc_parent_map_1, 496 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 497 .clkr.hw.init = &(struct clk_init_data) { 498 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 499 .parent_data = disp_cc_parent_data_1, 500 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 501 .flags = CLK_SET_RATE_PARENT, 502 .ops = &clk_dp_ops, 503 }, 504}; 505 506static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 507 .cmd_rcgr = 0x826c, 508 .mnd_width = 16, 509 .hid_width = 5, 510 .parent_map = disp_cc_parent_map_1, 511 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 512 .clkr.hw.init = &(struct clk_init_data) { 513 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 514 .parent_data = disp_cc_parent_data_1, 515 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 516 .flags = CLK_SET_RATE_PARENT, 517 .ops = &clk_dp_ops, 518 }, 519}; 520 521static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 522 .cmd_rcgr = 0x82d0, 523 .mnd_width = 0, 524 .hid_width = 5, 525 .parent_map = disp_cc_parent_map_0, 526 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 527 .clkr.hw.init = &(struct clk_init_data) { 528 .name = "disp_cc_mdss_dptx3_aux_clk_src", 529 .parent_data = disp_cc_parent_data_0, 530 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 531 .flags = CLK_SET_RATE_PARENT, 532 .ops = &clk_rcg2_ops, 533 }, 534}; 535 536static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 537 .cmd_rcgr = 0x82b4, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = disp_cc_parent_map_3, 541 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 542 .clkr.hw.init = &(struct clk_init_data) { 543 .name = "disp_cc_mdss_dptx3_link_clk_src", 544 .parent_data = disp_cc_parent_data_3, 545 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 546 .flags = CLK_SET_RATE_PARENT, 547 .ops = &clk_rcg2_ops, 548 }, 549}; 550 551static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 552 .cmd_rcgr = 0x829c, 553 .mnd_width = 16, 554 .hid_width = 5, 555 .parent_map = disp_cc_parent_map_1, 556 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 557 .clkr.hw.init = &(struct clk_init_data) { 558 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 559 .parent_data = disp_cc_parent_data_1, 560 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 561 .flags = CLK_SET_RATE_PARENT, 562 .ops = &clk_dp_ops, 563 }, 564}; 565 566static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 567 .cmd_rcgr = 0x8140, 568 .mnd_width = 0, 569 .hid_width = 5, 570 .parent_map = disp_cc_parent_map_5, 571 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 572 .clkr.hw.init = &(struct clk_init_data) { 573 .name = "disp_cc_mdss_esc0_clk_src", 574 .parent_data = disp_cc_parent_data_5, 575 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 576 .flags = CLK_SET_RATE_PARENT, 577 .ops = &clk_rcg2_ops, 578 }, 579}; 580 581static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 582 .cmd_rcgr = 0x8158, 583 .mnd_width = 0, 584 .hid_width = 5, 585 .parent_map = disp_cc_parent_map_5, 586 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 587 .clkr.hw.init = &(struct clk_init_data) { 588 .name = "disp_cc_mdss_esc1_clk_src", 589 .parent_data = disp_cc_parent_data_5, 590 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 591 .flags = CLK_SET_RATE_PARENT, 592 .ops = &clk_rcg2_ops, 593 }, 594}; 595 596static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 597 F(19200000, P_BI_TCXO, 1, 0, 0), 598 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 600 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 601 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 602 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 603 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 604 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 605 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 606 { } 607}; 608 609static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 610 .cmd_rcgr = 0x80d8, 611 .mnd_width = 0, 612 .hid_width = 5, 613 .parent_map = disp_cc_parent_map_8, 614 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 615 .clkr.hw.init = &(struct clk_init_data) { 616 .name = "disp_cc_mdss_mdp_clk_src", 617 .parent_data = disp_cc_parent_data_8, 618 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 619 .flags = CLK_SET_RATE_PARENT, 620 .ops = &clk_rcg2_shared_ops, 621 }, 622}; 623 624static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 625 .cmd_rcgr = 0x80a8, 626 .mnd_width = 8, 627 .hid_width = 5, 628 .parent_map = disp_cc_parent_map_2, 629 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 630 .clkr.hw.init = &(struct clk_init_data) { 631 .name = "disp_cc_mdss_pclk0_clk_src", 632 .parent_data = disp_cc_parent_data_2, 633 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 634 .flags = CLK_SET_RATE_PARENT, 635 .ops = &clk_pixel_ops, 636 }, 637}; 638 639static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 640 .cmd_rcgr = 0x80c0, 641 .mnd_width = 8, 642 .hid_width = 5, 643 .parent_map = disp_cc_parent_map_2, 644 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 645 .clkr.hw.init = &(struct clk_init_data) { 646 .name = "disp_cc_mdss_pclk1_clk_src", 647 .parent_data = disp_cc_parent_data_2, 648 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 649 .flags = CLK_SET_RATE_PARENT, 650 .ops = &clk_pixel_ops, 651 }, 652}; 653 654static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 655 .cmd_rcgr = 0x80f0, 656 .mnd_width = 0, 657 .hid_width = 5, 658 .parent_map = disp_cc_parent_map_0, 659 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 660 .clkr.hw.init = &(struct clk_init_data) { 661 .name = "disp_cc_mdss_vsync_clk_src", 662 .parent_data = disp_cc_parent_data_0, 663 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 664 .flags = CLK_SET_RATE_PARENT, 665 .ops = &clk_rcg2_ops, 666 }, 667}; 668 669static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 670 F(32000, P_SLEEP_CLK, 1, 0, 0), 671 { } 672}; 673 674static struct clk_rcg2 disp_cc_sleep_clk_src = { 675 .cmd_rcgr = 0xe05c, 676 .mnd_width = 0, 677 .hid_width = 5, 678 .parent_map = disp_cc_parent_map_9, 679 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 680 .clkr.hw.init = &(struct clk_init_data) { 681 .name = "disp_cc_sleep_clk_src", 682 .parent_data = disp_cc_parent_data_9, 683 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 684 .flags = CLK_SET_RATE_PARENT, 685 .ops = &clk_rcg2_ops, 686 }, 687}; 688 689static struct clk_rcg2 disp_cc_xo_clk_src = { 690 .cmd_rcgr = 0xe03c, 691 .mnd_width = 0, 692 .hid_width = 5, 693 .parent_map = disp_cc_parent_map_0, 694 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 695 .clkr.hw.init = &(struct clk_init_data) { 696 .name = "disp_cc_xo_clk_src", 697 .parent_data = disp_cc_parent_data_0_ao, 698 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), 699 .flags = CLK_SET_RATE_PARENT, 700 .ops = &clk_rcg2_ops, 701 }, 702}; 703 704static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 705 .reg = 0x8120, 706 .shift = 0, 707 .width = 4, 708 .clkr.hw.init = &(struct clk_init_data) { 709 .name = "disp_cc_mdss_byte0_div_clk_src", 710 .parent_hws = (const struct clk_hw*[]) { 711 &disp_cc_mdss_byte0_clk_src.clkr.hw, 712 }, 713 .num_parents = 1, 714 .ops = &clk_regmap_div_ops, 715 }, 716}; 717 718static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 719 .reg = 0x813c, 720 .shift = 0, 721 .width = 4, 722 .clkr.hw.init = &(struct clk_init_data) { 723 .name = "disp_cc_mdss_byte1_div_clk_src", 724 .parent_hws = (const struct clk_hw*[]) { 725 &disp_cc_mdss_byte1_clk_src.clkr.hw, 726 }, 727 .num_parents = 1, 728 .ops = &clk_regmap_div_ops, 729 }, 730}; 731 732static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 733 .reg = 0x8188, 734 .shift = 0, 735 .width = 4, 736 .clkr.hw.init = &(struct clk_init_data) { 737 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 738 .parent_hws = (const struct clk_hw*[]) { 739 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 740 }, 741 .num_parents = 1, 742 .flags = CLK_SET_RATE_PARENT, 743 .ops = &clk_regmap_div_ro_ops, 744 }, 745}; 746 747static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 748 .reg = 0x821c, 749 .shift = 0, 750 .width = 4, 751 .clkr.hw.init = &(struct clk_init_data) { 752 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 753 .parent_hws = (const struct clk_hw*[]) { 754 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 755 }, 756 .num_parents = 1, 757 .flags = CLK_SET_RATE_PARENT, 758 .ops = &clk_regmap_div_ro_ops, 759 }, 760}; 761 762static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 763 .reg = 0x8250, 764 .shift = 0, 765 .width = 4, 766 .clkr.hw.init = &(struct clk_init_data) { 767 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 768 .parent_hws = (const struct clk_hw*[]) { 769 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 770 }, 771 .num_parents = 1, 772 .flags = CLK_SET_RATE_PARENT, 773 .ops = &clk_regmap_div_ro_ops, 774 }, 775}; 776 777static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 778 .reg = 0x82cc, 779 .shift = 0, 780 .width = 4, 781 .clkr.hw.init = &(struct clk_init_data) { 782 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 783 .parent_hws = (const struct clk_hw*[]) { 784 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 785 }, 786 .num_parents = 1, 787 .flags = CLK_SET_RATE_PARENT, 788 .ops = &clk_regmap_div_ro_ops, 789 }, 790}; 791 792static struct clk_branch disp_cc_mdss_accu_clk = { 793 .halt_reg = 0xe058, 794 .halt_check = BRANCH_HALT_VOTED, 795 .clkr = { 796 .enable_reg = 0xe058, 797 .enable_mask = BIT(0), 798 .hw.init = &(struct clk_init_data){ 799 .name = "disp_cc_mdss_accu_clk", 800 .parent_hws = (const struct clk_hw*[]) { 801 &disp_cc_xo_clk_src.clkr.hw, 802 }, 803 .num_parents = 1, 804 .flags = CLK_SET_RATE_PARENT, 805 .ops = &clk_branch2_ops, 806 }, 807 }, 808}; 809 810static struct clk_branch disp_cc_mdss_ahb1_clk = { 811 .halt_reg = 0xa020, 812 .halt_check = BRANCH_HALT, 813 .clkr = { 814 .enable_reg = 0xa020, 815 .enable_mask = BIT(0), 816 .hw.init = &(struct clk_init_data) { 817 .name = "disp_cc_mdss_ahb1_clk", 818 .parent_hws = (const struct clk_hw*[]) { 819 &disp_cc_mdss_ahb_clk_src.clkr.hw, 820 }, 821 .num_parents = 1, 822 .flags = CLK_SET_RATE_PARENT, 823 .ops = &clk_branch2_ops, 824 }, 825 }, 826}; 827 828static struct clk_branch disp_cc_mdss_ahb_clk = { 829 .halt_reg = 0x80a4, 830 .halt_check = BRANCH_HALT, 831 .clkr = { 832 .enable_reg = 0x80a4, 833 .enable_mask = BIT(0), 834 .hw.init = &(struct clk_init_data) { 835 .name = "disp_cc_mdss_ahb_clk", 836 .parent_hws = (const struct clk_hw*[]) { 837 &disp_cc_mdss_ahb_clk_src.clkr.hw, 838 }, 839 .num_parents = 1, 840 .flags = CLK_SET_RATE_PARENT, 841 .ops = &clk_branch2_ops, 842 }, 843 }, 844}; 845 846static struct clk_branch disp_cc_mdss_byte0_clk = { 847 .halt_reg = 0x8028, 848 .halt_check = BRANCH_HALT, 849 .clkr = { 850 .enable_reg = 0x8028, 851 .enable_mask = BIT(0), 852 .hw.init = &(struct clk_init_data) { 853 .name = "disp_cc_mdss_byte0_clk", 854 .parent_hws = (const struct clk_hw*[]) { 855 &disp_cc_mdss_byte0_clk_src.clkr.hw, 856 }, 857 .num_parents = 1, 858 .flags = CLK_SET_RATE_PARENT, 859 .ops = &clk_branch2_ops, 860 }, 861 }, 862}; 863 864static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 865 .halt_reg = 0x802c, 866 .halt_check = BRANCH_HALT, 867 .clkr = { 868 .enable_reg = 0x802c, 869 .enable_mask = BIT(0), 870 .hw.init = &(struct clk_init_data) { 871 .name = "disp_cc_mdss_byte0_intf_clk", 872 .parent_hws = (const struct clk_hw*[]) { 873 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 874 }, 875 .num_parents = 1, 876 .flags = CLK_SET_RATE_PARENT, 877 .ops = &clk_branch2_ops, 878 }, 879 }, 880}; 881 882static struct clk_branch disp_cc_mdss_byte1_clk = { 883 .halt_reg = 0x8030, 884 .halt_check = BRANCH_HALT, 885 .clkr = { 886 .enable_reg = 0x8030, 887 .enable_mask = BIT(0), 888 .hw.init = &(struct clk_init_data) { 889 .name = "disp_cc_mdss_byte1_clk", 890 .parent_hws = (const struct clk_hw*[]) { 891 &disp_cc_mdss_byte1_clk_src.clkr.hw, 892 }, 893 .num_parents = 1, 894 .flags = CLK_SET_RATE_PARENT, 895 .ops = &clk_branch2_ops, 896 }, 897 }, 898}; 899 900static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 901 .halt_reg = 0x8034, 902 .halt_check = BRANCH_HALT, 903 .clkr = { 904 .enable_reg = 0x8034, 905 .enable_mask = BIT(0), 906 .hw.init = &(struct clk_init_data) { 907 .name = "disp_cc_mdss_byte1_intf_clk", 908 .parent_hws = (const struct clk_hw*[]) { 909 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 910 }, 911 .num_parents = 1, 912 .flags = CLK_SET_RATE_PARENT, 913 .ops = &clk_branch2_ops, 914 }, 915 }, 916}; 917 918static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 919 .halt_reg = 0x8058, 920 .halt_check = BRANCH_HALT, 921 .clkr = { 922 .enable_reg = 0x8058, 923 .enable_mask = BIT(0), 924 .hw.init = &(struct clk_init_data) { 925 .name = "disp_cc_mdss_dptx0_aux_clk", 926 .parent_hws = (const struct clk_hw*[]) { 927 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 928 }, 929 .num_parents = 1, 930 .flags = CLK_SET_RATE_PARENT, 931 .ops = &clk_branch2_ops, 932 }, 933 }, 934}; 935 936static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 937 .halt_reg = 0x804c, 938 .halt_check = BRANCH_HALT, 939 .clkr = { 940 .enable_reg = 0x804c, 941 .enable_mask = BIT(0), 942 .hw.init = &(struct clk_init_data) { 943 .name = "disp_cc_mdss_dptx0_crypto_clk", 944 .parent_hws = (const struct clk_hw*[]) { 945 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 946 }, 947 .num_parents = 1, 948 .flags = CLK_SET_RATE_PARENT, 949 .ops = &clk_branch2_ops, 950 }, 951 }, 952}; 953 954static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 955 .halt_reg = 0x8040, 956 .halt_check = BRANCH_HALT, 957 .clkr = { 958 .enable_reg = 0x8040, 959 .enable_mask = BIT(0), 960 .hw.init = &(struct clk_init_data) { 961 .name = "disp_cc_mdss_dptx0_link_clk", 962 .parent_hws = (const struct clk_hw*[]) { 963 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 964 }, 965 .num_parents = 1, 966 .flags = CLK_SET_RATE_PARENT, 967 .ops = &clk_branch2_ops, 968 }, 969 }, 970}; 971 972static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 973 .halt_reg = 0x8048, 974 .halt_check = BRANCH_HALT, 975 .clkr = { 976 .enable_reg = 0x8048, 977 .enable_mask = BIT(0), 978 .hw.init = &(struct clk_init_data) { 979 .name = "disp_cc_mdss_dptx0_link_intf_clk", 980 .parent_hws = (const struct clk_hw*[]) { 981 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 982 }, 983 .num_parents = 1, 984 .flags = CLK_SET_RATE_PARENT, 985 .ops = &clk_branch2_ops, 986 }, 987 }, 988}; 989 990static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 991 .halt_reg = 0x8050, 992 .halt_check = BRANCH_HALT, 993 .clkr = { 994 .enable_reg = 0x8050, 995 .enable_mask = BIT(0), 996 .hw.init = &(struct clk_init_data) { 997 .name = "disp_cc_mdss_dptx0_pixel0_clk", 998 .parent_hws = (const struct clk_hw*[]) { 999 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1000 }, 1001 .num_parents = 1, 1002 .flags = CLK_SET_RATE_PARENT, 1003 .ops = &clk_branch2_ops, 1004 }, 1005 }, 1006}; 1007 1008static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1009 .halt_reg = 0x8054, 1010 .halt_check = BRANCH_HALT, 1011 .clkr = { 1012 .enable_reg = 0x8054, 1013 .enable_mask = BIT(0), 1014 .hw.init = &(struct clk_init_data) { 1015 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1016 .parent_hws = (const struct clk_hw*[]) { 1017 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1018 }, 1019 .num_parents = 1, 1020 .flags = CLK_SET_RATE_PARENT, 1021 .ops = &clk_branch2_ops, 1022 }, 1023 }, 1024}; 1025 1026static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1027 .halt_reg = 0x8044, 1028 .halt_check = BRANCH_HALT, 1029 .clkr = { 1030 .enable_reg = 0x8044, 1031 .enable_mask = BIT(0), 1032 .hw.init = &(struct clk_init_data) { 1033 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1034 .parent_hws = (const struct clk_hw*[]) { 1035 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1036 }, 1037 .num_parents = 1, 1038 .flags = CLK_SET_RATE_PARENT, 1039 .ops = &clk_branch2_ops, 1040 }, 1041 }, 1042}; 1043 1044static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1045 .halt_reg = 0x8074, 1046 .halt_check = BRANCH_HALT, 1047 .clkr = { 1048 .enable_reg = 0x8074, 1049 .enable_mask = BIT(0), 1050 .hw.init = &(struct clk_init_data) { 1051 .name = "disp_cc_mdss_dptx1_aux_clk", 1052 .parent_hws = (const struct clk_hw*[]) { 1053 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1054 }, 1055 .num_parents = 1, 1056 .flags = CLK_SET_RATE_PARENT, 1057 .ops = &clk_branch2_ops, 1058 }, 1059 }, 1060}; 1061 1062static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1063 .halt_reg = 0x8070, 1064 .halt_check = BRANCH_HALT, 1065 .clkr = { 1066 .enable_reg = 0x8070, 1067 .enable_mask = BIT(0), 1068 .hw.init = &(struct clk_init_data) { 1069 .name = "disp_cc_mdss_dptx1_crypto_clk", 1070 .parent_hws = (const struct clk_hw*[]) { 1071 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1072 }, 1073 .num_parents = 1, 1074 .flags = CLK_SET_RATE_PARENT, 1075 .ops = &clk_branch2_ops, 1076 }, 1077 }, 1078}; 1079 1080static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1081 .halt_reg = 0x8064, 1082 .halt_check = BRANCH_HALT, 1083 .clkr = { 1084 .enable_reg = 0x8064, 1085 .enable_mask = BIT(0), 1086 .hw.init = &(struct clk_init_data) { 1087 .name = "disp_cc_mdss_dptx1_link_clk", 1088 .parent_hws = (const struct clk_hw*[]) { 1089 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1090 }, 1091 .num_parents = 1, 1092 .flags = CLK_SET_RATE_PARENT, 1093 .ops = &clk_branch2_ops, 1094 }, 1095 }, 1096}; 1097 1098static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1099 .halt_reg = 0x806c, 1100 .halt_check = BRANCH_HALT, 1101 .clkr = { 1102 .enable_reg = 0x806c, 1103 .enable_mask = BIT(0), 1104 .hw.init = &(struct clk_init_data) { 1105 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1106 .parent_hws = (const struct clk_hw*[]) { 1107 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1108 }, 1109 .num_parents = 1, 1110 .flags = CLK_SET_RATE_PARENT, 1111 .ops = &clk_branch2_ops, 1112 }, 1113 }, 1114}; 1115 1116static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1117 .halt_reg = 0x805c, 1118 .halt_check = BRANCH_HALT, 1119 .clkr = { 1120 .enable_reg = 0x805c, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(struct clk_init_data) { 1123 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1124 .parent_hws = (const struct clk_hw*[]) { 1125 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_ops, 1130 }, 1131 }, 1132}; 1133 1134static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1135 .halt_reg = 0x8060, 1136 .halt_check = BRANCH_HALT, 1137 .clkr = { 1138 .enable_reg = 0x8060, 1139 .enable_mask = BIT(0), 1140 .hw.init = &(struct clk_init_data) { 1141 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1142 .parent_hws = (const struct clk_hw*[]) { 1143 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1144 }, 1145 .num_parents = 1, 1146 .flags = CLK_SET_RATE_PARENT, 1147 .ops = &clk_branch2_ops, 1148 }, 1149 }, 1150}; 1151 1152static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1153 .halt_reg = 0x8068, 1154 .halt_check = BRANCH_HALT, 1155 .clkr = { 1156 .enable_reg = 0x8068, 1157 .enable_mask = BIT(0), 1158 .hw.init = &(struct clk_init_data) { 1159 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1160 .parent_hws = (const struct clk_hw*[]) { 1161 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1162 }, 1163 .num_parents = 1, 1164 .flags = CLK_SET_RATE_PARENT, 1165 .ops = &clk_branch2_ops, 1166 }, 1167 }, 1168}; 1169 1170static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1171 .halt_reg = 0x808c, 1172 .halt_check = BRANCH_HALT, 1173 .clkr = { 1174 .enable_reg = 0x808c, 1175 .enable_mask = BIT(0), 1176 .hw.init = &(struct clk_init_data) { 1177 .name = "disp_cc_mdss_dptx2_aux_clk", 1178 .parent_hws = (const struct clk_hw*[]) { 1179 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1180 }, 1181 .num_parents = 1, 1182 .flags = CLK_SET_RATE_PARENT, 1183 .ops = &clk_branch2_ops, 1184 }, 1185 }, 1186}; 1187 1188static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1189 .halt_reg = 0x8088, 1190 .halt_check = BRANCH_HALT, 1191 .clkr = { 1192 .enable_reg = 0x8088, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(struct clk_init_data) { 1195 .name = "disp_cc_mdss_dptx2_crypto_clk", 1196 .parent_hws = (const struct clk_hw*[]) { 1197 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1198 }, 1199 .num_parents = 1, 1200 .flags = CLK_SET_RATE_PARENT, 1201 .ops = &clk_branch2_ops, 1202 }, 1203 }, 1204}; 1205 1206static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1207 .halt_reg = 0x8080, 1208 .halt_check = BRANCH_HALT, 1209 .clkr = { 1210 .enable_reg = 0x8080, 1211 .enable_mask = BIT(0), 1212 .hw.init = &(struct clk_init_data) { 1213 .name = "disp_cc_mdss_dptx2_link_clk", 1214 .parent_hws = (const struct clk_hw*[]) { 1215 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1216 }, 1217 .num_parents = 1, 1218 .flags = CLK_SET_RATE_PARENT, 1219 .ops = &clk_branch2_ops, 1220 }, 1221 }, 1222}; 1223 1224static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1225 .halt_reg = 0x8084, 1226 .halt_check = BRANCH_HALT, 1227 .clkr = { 1228 .enable_reg = 0x8084, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(struct clk_init_data) { 1231 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1232 .parent_hws = (const struct clk_hw*[]) { 1233 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 .ops = &clk_branch2_ops, 1238 }, 1239 }, 1240}; 1241 1242static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1243 .halt_reg = 0x8078, 1244 .halt_check = BRANCH_HALT, 1245 .clkr = { 1246 .enable_reg = 0x8078, 1247 .enable_mask = BIT(0), 1248 .hw.init = &(struct clk_init_data) { 1249 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1250 .parent_hws = (const struct clk_hw*[]) { 1251 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1252 }, 1253 .num_parents = 1, 1254 .flags = CLK_SET_RATE_PARENT, 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258}; 1259 1260static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1261 .halt_reg = 0x807c, 1262 .halt_check = BRANCH_HALT, 1263 .clkr = { 1264 .enable_reg = 0x807c, 1265 .enable_mask = BIT(0), 1266 .hw.init = &(struct clk_init_data) { 1267 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1268 .parent_hws = (const struct clk_hw*[]) { 1269 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1270 }, 1271 .num_parents = 1, 1272 .flags = CLK_SET_RATE_PARENT, 1273 .ops = &clk_branch2_ops, 1274 }, 1275 }, 1276}; 1277 1278static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1279 .halt_reg = 0x809c, 1280 .halt_check = BRANCH_HALT, 1281 .clkr = { 1282 .enable_reg = 0x809c, 1283 .enable_mask = BIT(0), 1284 .hw.init = &(struct clk_init_data) { 1285 .name = "disp_cc_mdss_dptx3_aux_clk", 1286 .parent_hws = (const struct clk_hw*[]) { 1287 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1288 }, 1289 .num_parents = 1, 1290 .flags = CLK_SET_RATE_PARENT, 1291 .ops = &clk_branch2_ops, 1292 }, 1293 }, 1294}; 1295 1296static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1297 .halt_reg = 0x80a0, 1298 .halt_check = BRANCH_HALT, 1299 .clkr = { 1300 .enable_reg = 0x80a0, 1301 .enable_mask = BIT(0), 1302 .hw.init = &(struct clk_init_data) { 1303 .name = "disp_cc_mdss_dptx3_crypto_clk", 1304 .parent_hws = (const struct clk_hw*[]) { 1305 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1306 }, 1307 .num_parents = 1, 1308 .flags = CLK_SET_RATE_PARENT, 1309 .ops = &clk_branch2_ops, 1310 }, 1311 }, 1312}; 1313 1314static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1315 .halt_reg = 0x8094, 1316 .halt_check = BRANCH_HALT, 1317 .clkr = { 1318 .enable_reg = 0x8094, 1319 .enable_mask = BIT(0), 1320 .hw.init = &(struct clk_init_data) { 1321 .name = "disp_cc_mdss_dptx3_link_clk", 1322 .parent_hws = (const struct clk_hw*[]) { 1323 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1324 }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330}; 1331 1332static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1333 .halt_reg = 0x8098, 1334 .halt_check = BRANCH_HALT, 1335 .clkr = { 1336 .enable_reg = 0x8098, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data) { 1339 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1340 .parent_hws = (const struct clk_hw*[]) { 1341 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1342 }, 1343 .num_parents = 1, 1344 .flags = CLK_SET_RATE_PARENT, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348}; 1349 1350static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1351 .halt_reg = 0x8090, 1352 .halt_check = BRANCH_HALT, 1353 .clkr = { 1354 .enable_reg = 0x8090, 1355 .enable_mask = BIT(0), 1356 .hw.init = &(struct clk_init_data) { 1357 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1358 .parent_hws = (const struct clk_hw*[]) { 1359 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1360 }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT, 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366}; 1367 1368static struct clk_branch disp_cc_mdss_esc0_clk = { 1369 .halt_reg = 0x8038, 1370 .halt_check = BRANCH_HALT, 1371 .clkr = { 1372 .enable_reg = 0x8038, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(struct clk_init_data) { 1375 .name = "disp_cc_mdss_esc0_clk", 1376 .parent_hws = (const struct clk_hw*[]) { 1377 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384}; 1385 1386static struct clk_branch disp_cc_mdss_esc1_clk = { 1387 .halt_reg = 0x803c, 1388 .halt_check = BRANCH_HALT, 1389 .clkr = { 1390 .enable_reg = 0x803c, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(struct clk_init_data) { 1393 .name = "disp_cc_mdss_esc1_clk", 1394 .parent_hws = (const struct clk_hw*[]) { 1395 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402}; 1403 1404static struct clk_branch disp_cc_mdss_mdp1_clk = { 1405 .halt_reg = 0xa004, 1406 .halt_check = BRANCH_HALT, 1407 .clkr = { 1408 .enable_reg = 0xa004, 1409 .enable_mask = BIT(0), 1410 .hw.init = &(struct clk_init_data) { 1411 .name = "disp_cc_mdss_mdp1_clk", 1412 .parent_hws = (const struct clk_hw*[]) { 1413 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1414 }, 1415 .num_parents = 1, 1416 .flags = CLK_SET_RATE_PARENT, 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420}; 1421 1422static struct clk_branch disp_cc_mdss_mdp_clk = { 1423 .halt_reg = 0x800c, 1424 .halt_check = BRANCH_HALT, 1425 .clkr = { 1426 .enable_reg = 0x800c, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(struct clk_init_data) { 1429 .name = "disp_cc_mdss_mdp_clk", 1430 .parent_hws = (const struct clk_hw*[]) { 1431 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1432 }, 1433 .num_parents = 1, 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_branch2_ops, 1436 }, 1437 }, 1438}; 1439 1440static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1441 .halt_reg = 0xa010, 1442 .halt_check = BRANCH_HALT, 1443 .clkr = { 1444 .enable_reg = 0xa010, 1445 .enable_mask = BIT(0), 1446 .hw.init = &(struct clk_init_data) { 1447 .name = "disp_cc_mdss_mdp_lut1_clk", 1448 .parent_hws = (const struct clk_hw*[]) { 1449 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1450 }, 1451 .num_parents = 1, 1452 .flags = CLK_SET_RATE_PARENT, 1453 .ops = &clk_branch2_ops, 1454 }, 1455 }, 1456}; 1457 1458static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1459 .halt_reg = 0x8018, 1460 .halt_check = BRANCH_HALT_VOTED, 1461 .clkr = { 1462 .enable_reg = 0x8018, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(struct clk_init_data) { 1465 .name = "disp_cc_mdss_mdp_lut_clk", 1466 .parent_hws = (const struct clk_hw*[]) { 1467 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1468 }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474}; 1475 1476static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1477 .halt_reg = 0xc004, 1478 .halt_check = BRANCH_HALT_VOTED, 1479 .clkr = { 1480 .enable_reg = 0xc004, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(struct clk_init_data) { 1483 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1484 .parent_hws = (const struct clk_hw*[]) { 1485 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492}; 1493 1494static struct clk_branch disp_cc_mdss_pclk0_clk = { 1495 .halt_reg = 0x8004, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x8004, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(struct clk_init_data) { 1501 .name = "disp_cc_mdss_pclk0_clk", 1502 .parent_hws = (const struct clk_hw*[]) { 1503 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1504 }, 1505 .num_parents = 1, 1506 .flags = CLK_SET_RATE_PARENT, 1507 .ops = &clk_branch2_ops, 1508 }, 1509 }, 1510}; 1511 1512static struct clk_branch disp_cc_mdss_pclk1_clk = { 1513 .halt_reg = 0x8008, 1514 .halt_check = BRANCH_HALT, 1515 .clkr = { 1516 .enable_reg = 0x8008, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(struct clk_init_data) { 1519 .name = "disp_cc_mdss_pclk1_clk", 1520 .parent_hws = (const struct clk_hw*[]) { 1521 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1522 }, 1523 .num_parents = 1, 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528}; 1529 1530static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1531 .halt_reg = 0xc00c, 1532 .halt_check = BRANCH_HALT, 1533 .clkr = { 1534 .enable_reg = 0xc00c, 1535 .enable_mask = BIT(0), 1536 .hw.init = &(struct clk_init_data) { 1537 .name = "disp_cc_mdss_rscc_ahb_clk", 1538 .parent_hws = (const struct clk_hw*[]) { 1539 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1540 }, 1541 .num_parents = 1, 1542 .flags = CLK_SET_RATE_PARENT, 1543 .ops = &clk_branch2_ops, 1544 }, 1545 }, 1546}; 1547 1548static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1549 .halt_reg = 0xc008, 1550 .halt_check = BRANCH_HALT, 1551 .clkr = { 1552 .enable_reg = 0xc008, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(struct clk_init_data) { 1555 .name = "disp_cc_mdss_rscc_vsync_clk", 1556 .parent_hws = (const struct clk_hw*[]) { 1557 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564}; 1565 1566static struct clk_branch disp_cc_mdss_vsync1_clk = { 1567 .halt_reg = 0xa01c, 1568 .halt_check = BRANCH_HALT, 1569 .clkr = { 1570 .enable_reg = 0xa01c, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(struct clk_init_data) { 1573 .name = "disp_cc_mdss_vsync1_clk", 1574 .parent_hws = (const struct clk_hw*[]) { 1575 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582}; 1583 1584static struct clk_branch disp_cc_mdss_vsync_clk = { 1585 .halt_reg = 0x8024, 1586 .halt_check = BRANCH_HALT, 1587 .clkr = { 1588 .enable_reg = 0x8024, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(struct clk_init_data) { 1591 .name = "disp_cc_mdss_vsync_clk", 1592 .parent_hws = (const struct clk_hw*[]) { 1593 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1594 }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600}; 1601 1602static struct clk_branch disp_cc_sleep_clk = { 1603 .halt_reg = 0xe074, 1604 .halt_check = BRANCH_HALT, 1605 .clkr = { 1606 .enable_reg = 0xe074, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(struct clk_init_data) { 1609 .name = "disp_cc_sleep_clk", 1610 .parent_hws = (const struct clk_hw*[]) { 1611 &disp_cc_sleep_clk_src.clkr.hw, 1612 }, 1613 .num_parents = 1, 1614 .flags = CLK_SET_RATE_PARENT, 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618}; 1619 1620static struct gdsc mdss_gdsc = { 1621 .gdscr = 0x9000, 1622 .pd = { 1623 .name = "mdss_gdsc", 1624 }, 1625 .pwrsts = PWRSTS_OFF_ON, 1626 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1627}; 1628 1629static struct gdsc mdss_int2_gdsc = { 1630 .gdscr = 0xb000, 1631 .pd = { 1632 .name = "mdss_int2_gdsc", 1633 }, 1634 .pwrsts = PWRSTS_OFF_ON, 1635 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1636}; 1637 1638static struct clk_regmap *disp_cc_sm8550_clocks[] = { 1639 [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, 1640 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1641 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1642 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1643 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1644 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1645 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1646 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1647 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1648 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1649 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1650 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1651 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1652 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1653 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1654 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1655 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1656 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1657 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1658 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1659 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1660 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1661 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1662 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1663 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1664 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1665 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1666 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1667 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1668 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1669 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1670 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1671 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1672 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1673 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1674 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1675 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1676 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1677 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1678 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1679 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1680 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1681 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1682 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1683 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1684 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1685 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1686 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1687 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1688 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1689 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1690 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1691 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1692 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1693 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1694 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1695 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1696 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1697 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1698 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1699 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1700 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1701 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1702 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1703 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1704 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1705 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1706 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1707 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1708 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1709 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1710 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1711 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1712 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1713 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1714 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1715 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1716 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1717 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1718 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1719 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1720 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1721}; 1722 1723static const struct qcom_reset_map disp_cc_sm8550_resets[] = { 1724 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1725 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1726 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1727}; 1728 1729static struct gdsc *disp_cc_sm8550_gdscs[] = { 1730 [MDSS_GDSC] = &mdss_gdsc, 1731 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1732}; 1733 1734static const struct regmap_config disp_cc_sm8550_regmap_config = { 1735 .reg_bits = 32, 1736 .reg_stride = 4, 1737 .val_bits = 32, 1738 .max_register = 0x11008, 1739 .fast_io = true, 1740}; 1741 1742static struct qcom_cc_desc disp_cc_sm8550_desc = { 1743 .config = &disp_cc_sm8550_regmap_config, 1744 .clks = disp_cc_sm8550_clocks, 1745 .num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks), 1746 .resets = disp_cc_sm8550_resets, 1747 .num_resets = ARRAY_SIZE(disp_cc_sm8550_resets), 1748 .gdscs = disp_cc_sm8550_gdscs, 1749 .num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs), 1750}; 1751 1752static const struct of_device_id disp_cc_sm8550_match_table[] = { 1753 { .compatible = "qcom,sm8550-dispcc" }, 1754 { } 1755}; 1756MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table); 1757 1758static int disp_cc_sm8550_probe(struct platform_device *pdev) 1759{ 1760 struct regmap *regmap; 1761 int ret; 1762 1763 ret = devm_pm_runtime_enable(&pdev->dev); 1764 if (ret) 1765 return ret; 1766 1767 ret = pm_runtime_resume_and_get(&pdev->dev); 1768 if (ret) 1769 return ret; 1770 1771 regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc); 1772 if (IS_ERR(regmap)) { 1773 ret = PTR_ERR(regmap); 1774 goto err_put_rpm; 1775 } 1776 1777 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1778 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1779 1780 /* Enable clock gating for MDP clocks */ 1781 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1782 1783 /* 1784 * Keep clocks always enabled: 1785 * disp_cc_xo_clk 1786 */ 1787 regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); 1788 1789 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); 1790 if (ret) 1791 goto err_put_rpm; 1792 1793 pm_runtime_put(&pdev->dev); 1794 1795 return 0; 1796 1797err_put_rpm: 1798 pm_runtime_put_sync(&pdev->dev); 1799 1800 return ret; 1801} 1802 1803static struct platform_driver disp_cc_sm8550_driver = { 1804 .probe = disp_cc_sm8550_probe, 1805 .driver = { 1806 .name = "disp_cc-sm8550", 1807 .of_match_table = disp_cc_sm8550_match_table, 1808 }, 1809}; 1810 1811static int __init disp_cc_sm8550_init(void) 1812{ 1813 return platform_driver_register(&disp_cc_sm8550_driver); 1814} 1815subsys_initcall(disp_cc_sm8550_init); 1816 1817static void __exit disp_cc_sm8550_exit(void) 1818{ 1819 platform_driver_unregister(&disp_cc_sm8550_driver); 1820} 1821module_exit(disp_cc_sm8550_exit); 1822 1823MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver"); 1824MODULE_LICENSE("GPL"); 1825