1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/module.h> 8#include <linux/platform_device.h> 9#include <linux/pm_runtime.h> 10#include <linux/regmap.h> 11#include <linux/reset-controller.h> 12 13#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 14 15#include "clk-alpha-pll.h" 16#include "clk-branch.h" 17#include "clk-rcg.h" 18#include "clk-regmap-divider.h" 19#include "common.h" 20#include "gdsc.h" 21#include "reset.h" 22 23enum { 24 P_BI_TCXO, 25 P_DISP_CC_PLL0_OUT_MAIN, 26 P_DISP_CC_PLL1_OUT_EVEN, 27 P_DISP_CC_PLL1_OUT_MAIN, 28 P_DP_PHY_PLL_LINK_CLK, 29 P_DP_PHY_PLL_VCO_DIV_CLK, 30 P_DPTX1_PHY_PLL_LINK_CLK, 31 P_DPTX1_PHY_PLL_VCO_DIV_CLK, 32 P_DPTX2_PHY_PLL_LINK_CLK, 33 P_DPTX2_PHY_PLL_VCO_DIV_CLK, 34 P_EDP_PHY_PLL_LINK_CLK, 35 P_EDP_PHY_PLL_VCO_DIV_CLK, 36 P_DSI0_PHY_PLL_OUT_BYTECLK, 37 P_DSI0_PHY_PLL_OUT_DSICLK, 38 P_DSI1_PHY_PLL_OUT_BYTECLK, 39 P_DSI1_PHY_PLL_OUT_DSICLK, 40}; 41 42static struct pll_vco vco_table[] = { 43 { 249600000, 2000000000, 0 }, 44}; 45 46static struct pll_vco lucid_5lpe_vco[] = { 47 { 249600000, 1750000000, 0 }, 48}; 49 50static struct alpha_pll_config disp_cc_pll0_config = { 51 .l = 0x47, 52 .alpha = 0xE000, 53 .config_ctl_val = 0x20485699, 54 .config_ctl_hi_val = 0x00002261, 55 .config_ctl_hi1_val = 0x329A699C, 56 .user_ctl_val = 0x00000000, 57 .user_ctl_hi_val = 0x00000805, 58 .user_ctl_hi1_val = 0x00000000, 59}; 60 61static struct clk_init_data disp_cc_pll0_init = { 62 .name = "disp_cc_pll0", 63 .parent_data = &(const struct clk_parent_data){ 64 .fw_name = "bi_tcxo", 65 }, 66 .num_parents = 1, 67 .ops = &clk_alpha_pll_lucid_ops, 68}; 69 70static struct clk_alpha_pll disp_cc_pll0 = { 71 .offset = 0x0, 72 .vco_table = vco_table, 73 .num_vco = ARRAY_SIZE(vco_table), 74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 75 .clkr.hw.init = &disp_cc_pll0_init 76}; 77 78static struct alpha_pll_config disp_cc_pll1_config = { 79 .l = 0x1F, 80 .alpha = 0x4000, 81 .config_ctl_val = 0x20485699, 82 .config_ctl_hi_val = 0x00002261, 83 .config_ctl_hi1_val = 0x329A699C, 84 .user_ctl_val = 0x00000000, 85 .user_ctl_hi_val = 0x00000805, 86 .user_ctl_hi1_val = 0x00000000, 87}; 88 89static struct clk_init_data disp_cc_pll1_init = { 90 .name = "disp_cc_pll1", 91 .parent_data = &(const struct clk_parent_data){ 92 .fw_name = "bi_tcxo", 93 }, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_lucid_ops, 96}; 97 98static struct clk_alpha_pll disp_cc_pll1 = { 99 .offset = 0x1000, 100 .vco_table = vco_table, 101 .num_vco = ARRAY_SIZE(vco_table), 102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 103 .clkr.hw.init = &disp_cc_pll1_init 104}; 105 106static const struct parent_map disp_cc_parent_map_0[] = { 107 { P_BI_TCXO, 0 }, 108 { P_DP_PHY_PLL_LINK_CLK, 1 }, 109 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, 110 { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, 111 { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, 112 { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, 113 { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, 114}; 115 116static const struct clk_parent_data disp_cc_parent_data_0[] = { 117 { .fw_name = "bi_tcxo" }, 118 { .fw_name = "dp_phy_pll_link_clk" }, 119 { .fw_name = "dp_phy_pll_vco_div_clk" }, 120 { .fw_name = "dptx1_phy_pll_link_clk" }, 121 { .fw_name = "dptx1_phy_pll_vco_div_clk" }, 122 { .fw_name = "dptx2_phy_pll_link_clk" }, 123 { .fw_name = "dptx2_phy_pll_vco_div_clk" }, 124}; 125 126static const struct parent_map disp_cc_parent_map_1[] = { 127 { P_BI_TCXO, 0 }, 128}; 129 130static const struct clk_parent_data disp_cc_parent_data_1[] = { 131 { .fw_name = "bi_tcxo" }, 132}; 133 134static const struct parent_map disp_cc_parent_map_2[] = { 135 { P_BI_TCXO, 0 }, 136 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 137 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, 138}; 139 140static const struct clk_parent_data disp_cc_parent_data_2[] = { 141 { .fw_name = "bi_tcxo" }, 142 { .fw_name = "dsi0_phy_pll_out_byteclk" }, 143 { .fw_name = "dsi1_phy_pll_out_byteclk" }, 144}; 145 146static const struct parent_map disp_cc_parent_map_3[] = { 147 { P_BI_TCXO, 0 }, 148 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 149}; 150 151static const struct clk_parent_data disp_cc_parent_data_3[] = { 152 { .fw_name = "bi_tcxo" }, 153 { .hw = &disp_cc_pll1.clkr.hw }, 154}; 155 156static const struct parent_map disp_cc_parent_map_4[] = { 157 { P_BI_TCXO, 0 }, 158 { P_EDP_PHY_PLL_LINK_CLK, 1 }, 159 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, 160}; 161 162static const struct clk_parent_data disp_cc_parent_data_4[] = { 163 { .fw_name = "bi_tcxo" }, 164 { .fw_name = "edp_phy_pll_link_clk" }, 165 { .fw_name = "edp_phy_pll_vco_div_clk" }, 166}; 167 168static const struct parent_map disp_cc_parent_map_5[] = { 169 { P_BI_TCXO, 0 }, 170 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 171 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 172}; 173 174static const struct clk_parent_data disp_cc_parent_data_5[] = { 175 { .fw_name = "bi_tcxo" }, 176 { .hw = &disp_cc_pll0.clkr.hw }, 177 { .hw = &disp_cc_pll1.clkr.hw }, 178}; 179 180static const struct parent_map disp_cc_parent_map_6[] = { 181 { P_BI_TCXO, 0 }, 182 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 183 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, 184}; 185 186static const struct clk_parent_data disp_cc_parent_data_6[] = { 187 { .fw_name = "bi_tcxo" }, 188 { .fw_name = "dsi0_phy_pll_out_dsiclk" }, 189 { .fw_name = "dsi1_phy_pll_out_dsiclk" }, 190}; 191 192static const struct parent_map disp_cc_parent_map_7[] = { 193 { P_BI_TCXO, 0 }, 194 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 195 /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ 196}; 197 198static const struct clk_parent_data disp_cc_parent_data_7[] = { 199 { .fw_name = "bi_tcxo" }, 200 { .hw = &disp_cc_pll1.clkr.hw }, 201 /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ 202}; 203 204static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 205 F(19200000, P_BI_TCXO, 1, 0, 0), 206 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 207 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 208 { } 209}; 210 211static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 212 .cmd_rcgr = 0x22bc, 213 .mnd_width = 0, 214 .hid_width = 5, 215 .parent_map = disp_cc_parent_map_3, 216 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 217 .clkr.hw.init = &(struct clk_init_data){ 218 .name = "disp_cc_mdss_ahb_clk_src", 219 .parent_data = disp_cc_parent_data_3, 220 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 221 .flags = CLK_SET_RATE_PARENT, 222 .ops = &clk_rcg2_shared_ops, 223 }, 224}; 225 226static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 227 F(19200000, P_BI_TCXO, 1, 0, 0), 228 { } 229}; 230 231static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 232 .cmd_rcgr = 0x2110, 233 .mnd_width = 0, 234 .hid_width = 5, 235 .parent_map = disp_cc_parent_map_2, 236 .clkr.hw.init = &(struct clk_init_data){ 237 .name = "disp_cc_mdss_byte0_clk_src", 238 .parent_data = disp_cc_parent_data_2, 239 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 240 .flags = CLK_SET_RATE_PARENT, 241 .ops = &clk_byte2_ops, 242 }, 243}; 244 245static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 246 .cmd_rcgr = 0x212c, 247 .mnd_width = 0, 248 .hid_width = 5, 249 .parent_map = disp_cc_parent_map_2, 250 .clkr.hw.init = &(struct clk_init_data){ 251 .name = "disp_cc_mdss_byte1_clk_src", 252 .parent_data = disp_cc_parent_data_2, 253 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 254 .flags = CLK_SET_RATE_PARENT, 255 .ops = &clk_byte2_ops, 256 }, 257}; 258 259static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { 260 .cmd_rcgr = 0x2240, 261 .mnd_width = 0, 262 .hid_width = 5, 263 .parent_map = disp_cc_parent_map_1, 264 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 265 .clkr.hw.init = &(struct clk_init_data){ 266 .name = "disp_cc_mdss_dp_aux1_clk_src", 267 .parent_data = disp_cc_parent_data_1, 268 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 269 .flags = CLK_SET_RATE_PARENT, 270 .ops = &clk_rcg2_ops, 271 }, 272}; 273 274static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 275 .cmd_rcgr = 0x21dc, 276 .mnd_width = 0, 277 .hid_width = 5, 278 .parent_map = disp_cc_parent_map_1, 279 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 280 .clkr.hw.init = &(struct clk_init_data){ 281 .name = "disp_cc_mdss_dp_aux_clk_src", 282 .parent_data = disp_cc_parent_data_1, 283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 284 .flags = CLK_SET_RATE_PARENT, 285 .ops = &clk_rcg2_ops, 286 }, 287}; 288 289static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 290 .cmd_rcgr = 0x220c, 291 .mnd_width = 0, 292 .hid_width = 5, 293 .parent_map = disp_cc_parent_map_0, 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "disp_cc_mdss_dp_link1_clk_src", 296 .parent_data = disp_cc_parent_data_0, 297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 298 .ops = &clk_byte2_ops, 299 }, 300}; 301 302static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 303 .cmd_rcgr = 0x2178, 304 .mnd_width = 0, 305 .hid_width = 5, 306 .parent_map = disp_cc_parent_map_0, 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "disp_cc_mdss_dp_link_clk_src", 309 .parent_data = disp_cc_parent_data_0, 310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 311 .ops = &clk_byte2_ops, 312 }, 313}; 314 315static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { 316 .cmd_rcgr = 0x21c4, 317 .mnd_width = 16, 318 .hid_width = 5, 319 .parent_map = disp_cc_parent_map_0, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "disp_cc_mdss_dp_pixel1_clk_src", 322 .parent_data = disp_cc_parent_data_0, 323 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 324 .ops = &clk_dp_ops, 325 }, 326}; 327 328static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { 329 .cmd_rcgr = 0x21f4, 330 .mnd_width = 16, 331 .hid_width = 5, 332 .parent_map = disp_cc_parent_map_0, 333 .clkr.hw.init = &(struct clk_init_data){ 334 .name = "disp_cc_mdss_dp_pixel2_clk_src", 335 .parent_data = disp_cc_parent_data_0, 336 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 337 .ops = &clk_dp_ops, 338 }, 339}; 340 341static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 342 .cmd_rcgr = 0x21ac, 343 .mnd_width = 16, 344 .hid_width = 5, 345 .parent_map = disp_cc_parent_map_0, 346 .clkr.hw.init = &(struct clk_init_data){ 347 .name = "disp_cc_mdss_dp_pixel_clk_src", 348 .parent_data = disp_cc_parent_data_0, 349 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 350 .ops = &clk_dp_ops, 351 }, 352}; 353 354static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { 355 .cmd_rcgr = 0x228c, 356 .mnd_width = 0, 357 .hid_width = 5, 358 .parent_map = disp_cc_parent_map_1, 359 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 360 .clkr.hw.init = &(struct clk_init_data){ 361 .name = "disp_cc_mdss_edp_aux_clk_src", 362 .parent_data = disp_cc_parent_data_1, 363 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 364 .flags = CLK_SET_RATE_PARENT, 365 .ops = &clk_rcg2_ops, 366 }, 367}; 368 369static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { 370 .cmd_rcgr = 0x22a4, 371 .mnd_width = 0, 372 .hid_width = 5, 373 .parent_map = disp_cc_parent_map_7, 374 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "disp_cc_mdss_edp_gtc_clk_src", 377 .parent_data = disp_cc_parent_data_7, 378 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 379 .flags = CLK_SET_RATE_PARENT, 380 .ops = &clk_rcg2_ops, 381 }, 382}; 383 384static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { 385 .cmd_rcgr = 0x2270, 386 .mnd_width = 0, 387 .hid_width = 5, 388 .parent_map = disp_cc_parent_map_4, 389 .clkr.hw.init = &(struct clk_init_data){ 390 .name = "disp_cc_mdss_edp_link_clk_src", 391 .parent_data = disp_cc_parent_data_4, 392 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 393 .flags = CLK_SET_RATE_PARENT, 394 .ops = &clk_byte2_ops, 395 }, 396}; 397 398static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { 399 .cmd_rcgr = 0x2258, 400 .mnd_width = 16, 401 .hid_width = 5, 402 .parent_map = disp_cc_parent_map_4, 403 .clkr.hw.init = &(struct clk_init_data){ 404 .name = "disp_cc_mdss_edp_pixel_clk_src", 405 .parent_data = disp_cc_parent_data_4, 406 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 407 .ops = &clk_dp_ops, 408 }, 409}; 410 411static struct clk_branch disp_cc_mdss_edp_aux_clk = { 412 .halt_reg = 0x2078, 413 .halt_check = BRANCH_HALT, 414 .clkr = { 415 .enable_reg = 0x2078, 416 .enable_mask = BIT(0), 417 .hw.init = &(struct clk_init_data){ 418 .name = "disp_cc_mdss_edp_aux_clk", 419 .parent_hws = (const struct clk_hw*[]){ 420 &disp_cc_mdss_edp_aux_clk_src.clkr.hw, 421 }, 422 .num_parents = 1, 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_branch2_ops, 425 }, 426 }, 427}; 428 429static struct clk_branch disp_cc_mdss_edp_gtc_clk = { 430 .halt_reg = 0x207c, 431 .halt_check = BRANCH_HALT, 432 .clkr = { 433 .enable_reg = 0x207c, 434 .enable_mask = BIT(0), 435 .hw.init = &(struct clk_init_data){ 436 .name = "disp_cc_mdss_edp_gtc_clk", 437 .parent_hws = (const struct clk_hw*[]){ 438 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, 439 }, 440 .num_parents = 1, 441 .flags = CLK_SET_RATE_PARENT, 442 .ops = &clk_branch2_ops, 443 }, 444 }, 445}; 446 447static struct clk_branch disp_cc_mdss_edp_link_clk = { 448 .halt_reg = 0x2070, 449 .halt_check = BRANCH_HALT, 450 .clkr = { 451 .enable_reg = 0x2070, 452 .enable_mask = BIT(0), 453 .hw.init = &(struct clk_init_data){ 454 .name = "disp_cc_mdss_edp_link_clk", 455 .parent_hws = (const struct clk_hw*[]){ 456 &disp_cc_mdss_edp_link_clk_src.clkr.hw, 457 }, 458 .num_parents = 1, 459 .flags = CLK_SET_RATE_PARENT, 460 .ops = &clk_branch2_ops, 461 }, 462 }, 463}; 464 465static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = { 466 .reg = 0x2288, 467 .shift = 0, 468 .width = 2, 469 .clkr.hw.init = &(struct clk_init_data) { 470 .name = "disp_cc_mdss_edp_link_div_clk_src", 471 .parent_hws = (const struct clk_hw*[]){ 472 &disp_cc_mdss_edp_link_clk_src.clkr.hw, 473 }, 474 .num_parents = 1, 475 .ops = &clk_regmap_div_ro_ops, 476 }, 477}; 478 479static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { 480 .halt_reg = 0x2074, 481 .halt_check = BRANCH_HALT, 482 .clkr = { 483 .enable_reg = 0x2074, 484 .enable_mask = BIT(0), 485 .hw.init = &(struct clk_init_data){ 486 .name = "disp_cc_mdss_edp_link_intf_clk", 487 .parent_hws = (const struct clk_hw*[]){ 488 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw, 489 }, 490 .num_parents = 1, 491 .flags = CLK_GET_RATE_NOCACHE, 492 .ops = &clk_branch2_ops, 493 }, 494 }, 495}; 496 497static struct clk_branch disp_cc_mdss_edp_pixel_clk = { 498 .halt_reg = 0x206c, 499 .halt_check = BRANCH_HALT, 500 .clkr = { 501 .enable_reg = 0x206c, 502 .enable_mask = BIT(0), 503 .hw.init = &(struct clk_init_data){ 504 .name = "disp_cc_mdss_edp_pixel_clk", 505 .parent_hws = (const struct clk_hw*[]){ 506 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, 507 }, 508 .num_parents = 1, 509 .flags = CLK_SET_RATE_PARENT, 510 .ops = &clk_branch2_ops, 511 }, 512 }, 513}; 514 515static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 516 .cmd_rcgr = 0x2148, 517 .mnd_width = 0, 518 .hid_width = 5, 519 .parent_map = disp_cc_parent_map_2, 520 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 521 .clkr.hw.init = &(struct clk_init_data){ 522 .name = "disp_cc_mdss_esc0_clk_src", 523 .parent_data = disp_cc_parent_data_2, 524 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 525 .flags = CLK_SET_RATE_PARENT, 526 .ops = &clk_rcg2_ops, 527 }, 528}; 529 530static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 531 .cmd_rcgr = 0x2160, 532 .mnd_width = 0, 533 .hid_width = 5, 534 .parent_map = disp_cc_parent_map_2, 535 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 536 .clkr.hw.init = &(struct clk_init_data){ 537 .name = "disp_cc_mdss_esc1_clk_src", 538 .parent_data = disp_cc_parent_data_2, 539 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 540 .flags = CLK_SET_RATE_PARENT, 541 .ops = &clk_rcg2_ops, 542 }, 543}; 544 545static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 546 F(19200000, P_BI_TCXO, 1, 0, 0), 547 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), 548 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), 549 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 550 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 551 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 552 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 553 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 554 { } 555}; 556 557static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 558 .cmd_rcgr = 0x20c8, 559 .mnd_width = 0, 560 .hid_width = 5, 561 .parent_map = disp_cc_parent_map_5, 562 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 563 .clkr.hw.init = &(struct clk_init_data){ 564 .name = "disp_cc_mdss_mdp_clk_src", 565 .parent_data = disp_cc_parent_data_5, 566 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 567 .flags = CLK_SET_RATE_PARENT, 568 .ops = &clk_rcg2_shared_ops, 569 }, 570}; 571 572static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 573 .cmd_rcgr = 0x2098, 574 .mnd_width = 8, 575 .hid_width = 5, 576 .parent_map = disp_cc_parent_map_6, 577 .clkr.hw.init = &(struct clk_init_data){ 578 .name = "disp_cc_mdss_pclk0_clk_src", 579 .parent_data = disp_cc_parent_data_6, 580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 581 .flags = CLK_SET_RATE_PARENT, 582 .ops = &clk_pixel_ops, 583 }, 584}; 585 586static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 587 .cmd_rcgr = 0x20b0, 588 .mnd_width = 8, 589 .hid_width = 5, 590 .parent_map = disp_cc_parent_map_6, 591 .clkr.hw.init = &(struct clk_init_data){ 592 .name = "disp_cc_mdss_pclk1_clk_src", 593 .parent_data = disp_cc_parent_data_6, 594 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_pixel_ops, 597 }, 598}; 599 600static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 601 F(19200000, P_BI_TCXO, 1, 0, 0), 602 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 603 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 604 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 605 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 606 { } 607}; 608 609static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 610 .cmd_rcgr = 0x20e0, 611 .mnd_width = 0, 612 .hid_width = 5, 613 .parent_map = disp_cc_parent_map_5, 614 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "disp_cc_mdss_rot_clk_src", 617 .parent_data = disp_cc_parent_data_5, 618 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 619 .flags = CLK_SET_RATE_PARENT, 620 .ops = &clk_rcg2_shared_ops, 621 }, 622}; 623 624static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 625 .cmd_rcgr = 0x20f8, 626 .mnd_width = 0, 627 .hid_width = 5, 628 .parent_map = disp_cc_parent_map_1, 629 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 630 .clkr.hw.init = &(struct clk_init_data){ 631 .name = "disp_cc_mdss_vsync_clk_src", 632 .parent_data = disp_cc_parent_data_1, 633 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 634 .flags = CLK_SET_RATE_PARENT, 635 .ops = &clk_rcg2_ops, 636 }, 637}; 638 639static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 640 .reg = 0x2128, 641 .shift = 0, 642 .width = 2, 643 .clkr.hw.init = &(struct clk_init_data) { 644 .name = "disp_cc_mdss_byte0_div_clk_src", 645 .parent_hws = (const struct clk_hw*[]){ 646 &disp_cc_mdss_byte0_clk_src.clkr.hw, 647 }, 648 .num_parents = 1, 649 .ops = &clk_regmap_div_ops, 650 }, 651}; 652 653 654static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 655 .reg = 0x2144, 656 .shift = 0, 657 .width = 2, 658 .clkr.hw.init = &(struct clk_init_data) { 659 .name = "disp_cc_mdss_byte1_div_clk_src", 660 .parent_hws = (const struct clk_hw*[]){ 661 &disp_cc_mdss_byte1_clk_src.clkr.hw, 662 }, 663 .num_parents = 1, 664 .ops = &clk_regmap_div_ops, 665 }, 666}; 667 668 669static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { 670 .reg = 0x2224, 671 .shift = 0, 672 .width = 2, 673 .clkr.hw.init = &(struct clk_init_data) { 674 .name = "disp_cc_mdss_dp_link1_div_clk_src", 675 .parent_hws = (const struct clk_hw*[]){ 676 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 677 }, 678 .num_parents = 1, 679 .ops = &clk_regmap_div_ro_ops, 680 }, 681}; 682 683 684static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { 685 .reg = 0x2190, 686 .shift = 0, 687 .width = 2, 688 .clkr.hw.init = &(struct clk_init_data) { 689 .name = "disp_cc_mdss_dp_link_div_clk_src", 690 .parent_hws = (const struct clk_hw*[]){ 691 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 692 }, 693 .num_parents = 1, 694 .ops = &clk_regmap_div_ro_ops, 695 }, 696}; 697 698static struct clk_branch disp_cc_mdss_ahb_clk = { 699 .halt_reg = 0x2080, 700 .halt_check = BRANCH_HALT, 701 .clkr = { 702 .enable_reg = 0x2080, 703 .enable_mask = BIT(0), 704 .hw.init = &(struct clk_init_data){ 705 .name = "disp_cc_mdss_ahb_clk", 706 .parent_hws = (const struct clk_hw*[]){ 707 &disp_cc_mdss_ahb_clk_src.clkr.hw, 708 }, 709 .num_parents = 1, 710 .flags = CLK_SET_RATE_PARENT, 711 .ops = &clk_branch2_ops, 712 }, 713 }, 714}; 715 716static struct clk_branch disp_cc_mdss_byte0_clk = { 717 .halt_reg = 0x2028, 718 .halt_check = BRANCH_HALT, 719 .clkr = { 720 .enable_reg = 0x2028, 721 .enable_mask = BIT(0), 722 .hw.init = &(struct clk_init_data){ 723 .name = "disp_cc_mdss_byte0_clk", 724 .parent_hws = (const struct clk_hw*[]){ 725 &disp_cc_mdss_byte0_clk_src.clkr.hw, 726 }, 727 .num_parents = 1, 728 .flags = CLK_SET_RATE_PARENT, 729 .ops = &clk_branch2_ops, 730 }, 731 }, 732}; 733 734static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 735 .halt_reg = 0x202c, 736 .halt_check = BRANCH_HALT, 737 .clkr = { 738 .enable_reg = 0x202c, 739 .enable_mask = BIT(0), 740 .hw.init = &(struct clk_init_data){ 741 .name = "disp_cc_mdss_byte0_intf_clk", 742 .parent_hws = (const struct clk_hw*[]){ 743 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 744 }, 745 .num_parents = 1, 746 .flags = CLK_SET_RATE_PARENT, 747 .ops = &clk_branch2_ops, 748 }, 749 }, 750}; 751 752static struct clk_branch disp_cc_mdss_byte1_clk = { 753 .halt_reg = 0x2030, 754 .halt_check = BRANCH_HALT, 755 .clkr = { 756 .enable_reg = 0x2030, 757 .enable_mask = BIT(0), 758 .hw.init = &(struct clk_init_data){ 759 .name = "disp_cc_mdss_byte1_clk", 760 .parent_hws = (const struct clk_hw*[]){ 761 &disp_cc_mdss_byte1_clk_src.clkr.hw, 762 }, 763 .num_parents = 1, 764 .flags = CLK_SET_RATE_PARENT, 765 .ops = &clk_branch2_ops, 766 }, 767 }, 768}; 769 770static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 771 .halt_reg = 0x2034, 772 .halt_check = BRANCH_HALT, 773 .clkr = { 774 .enable_reg = 0x2034, 775 .enable_mask = BIT(0), 776 .hw.init = &(struct clk_init_data){ 777 .name = "disp_cc_mdss_byte1_intf_clk", 778 .parent_hws = (const struct clk_hw*[]){ 779 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 780 }, 781 .num_parents = 1, 782 .flags = CLK_SET_RATE_PARENT, 783 .ops = &clk_branch2_ops, 784 }, 785 }, 786}; 787 788static struct clk_branch disp_cc_mdss_dp_aux1_clk = { 789 .halt_reg = 0x2068, 790 .halt_check = BRANCH_HALT, 791 .clkr = { 792 .enable_reg = 0x2068, 793 .enable_mask = BIT(0), 794 .hw.init = &(struct clk_init_data){ 795 .name = "disp_cc_mdss_dp_aux1_clk", 796 .parent_hws = (const struct clk_hw*[]){ 797 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, 798 }, 799 .num_parents = 1, 800 .flags = CLK_SET_RATE_PARENT, 801 .ops = &clk_branch2_ops, 802 }, 803 }, 804}; 805 806static struct clk_branch disp_cc_mdss_dp_aux_clk = { 807 .halt_reg = 0x2054, 808 .halt_check = BRANCH_HALT, 809 .clkr = { 810 .enable_reg = 0x2054, 811 .enable_mask = BIT(0), 812 .hw.init = &(struct clk_init_data){ 813 .name = "disp_cc_mdss_dp_aux_clk", 814 .parent_hws = (const struct clk_hw*[]){ 815 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 816 }, 817 .num_parents = 1, 818 .flags = CLK_SET_RATE_PARENT, 819 .ops = &clk_branch2_ops, 820 }, 821 }, 822}; 823 824static struct clk_branch disp_cc_mdss_dp_link1_clk = { 825 .halt_reg = 0x205c, 826 .halt_check = BRANCH_HALT, 827 .clkr = { 828 .enable_reg = 0x205c, 829 .enable_mask = BIT(0), 830 .hw.init = &(struct clk_init_data){ 831 .name = "disp_cc_mdss_dp_link1_clk", 832 .parent_hws = (const struct clk_hw*[]){ 833 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 834 }, 835 .num_parents = 1, 836 .flags = CLK_SET_RATE_PARENT, 837 .ops = &clk_branch2_ops, 838 }, 839 }, 840}; 841 842static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { 843 .halt_reg = 0x2060, 844 .halt_check = BRANCH_HALT, 845 .clkr = { 846 .enable_reg = 0x2060, 847 .enable_mask = BIT(0), 848 .hw.init = &(struct clk_init_data){ 849 .name = "disp_cc_mdss_dp_link1_intf_clk", 850 .parent_hws = (const struct clk_hw*[]){ 851 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, 852 }, 853 .num_parents = 1, 854 .ops = &clk_branch2_ops, 855 }, 856 }, 857}; 858 859static struct clk_branch disp_cc_mdss_dp_link_clk = { 860 .halt_reg = 0x2040, 861 .halt_check = BRANCH_HALT, 862 .clkr = { 863 .enable_reg = 0x2040, 864 .enable_mask = BIT(0), 865 .hw.init = &(struct clk_init_data){ 866 .name = "disp_cc_mdss_dp_link_clk", 867 .parent_hws = (const struct clk_hw*[]){ 868 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 869 }, 870 .num_parents = 1, 871 .flags = CLK_SET_RATE_PARENT, 872 .ops = &clk_branch2_ops, 873 }, 874 }, 875}; 876 877static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 878 .halt_reg = 0x2044, 879 .halt_check = BRANCH_HALT, 880 .clkr = { 881 .enable_reg = 0x2044, 882 .enable_mask = BIT(0), 883 .hw.init = &(struct clk_init_data){ 884 .name = "disp_cc_mdss_dp_link_intf_clk", 885 .parent_hws = (const struct clk_hw*[]){ 886 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 887 }, 888 .num_parents = 1, 889 .ops = &clk_branch2_ops, 890 }, 891 }, 892}; 893 894static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { 895 .halt_reg = 0x2050, 896 .halt_check = BRANCH_HALT, 897 .clkr = { 898 .enable_reg = 0x2050, 899 .enable_mask = BIT(0), 900 .hw.init = &(struct clk_init_data){ 901 .name = "disp_cc_mdss_dp_pixel1_clk", 902 .parent_hws = (const struct clk_hw*[]){ 903 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, 904 }, 905 .num_parents = 1, 906 .flags = CLK_SET_RATE_PARENT, 907 .ops = &clk_branch2_ops, 908 }, 909 }, 910}; 911 912static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { 913 .halt_reg = 0x2058, 914 .halt_check = BRANCH_HALT, 915 .clkr = { 916 .enable_reg = 0x2058, 917 .enable_mask = BIT(0), 918 .hw.init = &(struct clk_init_data){ 919 .name = "disp_cc_mdss_dp_pixel2_clk", 920 .parent_hws = (const struct clk_hw*[]){ 921 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, 922 }, 923 .num_parents = 1, 924 .flags = CLK_SET_RATE_PARENT, 925 .ops = &clk_branch2_ops, 926 }, 927 }, 928}; 929 930static struct clk_branch disp_cc_mdss_dp_pixel_clk = { 931 .halt_reg = 0x204c, 932 .halt_check = BRANCH_HALT, 933 .clkr = { 934 .enable_reg = 0x204c, 935 .enable_mask = BIT(0), 936 .hw.init = &(struct clk_init_data){ 937 .name = "disp_cc_mdss_dp_pixel_clk", 938 .parent_hws = (const struct clk_hw*[]){ 939 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 940 }, 941 .num_parents = 1, 942 .flags = CLK_SET_RATE_PARENT, 943 .ops = &clk_branch2_ops, 944 }, 945 }, 946}; 947 948static struct clk_branch disp_cc_mdss_esc0_clk = { 949 .halt_reg = 0x2038, 950 .halt_check = BRANCH_HALT, 951 .clkr = { 952 .enable_reg = 0x2038, 953 .enable_mask = BIT(0), 954 .hw.init = &(struct clk_init_data){ 955 .name = "disp_cc_mdss_esc0_clk", 956 .parent_hws = (const struct clk_hw*[]){ 957 &disp_cc_mdss_esc0_clk_src.clkr.hw, 958 }, 959 .num_parents = 1, 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_branch2_ops, 962 }, 963 }, 964}; 965 966static struct clk_branch disp_cc_mdss_esc1_clk = { 967 .halt_reg = 0x203c, 968 .halt_check = BRANCH_HALT, 969 .clkr = { 970 .enable_reg = 0x203c, 971 .enable_mask = BIT(0), 972 .hw.init = &(struct clk_init_data){ 973 .name = "disp_cc_mdss_esc1_clk", 974 .parent_hws = (const struct clk_hw*[]){ 975 &disp_cc_mdss_esc1_clk_src.clkr.hw, 976 }, 977 .num_parents = 1, 978 .flags = CLK_SET_RATE_PARENT, 979 .ops = &clk_branch2_ops, 980 }, 981 }, 982}; 983 984static struct clk_branch disp_cc_mdss_mdp_clk = { 985 .halt_reg = 0x200c, 986 .halt_check = BRANCH_HALT, 987 .clkr = { 988 .enable_reg = 0x200c, 989 .enable_mask = BIT(0), 990 .hw.init = &(struct clk_init_data){ 991 .name = "disp_cc_mdss_mdp_clk", 992 .parent_hws = (const struct clk_hw*[]){ 993 &disp_cc_mdss_mdp_clk_src.clkr.hw, 994 }, 995 .num_parents = 1, 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_branch2_ops, 998 }, 999 }, 1000}; 1001 1002static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1003 .halt_reg = 0x201c, 1004 .halt_check = BRANCH_VOTED, 1005 .clkr = { 1006 .enable_reg = 0x201c, 1007 .enable_mask = BIT(0), 1008 .hw.init = &(struct clk_init_data){ 1009 .name = "disp_cc_mdss_mdp_lut_clk", 1010 .parent_hws = (const struct clk_hw*[]){ 1011 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1012 }, 1013 .num_parents = 1, 1014 .ops = &clk_branch2_ops, 1015 }, 1016 }, 1017}; 1018 1019static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1020 .halt_reg = 0x4004, 1021 .halt_check = BRANCH_VOTED, 1022 .clkr = { 1023 .enable_reg = 0x4004, 1024 .enable_mask = BIT(0), 1025 .hw.init = &(struct clk_init_data){ 1026 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1027 .parent_hws = (const struct clk_hw*[]){ 1028 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1029 }, 1030 .num_parents = 1, 1031 .flags = CLK_SET_RATE_PARENT, 1032 .ops = &clk_branch2_ops, 1033 }, 1034 }, 1035}; 1036 1037static struct clk_branch disp_cc_mdss_pclk0_clk = { 1038 .halt_reg = 0x2004, 1039 .halt_check = BRANCH_HALT, 1040 .clkr = { 1041 .enable_reg = 0x2004, 1042 .enable_mask = BIT(0), 1043 .hw.init = &(struct clk_init_data){ 1044 .name = "disp_cc_mdss_pclk0_clk", 1045 .parent_hws = (const struct clk_hw*[]){ 1046 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1047 }, 1048 .num_parents = 1, 1049 .flags = CLK_SET_RATE_PARENT, 1050 .ops = &clk_branch2_ops, 1051 }, 1052 }, 1053}; 1054 1055static struct clk_branch disp_cc_mdss_pclk1_clk = { 1056 .halt_reg = 0x2008, 1057 .halt_check = BRANCH_HALT, 1058 .clkr = { 1059 .enable_reg = 0x2008, 1060 .enable_mask = BIT(0), 1061 .hw.init = &(struct clk_init_data){ 1062 .name = "disp_cc_mdss_pclk1_clk", 1063 .parent_hws = (const struct clk_hw*[]){ 1064 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1065 }, 1066 .num_parents = 1, 1067 .flags = CLK_SET_RATE_PARENT, 1068 .ops = &clk_branch2_ops, 1069 }, 1070 }, 1071}; 1072 1073static struct clk_branch disp_cc_mdss_rot_clk = { 1074 .halt_reg = 0x2014, 1075 .halt_check = BRANCH_HALT, 1076 .clkr = { 1077 .enable_reg = 0x2014, 1078 .enable_mask = BIT(0), 1079 .hw.init = &(struct clk_init_data){ 1080 .name = "disp_cc_mdss_rot_clk", 1081 .parent_hws = (const struct clk_hw*[]){ 1082 &disp_cc_mdss_rot_clk_src.clkr.hw, 1083 }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089}; 1090 1091static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1092 .halt_reg = 0x400c, 1093 .halt_check = BRANCH_HALT, 1094 .clkr = { 1095 .enable_reg = 0x400c, 1096 .enable_mask = BIT(0), 1097 .hw.init = &(struct clk_init_data){ 1098 .name = "disp_cc_mdss_rscc_ahb_clk", 1099 .parent_hws = (const struct clk_hw*[]){ 1100 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1101 }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 .ops = &clk_branch2_ops, 1105 }, 1106 }, 1107}; 1108 1109static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1110 .halt_reg = 0x4008, 1111 .halt_check = BRANCH_HALT, 1112 .clkr = { 1113 .enable_reg = 0x4008, 1114 .enable_mask = BIT(0), 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "disp_cc_mdss_rscc_vsync_clk", 1117 .parent_hws = (const struct clk_hw*[]){ 1118 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1119 }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT, 1122 .ops = &clk_branch2_ops, 1123 }, 1124 }, 1125}; 1126 1127static struct clk_branch disp_cc_mdss_vsync_clk = { 1128 .halt_reg = 0x2024, 1129 .halt_check = BRANCH_HALT, 1130 .clkr = { 1131 .enable_reg = 0x2024, 1132 .enable_mask = BIT(0), 1133 .hw.init = &(struct clk_init_data){ 1134 .name = "disp_cc_mdss_vsync_clk", 1135 .parent_hws = (const struct clk_hw*[]){ 1136 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1137 }, 1138 .num_parents = 1, 1139 .flags = CLK_SET_RATE_PARENT, 1140 .ops = &clk_branch2_ops, 1141 }, 1142 }, 1143}; 1144 1145static struct gdsc mdss_gdsc = { 1146 .gdscr = 0x3000, 1147 .en_rest_wait_val = 0x2, 1148 .en_few_wait_val = 0x2, 1149 .clk_dis_wait_val = 0xf, 1150 .pd = { 1151 .name = "mdss_gdsc", 1152 }, 1153 .pwrsts = PWRSTS_OFF_ON, 1154 .flags = HW_CTRL | RETAIN_FF_ENABLE, 1155}; 1156 1157static struct clk_regmap *disp_cc_sm8250_clocks[] = { 1158 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1159 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1160 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1161 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1162 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1163 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1164 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1165 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1166 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1167 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1168 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, 1169 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, 1170 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, 1171 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, 1172 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, 1173 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, 1174 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, 1175 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, 1176 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, 1177 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, 1178 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, 1179 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, 1180 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, 1181 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, 1182 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, 1183 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, 1184 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, 1185 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, 1186 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, 1187 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, 1188 [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, 1189 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, 1190 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, 1191 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, 1192 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr, 1193 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, 1194 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, 1195 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, 1196 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1197 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1198 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1199 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1200 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1201 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1202 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1203 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1204 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1205 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1206 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1207 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1208 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1209 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1210 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1211 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1212 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1213 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1214 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1215 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1216}; 1217 1218static const struct qcom_reset_map disp_cc_sm8250_resets[] = { 1219 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 1220 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 1221}; 1222 1223static struct gdsc *disp_cc_sm8250_gdscs[] = { 1224 [MDSS_GDSC] = &mdss_gdsc, 1225}; 1226 1227static const struct regmap_config disp_cc_sm8250_regmap_config = { 1228 .reg_bits = 32, 1229 .reg_stride = 4, 1230 .val_bits = 32, 1231 .max_register = 0x10000, 1232 .fast_io = true, 1233}; 1234 1235static const struct qcom_cc_desc disp_cc_sm8250_desc = { 1236 .config = &disp_cc_sm8250_regmap_config, 1237 .clks = disp_cc_sm8250_clocks, 1238 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks), 1239 .resets = disp_cc_sm8250_resets, 1240 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets), 1241 .gdscs = disp_cc_sm8250_gdscs, 1242 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs), 1243}; 1244 1245static const struct of_device_id disp_cc_sm8250_match_table[] = { 1246 { .compatible = "qcom,sc8180x-dispcc" }, 1247 { .compatible = "qcom,sm8150-dispcc" }, 1248 { .compatible = "qcom,sm8250-dispcc" }, 1249 { .compatible = "qcom,sm8350-dispcc" }, 1250 { } 1251}; 1252MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); 1253 1254static int disp_cc_sm8250_probe(struct platform_device *pdev) 1255{ 1256 struct regmap *regmap; 1257 int ret; 1258 1259 ret = devm_pm_runtime_enable(&pdev->dev); 1260 if (ret) 1261 return ret; 1262 1263 ret = pm_runtime_resume_and_get(&pdev->dev); 1264 if (ret) 1265 return ret; 1266 1267 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); 1268 if (IS_ERR(regmap)) { 1269 pm_runtime_put(&pdev->dev); 1270 return PTR_ERR(regmap); 1271 } 1272 1273 /* Apply differences for SM8150 and SM8350 */ 1274 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); 1275 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || 1276 of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { 1277 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; 1278 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; 1279 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; 1280 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; 1281 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; 1282 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; 1283 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; 1284 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; 1285 1286 disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] = 1287 &disp_cc_mdss_dp_link_clk_src.clkr.hw; 1288 disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] = 1289 &disp_cc_mdss_dp_link1_clk_src.clkr.hw; 1290 disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] = 1291 &disp_cc_mdss_edp_link_clk_src.clkr.hw; 1292 1293 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL; 1294 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL; 1295 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL; 1296 } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { 1297 static struct clk_rcg2 * const rcgs[] = { 1298 &disp_cc_mdss_byte0_clk_src, 1299 &disp_cc_mdss_byte1_clk_src, 1300 &disp_cc_mdss_dp_aux1_clk_src, 1301 &disp_cc_mdss_dp_aux_clk_src, 1302 &disp_cc_mdss_dp_link1_clk_src, 1303 &disp_cc_mdss_dp_link_clk_src, 1304 &disp_cc_mdss_dp_pixel1_clk_src, 1305 &disp_cc_mdss_dp_pixel2_clk_src, 1306 &disp_cc_mdss_dp_pixel_clk_src, 1307 &disp_cc_mdss_edp_aux_clk_src, 1308 &disp_cc_mdss_edp_link_clk_src, 1309 &disp_cc_mdss_edp_pixel_clk_src, 1310 &disp_cc_mdss_esc0_clk_src, 1311 &disp_cc_mdss_esc1_clk_src, 1312 &disp_cc_mdss_mdp_clk_src, 1313 &disp_cc_mdss_pclk0_clk_src, 1314 &disp_cc_mdss_pclk1_clk_src, 1315 &disp_cc_mdss_rot_clk_src, 1316 &disp_cc_mdss_vsync_clk_src, 1317 }; 1318 static struct clk_regmap_div * const divs[] = { 1319 &disp_cc_mdss_byte0_div_clk_src, 1320 &disp_cc_mdss_byte1_div_clk_src, 1321 &disp_cc_mdss_dp_link1_div_clk_src, 1322 &disp_cc_mdss_dp_link_div_clk_src, 1323 &disp_cc_mdss_edp_link_div_clk_src, 1324 }; 1325 unsigned int i; 1326 static bool offset_applied; 1327 1328 /* 1329 * note: trion == lucid, except for the prepare() op 1330 * only apply the offsets once (in case of deferred probe) 1331 */ 1332 if (!offset_applied) { 1333 for (i = 0; i < ARRAY_SIZE(rcgs); i++) 1334 rcgs[i]->cmd_rcgr -= 4; 1335 1336 for (i = 0; i < ARRAY_SIZE(divs); i++) { 1337 divs[i]->reg -= 4; 1338 divs[i]->width = 4; 1339 } 1340 1341 disp_cc_mdss_ahb_clk.halt_reg -= 4; 1342 disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; 1343 1344 offset_applied = true; 1345 } 1346 1347 disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; 1348 1349 disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; 1350 disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; 1351 disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; 1352 disp_cc_pll0.vco_table = lucid_5lpe_vco; 1353 disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; 1354 disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; 1355 disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; 1356 disp_cc_pll1.vco_table = lucid_5lpe_vco; 1357 1358 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL; 1359 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL; 1360 } 1361 1362 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1363 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1364 1365 /* Enable clock gating for MDP clocks */ 1366 regmap_update_bits(regmap, 0x8000, 0x10, 0x10); 1367 1368 /* DISP_CC_XO_CLK always-on */ 1369 regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 1370 1371 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); 1372 1373 pm_runtime_put(&pdev->dev); 1374 1375 return ret; 1376} 1377 1378static struct platform_driver disp_cc_sm8250_driver = { 1379 .probe = disp_cc_sm8250_probe, 1380 .driver = { 1381 .name = "disp_cc-sm8250", 1382 .of_match_table = disp_cc_sm8250_match_table, 1383 }, 1384}; 1385 1386static int __init disp_cc_sm8250_init(void) 1387{ 1388 return platform_driver_register(&disp_cc_sm8250_driver); 1389} 1390subsys_initcall(disp_cc_sm8250_init); 1391 1392static void __exit disp_cc_sm8250_exit(void) 1393{ 1394 platform_driver_unregister(&disp_cc_sm8250_driver); 1395} 1396module_exit(disp_cc_sm8250_exit); 1397 1398MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); 1399MODULE_LICENSE("GPL v2"); 1400