1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <linux/kernel.h> 8#include <linux/export.h> 9#include <linux/clk-provider.h> 10#include <linux/regmap.h> 11#include <linux/delay.h> 12 13#include "clk-alpha-pll.h" 14#include "common.h" 15 16#define PLL_MODE(p) ((p)->offset + 0x0) 17# define PLL_OUTCTRL BIT(0) 18# define PLL_BYPASSNL BIT(1) 19# define PLL_RESET_N BIT(2) 20# define PLL_OFFLINE_REQ BIT(7) 21# define PLL_LOCK_COUNT_SHIFT 8 22# define PLL_LOCK_COUNT_MASK 0x3f 23# define PLL_BIAS_COUNT_SHIFT 14 24# define PLL_BIAS_COUNT_MASK 0x3f 25# define PLL_VOTE_FSM_ENA BIT(20) 26# define PLL_FSM_ENA BIT(20) 27# define PLL_VOTE_FSM_RESET BIT(21) 28# define PLL_UPDATE BIT(22) 29# define PLL_UPDATE_BYPASS BIT(23) 30# define PLL_FSM_LEGACY_MODE BIT(24) 31# define PLL_OFFLINE_ACK BIT(28) 32# define ALPHA_PLL_ACK_LATCH BIT(29) 33# define PLL_ACTIVE_FLAG BIT(30) 34# define PLL_LOCK_DET BIT(31) 35 36#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42# define PLL_POST_DIV_SHIFT 8 43# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 44# define PLL_ALPHA_EN BIT(24) 45# define PLL_ALPHA_MODE BIT(25) 46# define PLL_VCO_SHIFT 20 47# define PLL_VCO_MASK 0x3 48 49#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 56#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 57#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 58#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 59#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 60#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 61#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 62 63const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 64 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 65 [PLL_OFF_L_VAL] = 0x04, 66 [PLL_OFF_ALPHA_VAL] = 0x08, 67 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 68 [PLL_OFF_USER_CTL] = 0x10, 69 [PLL_OFF_USER_CTL_U] = 0x14, 70 [PLL_OFF_CONFIG_CTL] = 0x18, 71 [PLL_OFF_TEST_CTL] = 0x1c, 72 [PLL_OFF_TEST_CTL_U] = 0x20, 73 [PLL_OFF_STATUS] = 0x24, 74 }, 75 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 76 [PLL_OFF_L_VAL] = 0x04, 77 [PLL_OFF_ALPHA_VAL] = 0x08, 78 [PLL_OFF_USER_CTL] = 0x10, 79 [PLL_OFF_CONFIG_CTL] = 0x14, 80 [PLL_OFF_CONFIG_CTL_U] = 0x18, 81 [PLL_OFF_TEST_CTL] = 0x1c, 82 [PLL_OFF_TEST_CTL_U] = 0x20, 83 [PLL_OFF_STATUS] = 0x24, 84 }, 85 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 86 [PLL_OFF_L_VAL] = 0x04, 87 [PLL_OFF_ALPHA_VAL] = 0x08, 88 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 89 [PLL_OFF_USER_CTL] = 0x10, 90 [PLL_OFF_CONFIG_CTL] = 0x18, 91 [PLL_OFF_TEST_CTL] = 0x1c, 92 [PLL_OFF_STATUS] = 0x24, 93 }, 94 [CLK_ALPHA_PLL_TYPE_FABIA] = { 95 [PLL_OFF_L_VAL] = 0x04, 96 [PLL_OFF_USER_CTL] = 0x0c, 97 [PLL_OFF_USER_CTL_U] = 0x10, 98 [PLL_OFF_CONFIG_CTL] = 0x14, 99 [PLL_OFF_CONFIG_CTL_U] = 0x18, 100 [PLL_OFF_TEST_CTL] = 0x1c, 101 [PLL_OFF_TEST_CTL_U] = 0x20, 102 [PLL_OFF_STATUS] = 0x24, 103 [PLL_OFF_OPMODE] = 0x2c, 104 [PLL_OFF_FRAC] = 0x38, 105 }, 106 [CLK_ALPHA_PLL_TYPE_TRION] = { 107 [PLL_OFF_L_VAL] = 0x04, 108 [PLL_OFF_CAL_L_VAL] = 0x08, 109 [PLL_OFF_USER_CTL] = 0x0c, 110 [PLL_OFF_USER_CTL_U] = 0x10, 111 [PLL_OFF_USER_CTL_U1] = 0x14, 112 [PLL_OFF_CONFIG_CTL] = 0x18, 113 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 114 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 115 [PLL_OFF_TEST_CTL] = 0x24, 116 [PLL_OFF_TEST_CTL_U] = 0x28, 117 [PLL_OFF_TEST_CTL_U1] = 0x2c, 118 [PLL_OFF_STATUS] = 0x30, 119 [PLL_OFF_OPMODE] = 0x38, 120 [PLL_OFF_ALPHA_VAL] = 0x40, 121 }, 122 [CLK_ALPHA_PLL_TYPE_AGERA] = { 123 [PLL_OFF_L_VAL] = 0x04, 124 [PLL_OFF_ALPHA_VAL] = 0x08, 125 [PLL_OFF_USER_CTL] = 0x0c, 126 [PLL_OFF_CONFIG_CTL] = 0x10, 127 [PLL_OFF_CONFIG_CTL_U] = 0x14, 128 [PLL_OFF_TEST_CTL] = 0x18, 129 [PLL_OFF_TEST_CTL_U] = 0x1c, 130 [PLL_OFF_STATUS] = 0x2c, 131 }, 132 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 133 [PLL_OFF_L_VAL] = 0x04, 134 [PLL_OFF_ALPHA_VAL] = 0x08, 135 [PLL_OFF_USER_CTL] = 0x0c, 136 [PLL_OFF_CONFIG_CTL] = 0x10, 137 [PLL_OFF_CONFIG_CTL_U] = 0x14, 138 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 139 [PLL_OFF_TEST_CTL] = 0x1c, 140 [PLL_OFF_TEST_CTL_U] = 0x20, 141 [PLL_OFF_TEST_CTL_U1] = 0x24, 142 [PLL_OFF_OPMODE] = 0x28, 143 [PLL_OFF_STATUS] = 0x38, 144 }, 145 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 146 [PLL_OFF_OPMODE] = 0x04, 147 [PLL_OFF_STATUS] = 0x0c, 148 [PLL_OFF_L_VAL] = 0x10, 149 [PLL_OFF_ALPHA_VAL] = 0x14, 150 [PLL_OFF_USER_CTL] = 0x18, 151 [PLL_OFF_USER_CTL_U] = 0x1c, 152 [PLL_OFF_CONFIG_CTL] = 0x20, 153 [PLL_OFF_CONFIG_CTL_U] = 0x24, 154 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 155 [PLL_OFF_TEST_CTL] = 0x2c, 156 [PLL_OFF_TEST_CTL_U] = 0x30, 157 [PLL_OFF_TEST_CTL_U1] = 0x34, 158 }, 159 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 160 [PLL_OFF_OPMODE] = 0x04, 161 [PLL_OFF_STATE] = 0x08, 162 [PLL_OFF_STATUS] = 0x0c, 163 [PLL_OFF_L_VAL] = 0x10, 164 [PLL_OFF_ALPHA_VAL] = 0x14, 165 [PLL_OFF_USER_CTL] = 0x18, 166 [PLL_OFF_USER_CTL_U] = 0x1c, 167 [PLL_OFF_CONFIG_CTL] = 0x20, 168 [PLL_OFF_CONFIG_CTL_U] = 0x24, 169 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 170 [PLL_OFF_TEST_CTL] = 0x2c, 171 [PLL_OFF_TEST_CTL_U] = 0x30, 172 [PLL_OFF_TEST_CTL_U1] = 0x34, 173 [PLL_OFF_TEST_CTL_U2] = 0x38, 174 }, 175 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 176 [PLL_OFF_OPMODE] = 0x04, 177 [PLL_OFF_STATUS] = 0x0c, 178 [PLL_OFF_L_VAL] = 0x10, 179 [PLL_OFF_USER_CTL] = 0x14, 180 [PLL_OFF_USER_CTL_U] = 0x18, 181 [PLL_OFF_CONFIG_CTL] = 0x1c, 182 [PLL_OFF_CONFIG_CTL_U] = 0x20, 183 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 184 [PLL_OFF_TEST_CTL] = 0x28, 185 [PLL_OFF_TEST_CTL_U] = 0x2c, 186 }, 187 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 188 [PLL_OFF_L_VAL] = 0x04, 189 [PLL_OFF_ALPHA_VAL] = 0x08, 190 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 191 [PLL_OFF_TEST_CTL] = 0x10, 192 [PLL_OFF_TEST_CTL_U] = 0x14, 193 [PLL_OFF_USER_CTL] = 0x18, 194 [PLL_OFF_USER_CTL_U] = 0x1c, 195 [PLL_OFF_CONFIG_CTL] = 0x20, 196 [PLL_OFF_STATUS] = 0x24, 197 }, 198 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 199 [PLL_OFF_L_VAL] = 0x04, 200 [PLL_OFF_ALPHA_VAL] = 0x08, 201 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 202 [PLL_OFF_TEST_CTL] = 0x10, 203 [PLL_OFF_TEST_CTL_U] = 0x14, 204 [PLL_OFF_USER_CTL] = 0x18, 205 [PLL_OFF_CONFIG_CTL] = 0x1C, 206 [PLL_OFF_STATUS] = 0x20, 207 }, 208 [CLK_ALPHA_PLL_TYPE_STROMER] = { 209 [PLL_OFF_L_VAL] = 0x08, 210 [PLL_OFF_ALPHA_VAL] = 0x10, 211 [PLL_OFF_ALPHA_VAL_U] = 0x14, 212 [PLL_OFF_USER_CTL] = 0x18, 213 [PLL_OFF_USER_CTL_U] = 0x1c, 214 [PLL_OFF_CONFIG_CTL] = 0x20, 215 [PLL_OFF_CONFIG_CTL_U] = 0xff, 216 [PLL_OFF_TEST_CTL] = 0x30, 217 [PLL_OFF_TEST_CTL_U] = 0x34, 218 [PLL_OFF_STATUS] = 0x28, 219 }, 220 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 221 [PLL_OFF_L_VAL] = 0x04, 222 [PLL_OFF_USER_CTL] = 0x08, 223 [PLL_OFF_USER_CTL_U] = 0x0c, 224 [PLL_OFF_CONFIG_CTL] = 0x10, 225 [PLL_OFF_TEST_CTL] = 0x14, 226 [PLL_OFF_TEST_CTL_U] = 0x18, 227 [PLL_OFF_STATUS] = 0x1c, 228 [PLL_OFF_ALPHA_VAL] = 0x24, 229 [PLL_OFF_ALPHA_VAL_U] = 0x28, 230 }, 231}; 232EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 233 234/* 235 * Even though 40 bits are present, use only 32 for ease of calculation. 236 */ 237#define ALPHA_REG_BITWIDTH 40 238#define ALPHA_REG_16BIT_WIDTH 16 239#define ALPHA_BITWIDTH 32U 240#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 241 242#define ALPHA_PLL_STATUS_REG_SHIFT 8 243 244#define PLL_HUAYRA_M_WIDTH 8 245#define PLL_HUAYRA_M_SHIFT 8 246#define PLL_HUAYRA_M_MASK 0xff 247#define PLL_HUAYRA_N_SHIFT 0 248#define PLL_HUAYRA_N_MASK 0xff 249#define PLL_HUAYRA_ALPHA_WIDTH 16 250 251#define PLL_STANDBY 0x0 252#define PLL_RUN 0x1 253#define PLL_OUT_MASK 0x7 254#define PLL_RATE_MARGIN 500 255 256/* TRION PLL specific settings and offsets */ 257#define TRION_PLL_CAL_VAL 0x44 258#define TRION_PCAL_DONE BIT(26) 259 260/* LUCID PLL specific settings and offsets */ 261#define LUCID_PCAL_DONE BIT(27) 262 263/* LUCID 5LPE PLL specific settings and offsets */ 264#define LUCID_5LPE_PCAL_DONE BIT(11) 265#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 266#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 267#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 268 269/* LUCID EVO PLL specific settings and offsets */ 270#define LUCID_EVO_PCAL_NOT_DONE BIT(8) 271#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 272#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 273#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 274 275/* ZONDA PLL specific */ 276#define ZONDA_PLL_OUT_MASK 0xf 277#define ZONDA_STAY_IN_CFA BIT(16) 278#define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 279 280#define pll_alpha_width(p) \ 281 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 282 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 283 284#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 285 286#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 287 struct clk_alpha_pll, clkr) 288 289#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 290 struct clk_alpha_pll_postdiv, clkr) 291 292static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 293 const char *action) 294{ 295 u32 val; 296 int count; 297 int ret; 298 const char *name = clk_hw_get_name(&pll->clkr.hw); 299 300 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 301 if (ret) 302 return ret; 303 304 for (count = 200; count > 0; count--) { 305 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 306 if (ret) 307 return ret; 308 if (inverse && !(val & mask)) 309 return 0; 310 else if ((val & mask) == mask) 311 return 0; 312 313 udelay(1); 314 } 315 316 WARN(1, "%s failed to %s!\n", name, action); 317 return -ETIMEDOUT; 318} 319 320#define wait_for_pll_enable_active(pll) \ 321 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 322 323#define wait_for_pll_enable_lock(pll) \ 324 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 325 326#define wait_for_zonda_pll_freq_lock(pll) \ 327 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 328 329#define wait_for_pll_disable(pll) \ 330 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 331 332#define wait_for_pll_offline(pll) \ 333 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 334 335#define wait_for_pll_update(pll) \ 336 wait_for_pll(pll, PLL_UPDATE, 1, "update") 337 338#define wait_for_pll_update_ack_set(pll) \ 339 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 340 341#define wait_for_pll_update_ack_clear(pll) \ 342 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 343 344static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 345 unsigned int val) 346{ 347 if (val) 348 regmap_write(regmap, reg, val); 349} 350 351void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 352 const struct alpha_pll_config *config) 353{ 354 u32 val, mask; 355 356 regmap_write(regmap, PLL_L_VAL(pll), config->l); 357 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 358 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 359 360 if (pll_has_64bit_config(pll)) 361 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 362 config->config_ctl_hi_val); 363 364 if (pll_alpha_width(pll) > 32) 365 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 366 367 val = config->main_output_mask; 368 val |= config->aux_output_mask; 369 val |= config->aux2_output_mask; 370 val |= config->early_output_mask; 371 val |= config->pre_div_val; 372 val |= config->post_div_val; 373 val |= config->vco_val; 374 val |= config->alpha_en_mask; 375 val |= config->alpha_mode_mask; 376 377 mask = config->main_output_mask; 378 mask |= config->aux_output_mask; 379 mask |= config->aux2_output_mask; 380 mask |= config->early_output_mask; 381 mask |= config->pre_div_mask; 382 mask |= config->post_div_mask; 383 mask |= config->vco_mask; 384 385 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 386 387 if (config->test_ctl_mask) 388 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 389 config->test_ctl_mask, 390 config->test_ctl_val); 391 else 392 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 393 config->test_ctl_val); 394 395 if (config->test_ctl_hi_mask) 396 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 397 config->test_ctl_hi_mask, 398 config->test_ctl_hi_val); 399 else 400 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 401 config->test_ctl_hi_val); 402 403 if (pll->flags & SUPPORTS_FSM_MODE) 404 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 405} 406EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 407 408static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 409{ 410 int ret; 411 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 412 u32 val; 413 414 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 415 if (ret) 416 return ret; 417 418 val |= PLL_FSM_ENA; 419 420 if (pll->flags & SUPPORTS_OFFLINE_REQ) 421 val &= ~PLL_OFFLINE_REQ; 422 423 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 424 if (ret) 425 return ret; 426 427 /* Make sure enable request goes through before waiting for update */ 428 mb(); 429 430 return wait_for_pll_enable_active(pll); 431} 432 433static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 434{ 435 int ret; 436 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 437 u32 val; 438 439 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 440 if (ret) 441 return; 442 443 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 444 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 445 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 446 if (ret) 447 return; 448 449 ret = wait_for_pll_offline(pll); 450 if (ret) 451 return; 452 } 453 454 /* Disable hwfsm */ 455 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 456 PLL_FSM_ENA, 0); 457 if (ret) 458 return; 459 460 wait_for_pll_disable(pll); 461} 462 463static int pll_is_enabled(struct clk_hw *hw, u32 mask) 464{ 465 int ret; 466 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 467 u32 val; 468 469 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 470 if (ret) 471 return ret; 472 473 return !!(val & mask); 474} 475 476static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 477{ 478 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 479} 480 481static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 482{ 483 return pll_is_enabled(hw, PLL_LOCK_DET); 484} 485 486static int clk_alpha_pll_enable(struct clk_hw *hw) 487{ 488 int ret; 489 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 490 u32 val, mask; 491 492 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 493 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 494 if (ret) 495 return ret; 496 497 /* If in FSM mode, just vote for it */ 498 if (val & PLL_VOTE_FSM_ENA) { 499 ret = clk_enable_regmap(hw); 500 if (ret) 501 return ret; 502 return wait_for_pll_enable_active(pll); 503 } 504 505 /* Skip if already enabled */ 506 if ((val & mask) == mask) 507 return 0; 508 509 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 510 PLL_BYPASSNL, PLL_BYPASSNL); 511 if (ret) 512 return ret; 513 514 /* 515 * H/W requires a 5us delay between disabling the bypass and 516 * de-asserting the reset. 517 */ 518 mb(); 519 udelay(5); 520 521 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 522 PLL_RESET_N, PLL_RESET_N); 523 if (ret) 524 return ret; 525 526 ret = wait_for_pll_enable_lock(pll); 527 if (ret) 528 return ret; 529 530 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 531 PLL_OUTCTRL, PLL_OUTCTRL); 532 533 /* Ensure that the write above goes through before returning. */ 534 mb(); 535 return ret; 536} 537 538static void clk_alpha_pll_disable(struct clk_hw *hw) 539{ 540 int ret; 541 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 542 u32 val, mask; 543 544 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 545 if (ret) 546 return; 547 548 /* If in FSM mode, just unvote it */ 549 if (val & PLL_VOTE_FSM_ENA) { 550 clk_disable_regmap(hw); 551 return; 552 } 553 554 mask = PLL_OUTCTRL; 555 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 556 557 /* Delay of 2 output clock ticks required until output is disabled */ 558 mb(); 559 udelay(1); 560 561 mask = PLL_RESET_N | PLL_BYPASSNL; 562 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 563} 564 565static unsigned long 566alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 567{ 568 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 569} 570 571static unsigned long 572alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 573 u32 alpha_width) 574{ 575 u64 remainder; 576 u64 quotient; 577 578 quotient = rate; 579 remainder = do_div(quotient, prate); 580 *l = quotient; 581 582 if (!remainder) { 583 *a = 0; 584 return rate; 585 } 586 587 /* Upper ALPHA_BITWIDTH bits of Alpha */ 588 quotient = remainder << ALPHA_SHIFT(alpha_width); 589 590 remainder = do_div(quotient, prate); 591 592 if (remainder) 593 quotient++; 594 595 *a = quotient; 596 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 597} 598 599static const struct pll_vco * 600alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 601{ 602 const struct pll_vco *v = pll->vco_table; 603 const struct pll_vco *end = v + pll->num_vco; 604 605 for (; v < end; v++) 606 if (rate >= v->min_freq && rate <= v->max_freq) 607 return v; 608 609 return NULL; 610} 611 612static unsigned long 613clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 614{ 615 u32 l, low, high, ctl; 616 u64 a = 0, prate = parent_rate; 617 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 618 u32 alpha_width = pll_alpha_width(pll); 619 620 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 621 622 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 623 if (ctl & PLL_ALPHA_EN) { 624 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 625 if (alpha_width > 32) { 626 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 627 &high); 628 a = (u64)high << 32 | low; 629 } else { 630 a = low & GENMASK(alpha_width - 1, 0); 631 } 632 633 if (alpha_width > ALPHA_BITWIDTH) 634 a >>= alpha_width - ALPHA_BITWIDTH; 635 } 636 637 return alpha_pll_calc_rate(prate, l, a, alpha_width); 638} 639 640 641static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 642{ 643 int ret; 644 u32 mode; 645 646 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 647 648 /* Latch the input to the PLL */ 649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 650 PLL_UPDATE); 651 652 /* Wait for 2 reference cycle before checking ACK bit */ 653 udelay(1); 654 655 /* 656 * PLL will latch the new L, Alpha and freq control word. 657 * PLL will respond by raising PLL_ACK_LATCH output when new programming 658 * has been latched in and PLL is being updated. When 659 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 660 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 661 */ 662 if (mode & PLL_UPDATE_BYPASS) { 663 ret = wait_for_pll_update_ack_set(pll); 664 if (ret) 665 return ret; 666 667 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 668 } else { 669 ret = wait_for_pll_update(pll); 670 if (ret) 671 return ret; 672 } 673 674 ret = wait_for_pll_update_ack_clear(pll); 675 if (ret) 676 return ret; 677 678 /* Wait for PLL output to stabilize */ 679 udelay(10); 680 681 return 0; 682} 683 684static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 685 int (*is_enabled)(struct clk_hw *)) 686{ 687 if (!is_enabled(&pll->clkr.hw) || 688 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 689 return 0; 690 691 return __clk_alpha_pll_update_latch(pll); 692} 693 694static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 695 unsigned long prate, 696 int (*is_enabled)(struct clk_hw *)) 697{ 698 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 699 const struct pll_vco *vco; 700 u32 l, alpha_width = pll_alpha_width(pll); 701 u64 a; 702 703 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 704 vco = alpha_pll_find_vco(pll, rate); 705 if (pll->vco_table && !vco) { 706 pr_err("%s: alpha pll not in a valid vco range\n", 707 clk_hw_get_name(hw)); 708 return -EINVAL; 709 } 710 711 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 712 713 if (alpha_width > ALPHA_BITWIDTH) 714 a <<= alpha_width - ALPHA_BITWIDTH; 715 716 if (alpha_width > 32) 717 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 718 719 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 720 721 if (vco) { 722 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 723 PLL_VCO_MASK << PLL_VCO_SHIFT, 724 vco->val << PLL_VCO_SHIFT); 725 } 726 727 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 728 PLL_ALPHA_EN, PLL_ALPHA_EN); 729 730 return clk_alpha_pll_update_latch(pll, is_enabled); 731} 732 733static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 734 unsigned long prate) 735{ 736 return __clk_alpha_pll_set_rate(hw, rate, prate, 737 clk_alpha_pll_is_enabled); 738} 739 740static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 741 unsigned long prate) 742{ 743 return __clk_alpha_pll_set_rate(hw, rate, prate, 744 clk_alpha_pll_hwfsm_is_enabled); 745} 746 747static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 748 unsigned long *prate) 749{ 750 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 751 u32 l, alpha_width = pll_alpha_width(pll); 752 u64 a; 753 unsigned long min_freq, max_freq; 754 755 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 756 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 757 return rate; 758 759 min_freq = pll->vco_table[0].min_freq; 760 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 761 762 return clamp(rate, min_freq, max_freq); 763} 764 765static unsigned long 766alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 767{ 768 /* 769 * a contains 16 bit alpha_val in two’s complement number in the range 770 * of [-0.5, 0.5). 771 */ 772 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 773 l -= 1; 774 775 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 776} 777 778static unsigned long 779alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 780 u32 *l, u32 *a) 781{ 782 u64 remainder; 783 u64 quotient; 784 785 quotient = rate; 786 remainder = do_div(quotient, prate); 787 *l = quotient; 788 789 if (!remainder) { 790 *a = 0; 791 return rate; 792 } 793 794 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 795 remainder = do_div(quotient, prate); 796 797 if (remainder) 798 quotient++; 799 800 /* 801 * alpha_val should be in two’s complement number in the range 802 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 803 * since alpha value will be subtracted in this case. 804 */ 805 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 806 *l += 1; 807 808 *a = quotient; 809 return alpha_huayra_pll_calc_rate(prate, *l, *a); 810} 811 812static unsigned long 813alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 814{ 815 u64 rate = parent_rate, tmp; 816 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 817 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 818 819 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 820 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 821 822 if (ctl & PLL_ALPHA_EN) { 823 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 824 /* 825 * Depending upon alpha_mode, it can be treated as M/N value or 826 * as a two’s complement number. When alpha_mode=1, 827 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 828 * 829 * Fout=FIN*(L+(M/N)) 830 * 831 * M is a signed number (-128 to 127) and N is unsigned 832 * (0 to 255). M/N has to be within +/-0.5. 833 * 834 * When alpha_mode=0, it is a two’s complement number in the 835 * range [-0.5, 0.5). 836 * 837 * Fout=FIN*(L+(alpha_val)/2^16) 838 * 839 * where alpha_val is two’s complement number. 840 */ 841 if (!(ctl & PLL_ALPHA_MODE)) 842 return alpha_huayra_pll_calc_rate(rate, l, alpha); 843 844 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 845 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 846 847 rate *= l; 848 tmp = parent_rate; 849 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 850 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 851 tmp *= alpha_m; 852 do_div(tmp, alpha_n); 853 rate -= tmp; 854 } else { 855 tmp *= alpha_m; 856 do_div(tmp, alpha_n); 857 rate += tmp; 858 } 859 860 return rate; 861 } 862 863 return alpha_huayra_pll_calc_rate(rate, l, alpha); 864} 865 866static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 867 unsigned long prate) 868{ 869 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 870 u32 l, a, ctl, cur_alpha = 0; 871 872 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 873 874 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 875 876 if (ctl & PLL_ALPHA_EN) 877 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 878 879 /* 880 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 881 * without having to go through the power on sequence. 882 */ 883 if (clk_alpha_pll_is_enabled(hw)) { 884 if (cur_alpha != a) { 885 pr_err("%s: clock needs to be gated\n", 886 clk_hw_get_name(hw)); 887 return -EBUSY; 888 } 889 890 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 891 /* Ensure that the write above goes to detect L val change. */ 892 mb(); 893 return wait_for_pll_enable_lock(pll); 894 } 895 896 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 897 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 898 899 if (a == 0) 900 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 901 PLL_ALPHA_EN, 0x0); 902 else 903 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 904 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 905 906 return 0; 907} 908 909static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 910 unsigned long *prate) 911{ 912 u32 l, a; 913 914 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 915} 916 917static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 918 struct regmap *regmap) 919{ 920 u32 mode_val, opmode_val; 921 int ret; 922 923 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 924 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 925 if (ret) 926 return 0; 927 928 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 929} 930 931static int clk_trion_pll_is_enabled(struct clk_hw *hw) 932{ 933 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 934 935 return trion_pll_is_enabled(pll, pll->clkr.regmap); 936} 937 938static int clk_trion_pll_enable(struct clk_hw *hw) 939{ 940 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 941 struct regmap *regmap = pll->clkr.regmap; 942 u32 val; 943 int ret; 944 945 ret = regmap_read(regmap, PLL_MODE(pll), &val); 946 if (ret) 947 return ret; 948 949 /* If in FSM mode, just vote for it */ 950 if (val & PLL_VOTE_FSM_ENA) { 951 ret = clk_enable_regmap(hw); 952 if (ret) 953 return ret; 954 return wait_for_pll_enable_active(pll); 955 } 956 957 /* Set operation mode to RUN */ 958 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 959 960 ret = wait_for_pll_enable_lock(pll); 961 if (ret) 962 return ret; 963 964 /* Enable the PLL outputs */ 965 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 966 PLL_OUT_MASK, PLL_OUT_MASK); 967 if (ret) 968 return ret; 969 970 /* Enable the global PLL outputs */ 971 return regmap_update_bits(regmap, PLL_MODE(pll), 972 PLL_OUTCTRL, PLL_OUTCTRL); 973} 974 975static void clk_trion_pll_disable(struct clk_hw *hw) 976{ 977 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 978 struct regmap *regmap = pll->clkr.regmap; 979 u32 val; 980 int ret; 981 982 ret = regmap_read(regmap, PLL_MODE(pll), &val); 983 if (ret) 984 return; 985 986 /* If in FSM mode, just unvote it */ 987 if (val & PLL_VOTE_FSM_ENA) { 988 clk_disable_regmap(hw); 989 return; 990 } 991 992 /* Disable the global PLL output */ 993 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 994 if (ret) 995 return; 996 997 /* Disable the PLL outputs */ 998 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 999 PLL_OUT_MASK, 0); 1000 if (ret) 1001 return; 1002 1003 /* Place the PLL mode in STANDBY */ 1004 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1005 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1006} 1007 1008static unsigned long 1009clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1010{ 1011 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1012 u32 l, frac, alpha_width = pll_alpha_width(pll); 1013 1014 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1015 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 1016 1017 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1018} 1019 1020const struct clk_ops clk_alpha_pll_fixed_ops = { 1021 .enable = clk_alpha_pll_enable, 1022 .disable = clk_alpha_pll_disable, 1023 .is_enabled = clk_alpha_pll_is_enabled, 1024 .recalc_rate = clk_alpha_pll_recalc_rate, 1025}; 1026EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1027 1028const struct clk_ops clk_alpha_pll_ops = { 1029 .enable = clk_alpha_pll_enable, 1030 .disable = clk_alpha_pll_disable, 1031 .is_enabled = clk_alpha_pll_is_enabled, 1032 .recalc_rate = clk_alpha_pll_recalc_rate, 1033 .round_rate = clk_alpha_pll_round_rate, 1034 .set_rate = clk_alpha_pll_set_rate, 1035}; 1036EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1037 1038const struct clk_ops clk_alpha_pll_huayra_ops = { 1039 .enable = clk_alpha_pll_enable, 1040 .disable = clk_alpha_pll_disable, 1041 .is_enabled = clk_alpha_pll_is_enabled, 1042 .recalc_rate = alpha_pll_huayra_recalc_rate, 1043 .round_rate = alpha_pll_huayra_round_rate, 1044 .set_rate = alpha_pll_huayra_set_rate, 1045}; 1046EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1047 1048const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1049 .enable = clk_alpha_pll_hwfsm_enable, 1050 .disable = clk_alpha_pll_hwfsm_disable, 1051 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1052 .recalc_rate = clk_alpha_pll_recalc_rate, 1053 .round_rate = clk_alpha_pll_round_rate, 1054 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1055}; 1056EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1057 1058const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1059 .enable = clk_trion_pll_enable, 1060 .disable = clk_trion_pll_disable, 1061 .is_enabled = clk_trion_pll_is_enabled, 1062 .recalc_rate = clk_trion_pll_recalc_rate, 1063 .round_rate = clk_alpha_pll_round_rate, 1064}; 1065EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1066 1067static unsigned long 1068clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1069{ 1070 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1071 u32 ctl; 1072 1073 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1074 1075 ctl >>= PLL_POST_DIV_SHIFT; 1076 ctl &= PLL_POST_DIV_MASK(pll); 1077 1078 return parent_rate >> fls(ctl); 1079} 1080 1081static const struct clk_div_table clk_alpha_div_table[] = { 1082 { 0x0, 1 }, 1083 { 0x1, 2 }, 1084 { 0x3, 4 }, 1085 { 0x7, 8 }, 1086 { 0xf, 16 }, 1087 { } 1088}; 1089 1090static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1091 { 0x0, 1 }, 1092 { 0x1, 2 }, 1093 { 0x3, 4 }, 1094 { } 1095}; 1096 1097static long 1098clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1099 unsigned long *prate) 1100{ 1101 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1102 const struct clk_div_table *table; 1103 1104 if (pll->width == 2) 1105 table = clk_alpha_2bit_div_table; 1106 else 1107 table = clk_alpha_div_table; 1108 1109 return divider_round_rate(hw, rate, prate, table, 1110 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1111} 1112 1113static long 1114clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1115 unsigned long *prate) 1116{ 1117 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1118 u32 ctl, div; 1119 1120 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1121 1122 ctl >>= PLL_POST_DIV_SHIFT; 1123 ctl &= BIT(pll->width) - 1; 1124 div = 1 << fls(ctl); 1125 1126 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1127 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1128 1129 return DIV_ROUND_UP_ULL((u64)*prate, div); 1130} 1131 1132static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1133 unsigned long parent_rate) 1134{ 1135 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1136 int div; 1137 1138 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1139 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1140 1141 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1142 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1143 div << PLL_POST_DIV_SHIFT); 1144} 1145 1146const struct clk_ops clk_alpha_pll_postdiv_ops = { 1147 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1148 .round_rate = clk_alpha_pll_postdiv_round_rate, 1149 .set_rate = clk_alpha_pll_postdiv_set_rate, 1150}; 1151EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1152 1153const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1154 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1155 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1156}; 1157EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1158 1159void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1160 const struct alpha_pll_config *config) 1161{ 1162 u32 val, mask; 1163 1164 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1165 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1166 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1167 config->config_ctl_val); 1168 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1169 config->config_ctl_hi_val); 1170 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1171 config->user_ctl_val); 1172 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1173 config->user_ctl_hi_val); 1174 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1175 config->test_ctl_val); 1176 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1177 config->test_ctl_hi_val); 1178 1179 if (config->post_div_mask) { 1180 mask = config->post_div_mask; 1181 val = config->post_div_val; 1182 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1183 } 1184 1185 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1186 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1187 PLL_FSM_LEGACY_MODE); 1188 1189 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1190 PLL_UPDATE_BYPASS); 1191 1192 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1193} 1194EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1195 1196static int alpha_pll_fabia_enable(struct clk_hw *hw) 1197{ 1198 int ret; 1199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1200 u32 val, opmode_val; 1201 struct regmap *regmap = pll->clkr.regmap; 1202 1203 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1204 if (ret) 1205 return ret; 1206 1207 /* If in FSM mode, just vote for it */ 1208 if (val & PLL_VOTE_FSM_ENA) { 1209 ret = clk_enable_regmap(hw); 1210 if (ret) 1211 return ret; 1212 return wait_for_pll_enable_active(pll); 1213 } 1214 1215 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1216 if (ret) 1217 return ret; 1218 1219 /* Skip If PLL is already running */ 1220 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1221 return 0; 1222 1223 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1224 if (ret) 1225 return ret; 1226 1227 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1228 if (ret) 1229 return ret; 1230 1231 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1232 PLL_RESET_N); 1233 if (ret) 1234 return ret; 1235 1236 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1237 if (ret) 1238 return ret; 1239 1240 ret = wait_for_pll_enable_lock(pll); 1241 if (ret) 1242 return ret; 1243 1244 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1245 PLL_OUT_MASK, PLL_OUT_MASK); 1246 if (ret) 1247 return ret; 1248 1249 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1250 PLL_OUTCTRL); 1251} 1252 1253static void alpha_pll_fabia_disable(struct clk_hw *hw) 1254{ 1255 int ret; 1256 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1257 u32 val; 1258 struct regmap *regmap = pll->clkr.regmap; 1259 1260 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1261 if (ret) 1262 return; 1263 1264 /* If in FSM mode, just unvote it */ 1265 if (val & PLL_FSM_ENA) { 1266 clk_disable_regmap(hw); 1267 return; 1268 } 1269 1270 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1271 if (ret) 1272 return; 1273 1274 /* Disable main outputs */ 1275 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1276 if (ret) 1277 return; 1278 1279 /* Place the PLL in STANDBY */ 1280 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1281} 1282 1283static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1284 unsigned long parent_rate) 1285{ 1286 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1287 u32 l, frac, alpha_width = pll_alpha_width(pll); 1288 1289 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1290 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1291 1292 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1293} 1294 1295/* 1296 * Due to limited number of bits for fractional rate programming, the 1297 * rounded up rate could be marginally higher than the requested rate. 1298 */ 1299static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1300 unsigned long rrate, unsigned long rate) 1301{ 1302 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1303 1304 if (rrate > rate_margin || rrate < rate) { 1305 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1306 clk_hw_get_name(hw), rrate, rate, rate_margin); 1307 return -EINVAL; 1308 } 1309 1310 return 0; 1311} 1312 1313static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1314 unsigned long prate) 1315{ 1316 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1317 u32 l, alpha_width = pll_alpha_width(pll); 1318 unsigned long rrate; 1319 int ret; 1320 u64 a; 1321 1322 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1323 1324 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1325 if (ret < 0) 1326 return ret; 1327 1328 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1329 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1330 1331 return __clk_alpha_pll_update_latch(pll); 1332} 1333 1334static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1335{ 1336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1337 const struct pll_vco *vco; 1338 struct clk_hw *parent_hw; 1339 unsigned long cal_freq, rrate; 1340 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1341 const char *name = clk_hw_get_name(hw); 1342 u64 a; 1343 int ret; 1344 1345 /* Check if calibration needs to be done i.e. PLL is in reset */ 1346 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1347 if (ret) 1348 return ret; 1349 1350 /* Return early if calibration is not needed. */ 1351 if (val & PLL_RESET_N) 1352 return 0; 1353 1354 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1355 if (!vco) { 1356 pr_err("%s: alpha pll not in a valid vco range\n", name); 1357 return -EINVAL; 1358 } 1359 1360 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1361 pll->vco_table[0].max_freq) * 54, 100); 1362 1363 parent_hw = clk_hw_get_parent(hw); 1364 if (!parent_hw) 1365 return -EINVAL; 1366 1367 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1368 &cal_l, &a, alpha_width); 1369 1370 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1371 if (ret < 0) 1372 return ret; 1373 1374 /* Setup PLL for calibration frequency */ 1375 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1376 1377 /* Bringup the PLL at calibration frequency */ 1378 ret = clk_alpha_pll_enable(hw); 1379 if (ret) { 1380 pr_err("%s: alpha pll calibration failed\n", name); 1381 return ret; 1382 } 1383 1384 clk_alpha_pll_disable(hw); 1385 1386 return 0; 1387} 1388 1389const struct clk_ops clk_alpha_pll_fabia_ops = { 1390 .prepare = alpha_pll_fabia_prepare, 1391 .enable = alpha_pll_fabia_enable, 1392 .disable = alpha_pll_fabia_disable, 1393 .is_enabled = clk_alpha_pll_is_enabled, 1394 .set_rate = alpha_pll_fabia_set_rate, 1395 .recalc_rate = alpha_pll_fabia_recalc_rate, 1396 .round_rate = clk_alpha_pll_round_rate, 1397}; 1398EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1399 1400const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1401 .enable = alpha_pll_fabia_enable, 1402 .disable = alpha_pll_fabia_disable, 1403 .is_enabled = clk_alpha_pll_is_enabled, 1404 .recalc_rate = alpha_pll_fabia_recalc_rate, 1405 .round_rate = clk_alpha_pll_round_rate, 1406}; 1407EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1408 1409static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1410 unsigned long parent_rate) 1411{ 1412 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1413 u32 i, div = 1, val; 1414 int ret; 1415 1416 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1417 if (ret) 1418 return ret; 1419 1420 val >>= pll->post_div_shift; 1421 val &= BIT(pll->width) - 1; 1422 1423 for (i = 0; i < pll->num_post_div; i++) { 1424 if (pll->post_div_table[i].val == val) { 1425 div = pll->post_div_table[i].div; 1426 break; 1427 } 1428 } 1429 1430 return (parent_rate / div); 1431} 1432 1433static unsigned long 1434clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1435{ 1436 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1437 struct regmap *regmap = pll->clkr.regmap; 1438 u32 i, div = 1, val; 1439 1440 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1441 1442 val >>= pll->post_div_shift; 1443 val &= PLL_POST_DIV_MASK(pll); 1444 1445 for (i = 0; i < pll->num_post_div; i++) { 1446 if (pll->post_div_table[i].val == val) { 1447 div = pll->post_div_table[i].div; 1448 break; 1449 } 1450 } 1451 1452 return (parent_rate / div); 1453} 1454 1455static long 1456clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1457 unsigned long *prate) 1458{ 1459 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1460 1461 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1462 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1463}; 1464 1465static int 1466clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1467 unsigned long parent_rate) 1468{ 1469 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1470 struct regmap *regmap = pll->clkr.regmap; 1471 int i, val = 0, div; 1472 1473 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1474 for (i = 0; i < pll->num_post_div; i++) { 1475 if (pll->post_div_table[i].div == div) { 1476 val = pll->post_div_table[i].val; 1477 break; 1478 } 1479 } 1480 1481 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1482 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1483 val << PLL_POST_DIV_SHIFT); 1484} 1485 1486const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1487 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1488 .round_rate = clk_trion_pll_postdiv_round_rate, 1489 .set_rate = clk_trion_pll_postdiv_set_rate, 1490}; 1491EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1492 1493static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1494 unsigned long rate, unsigned long *prate) 1495{ 1496 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1497 1498 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1499 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1500} 1501 1502static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1503 unsigned long rate, unsigned long parent_rate) 1504{ 1505 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1506 int i, val = 0, div, ret; 1507 1508 /* 1509 * If the PLL is in FSM mode, then treat set_rate callback as a 1510 * no-operation. 1511 */ 1512 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1513 if (ret) 1514 return ret; 1515 1516 if (val & PLL_VOTE_FSM_ENA) 1517 return 0; 1518 1519 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1520 for (i = 0; i < pll->num_post_div; i++) { 1521 if (pll->post_div_table[i].div == div) { 1522 val = pll->post_div_table[i].val; 1523 break; 1524 } 1525 } 1526 1527 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1528 (BIT(pll->width) - 1) << pll->post_div_shift, 1529 val << pll->post_div_shift); 1530} 1531 1532const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1533 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1534 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1535 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1536}; 1537EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1538 1539/** 1540 * clk_trion_pll_configure - configure the trion pll 1541 * 1542 * @pll: clk alpha pll 1543 * @regmap: register map 1544 * @config: configuration to apply for pll 1545 */ 1546void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1547 const struct alpha_pll_config *config) 1548{ 1549 /* 1550 * If the bootloader left the PLL enabled it's likely that there are 1551 * RCGs that will lock up if we disable the PLL below. 1552 */ 1553 if (trion_pll_is_enabled(pll, regmap)) { 1554 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1555 return; 1556 } 1557 1558 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1559 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1560 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1561 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1562 config->config_ctl_val); 1563 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1564 config->config_ctl_hi_val); 1565 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1566 config->config_ctl_hi1_val); 1567 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1568 config->user_ctl_val); 1569 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1570 config->user_ctl_hi_val); 1571 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1572 config->user_ctl_hi1_val); 1573 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1574 config->test_ctl_val); 1575 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1576 config->test_ctl_hi_val); 1577 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1578 config->test_ctl_hi1_val); 1579 1580 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1581 PLL_UPDATE_BYPASS); 1582 1583 /* Disable PLL output */ 1584 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1585 1586 /* Set operation mode to OFF */ 1587 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1588 1589 /* Place the PLL in STANDBY mode */ 1590 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1591} 1592EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1593 1594/* 1595 * The TRION PLL requires a power-on self-calibration which happens when the 1596 * PLL comes out of reset. Calibrate in case it is not completed. 1597 */ 1598static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1599{ 1600 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1601 u32 val; 1602 int ret; 1603 1604 /* Return early if calibration is not needed. */ 1605 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1606 if (val & pcal_done) 1607 return 0; 1608 1609 /* On/off to calibrate */ 1610 ret = clk_trion_pll_enable(hw); 1611 if (!ret) 1612 clk_trion_pll_disable(hw); 1613 1614 return ret; 1615} 1616 1617static int alpha_pll_trion_prepare(struct clk_hw *hw) 1618{ 1619 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1620} 1621 1622static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1623{ 1624 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1625} 1626 1627static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1628 unsigned long prate, u32 latch_bit, u32 latch_ack) 1629{ 1630 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1631 unsigned long rrate; 1632 u32 val, l, alpha_width = pll_alpha_width(pll); 1633 u64 a; 1634 int ret; 1635 1636 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1637 1638 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1639 if (ret < 0) 1640 return ret; 1641 1642 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1643 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1644 1645 /* Latch the PLL input */ 1646 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1647 if (ret) 1648 return ret; 1649 1650 /* Wait for 2 reference cycles before checking the ACK bit. */ 1651 udelay(1); 1652 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1653 if (!(val & latch_ack)) { 1654 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1655 return -EINVAL; 1656 } 1657 1658 /* Return the latch input to 0 */ 1659 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1660 if (ret) 1661 return ret; 1662 1663 if (clk_hw_is_enabled(hw)) { 1664 ret = wait_for_pll_enable_lock(pll); 1665 if (ret) 1666 return ret; 1667 } 1668 1669 /* Wait for PLL output to stabilize */ 1670 udelay(100); 1671 return 0; 1672} 1673 1674static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1675 unsigned long prate) 1676{ 1677 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1678} 1679 1680const struct clk_ops clk_alpha_pll_trion_ops = { 1681 .prepare = alpha_pll_trion_prepare, 1682 .enable = clk_trion_pll_enable, 1683 .disable = clk_trion_pll_disable, 1684 .is_enabled = clk_trion_pll_is_enabled, 1685 .recalc_rate = clk_trion_pll_recalc_rate, 1686 .round_rate = clk_alpha_pll_round_rate, 1687 .set_rate = alpha_pll_trion_set_rate, 1688}; 1689EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1690 1691const struct clk_ops clk_alpha_pll_lucid_ops = { 1692 .prepare = alpha_pll_lucid_prepare, 1693 .enable = clk_trion_pll_enable, 1694 .disable = clk_trion_pll_disable, 1695 .is_enabled = clk_trion_pll_is_enabled, 1696 .recalc_rate = clk_trion_pll_recalc_rate, 1697 .round_rate = clk_alpha_pll_round_rate, 1698 .set_rate = alpha_pll_trion_set_rate, 1699}; 1700EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1701 1702const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1703 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1704 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1705 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1706}; 1707EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1708 1709void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1710 const struct alpha_pll_config *config) 1711{ 1712 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1713 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1714 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1715 config->user_ctl_val); 1716 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1717 config->config_ctl_val); 1718 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1719 config->config_ctl_hi_val); 1720 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1721 config->test_ctl_val); 1722 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1723 config->test_ctl_hi_val); 1724} 1725EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1726 1727static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1728 unsigned long prate) 1729{ 1730 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1731 u32 l, alpha_width = pll_alpha_width(pll); 1732 int ret; 1733 unsigned long rrate; 1734 u64 a; 1735 1736 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1737 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1738 if (ret < 0) 1739 return ret; 1740 1741 /* change L_VAL without having to go through the power on sequence */ 1742 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1743 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1744 1745 if (clk_hw_is_enabled(hw)) 1746 return wait_for_pll_enable_lock(pll); 1747 1748 return 0; 1749} 1750 1751const struct clk_ops clk_alpha_pll_agera_ops = { 1752 .enable = clk_alpha_pll_enable, 1753 .disable = clk_alpha_pll_disable, 1754 .is_enabled = clk_alpha_pll_is_enabled, 1755 .recalc_rate = alpha_pll_fabia_recalc_rate, 1756 .round_rate = clk_alpha_pll_round_rate, 1757 .set_rate = clk_alpha_pll_agera_set_rate, 1758}; 1759EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1760 1761static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1762{ 1763 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1764 u32 val; 1765 int ret; 1766 1767 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1768 if (ret) 1769 return ret; 1770 1771 /* If in FSM mode, just vote for it */ 1772 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1773 ret = clk_enable_regmap(hw); 1774 if (ret) 1775 return ret; 1776 return wait_for_pll_enable_lock(pll); 1777 } 1778 1779 /* Check if PLL is already enabled, return if enabled */ 1780 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1781 if (ret < 0) 1782 return ret; 1783 1784 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1785 if (ret) 1786 return ret; 1787 1788 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1789 1790 ret = wait_for_pll_enable_lock(pll); 1791 if (ret) 1792 return ret; 1793 1794 /* Enable the PLL outputs */ 1795 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1796 if (ret) 1797 return ret; 1798 1799 /* Enable the global PLL outputs */ 1800 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1801} 1802 1803static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1804{ 1805 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1806 u32 val; 1807 int ret; 1808 1809 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1810 if (ret) 1811 return; 1812 1813 /* If in FSM mode, just unvote it */ 1814 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1815 clk_disable_regmap(hw); 1816 return; 1817 } 1818 1819 /* Disable the global PLL output */ 1820 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1821 if (ret) 1822 return; 1823 1824 /* Disable the PLL outputs */ 1825 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1826 if (ret) 1827 return; 1828 1829 /* Place the PLL mode in STANDBY */ 1830 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1831} 1832 1833/* 1834 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1835 * when the PLL comes out of reset. Calibrate in case it is not completed. 1836 */ 1837static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1838{ 1839 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1840 struct clk_hw *p; 1841 u32 val = 0; 1842 int ret; 1843 1844 /* Return early if calibration is not needed. */ 1845 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1846 if (val & LUCID_5LPE_PCAL_DONE) 1847 return 0; 1848 1849 p = clk_hw_get_parent(hw); 1850 if (!p) 1851 return -EINVAL; 1852 1853 ret = alpha_pll_lucid_5lpe_enable(hw); 1854 if (ret) 1855 return ret; 1856 1857 alpha_pll_lucid_5lpe_disable(hw); 1858 1859 return 0; 1860} 1861 1862static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1863 unsigned long prate) 1864{ 1865 return __alpha_pll_trion_set_rate(hw, rate, prate, 1866 LUCID_5LPE_PLL_LATCH_INPUT, 1867 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1868} 1869 1870static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1871 unsigned long parent_rate, 1872 unsigned long enable_vote_run) 1873{ 1874 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1875 struct regmap *regmap = pll->clkr.regmap; 1876 int i, val, div, ret; 1877 u32 mask; 1878 1879 /* 1880 * If the PLL is in FSM mode, then treat set_rate callback as a 1881 * no-operation. 1882 */ 1883 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1884 if (ret) 1885 return ret; 1886 1887 if (val & enable_vote_run) 1888 return 0; 1889 1890 if (!pll->post_div_table) { 1891 pr_err("Missing the post_div_table for the %s PLL\n", 1892 clk_hw_get_name(&pll->clkr.hw)); 1893 return -EINVAL; 1894 } 1895 1896 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1897 for (i = 0; i < pll->num_post_div; i++) { 1898 if (pll->post_div_table[i].div == div) { 1899 val = pll->post_div_table[i].val; 1900 break; 1901 } 1902 } 1903 1904 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1905 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1906 mask, val << pll->post_div_shift); 1907} 1908 1909static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1910 unsigned long parent_rate) 1911{ 1912 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1913} 1914 1915const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1916 .prepare = alpha_pll_lucid_5lpe_prepare, 1917 .enable = alpha_pll_lucid_5lpe_enable, 1918 .disable = alpha_pll_lucid_5lpe_disable, 1919 .is_enabled = clk_trion_pll_is_enabled, 1920 .recalc_rate = clk_trion_pll_recalc_rate, 1921 .round_rate = clk_alpha_pll_round_rate, 1922 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1923}; 1924EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1925 1926const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1927 .enable = alpha_pll_lucid_5lpe_enable, 1928 .disable = alpha_pll_lucid_5lpe_disable, 1929 .is_enabled = clk_trion_pll_is_enabled, 1930 .recalc_rate = clk_trion_pll_recalc_rate, 1931 .round_rate = clk_alpha_pll_round_rate, 1932}; 1933EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1934 1935const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1936 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1937 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1938 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1939}; 1940EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1941 1942void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1943 const struct alpha_pll_config *config) 1944{ 1945 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1946 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1947 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 1949 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 1950 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 1951 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 1952 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 1953 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 1954 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 1955 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 1956 1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 1958 1959 /* Disable PLL output */ 1960 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1961 1962 /* Set operation mode to OFF */ 1963 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1964 1965 /* Place the PLL in STANDBY mode */ 1966 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1967} 1968EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 1969 1970static int clk_zonda_pll_enable(struct clk_hw *hw) 1971{ 1972 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1973 struct regmap *regmap = pll->clkr.regmap; 1974 u32 val; 1975 int ret; 1976 1977 regmap_read(regmap, PLL_MODE(pll), &val); 1978 1979 /* If in FSM mode, just vote for it */ 1980 if (val & PLL_VOTE_FSM_ENA) { 1981 ret = clk_enable_regmap(hw); 1982 if (ret) 1983 return ret; 1984 return wait_for_pll_enable_active(pll); 1985 } 1986 1987 /* Get the PLL out of bypass mode */ 1988 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 1989 1990 /* 1991 * H/W requires a 1us delay between disabling the bypass and 1992 * de-asserting the reset. 1993 */ 1994 udelay(1); 1995 1996 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1997 1998 /* Set operation mode to RUN */ 1999 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2000 2001 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2002 2003 /* If cfa mode then poll for freq lock */ 2004 if (val & ZONDA_STAY_IN_CFA) 2005 ret = wait_for_zonda_pll_freq_lock(pll); 2006 else 2007 ret = wait_for_pll_enable_lock(pll); 2008 if (ret) 2009 return ret; 2010 2011 /* Enable the PLL outputs */ 2012 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2013 2014 /* Enable the global PLL outputs */ 2015 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2016 2017 return 0; 2018} 2019 2020static void clk_zonda_pll_disable(struct clk_hw *hw) 2021{ 2022 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2023 struct regmap *regmap = pll->clkr.regmap; 2024 u32 val; 2025 2026 regmap_read(regmap, PLL_MODE(pll), &val); 2027 2028 /* If in FSM mode, just unvote it */ 2029 if (val & PLL_VOTE_FSM_ENA) { 2030 clk_disable_regmap(hw); 2031 return; 2032 } 2033 2034 /* Disable the global PLL output */ 2035 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2036 2037 /* Disable the PLL outputs */ 2038 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2039 2040 /* Put the PLL in bypass and reset */ 2041 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2042 2043 /* Place the PLL mode in OFF state */ 2044 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2045} 2046 2047static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2048 unsigned long prate) 2049{ 2050 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2051 unsigned long rrate; 2052 u32 test_ctl_val; 2053 u32 l, alpha_width = pll_alpha_width(pll); 2054 u64 a; 2055 int ret; 2056 2057 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2058 2059 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2060 if (ret < 0) 2061 return ret; 2062 2063 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2064 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2065 2066 /* Wait before polling for the frequency latch */ 2067 udelay(5); 2068 2069 /* Read stay in cfa mode */ 2070 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2071 2072 /* If cfa mode then poll for freq lock */ 2073 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2074 ret = wait_for_zonda_pll_freq_lock(pll); 2075 else 2076 ret = wait_for_pll_enable_lock(pll); 2077 if (ret) 2078 return ret; 2079 2080 /* Wait for PLL output to stabilize */ 2081 udelay(100); 2082 return 0; 2083} 2084 2085const struct clk_ops clk_alpha_pll_zonda_ops = { 2086 .enable = clk_zonda_pll_enable, 2087 .disable = clk_zonda_pll_disable, 2088 .is_enabled = clk_trion_pll_is_enabled, 2089 .recalc_rate = clk_trion_pll_recalc_rate, 2090 .round_rate = clk_alpha_pll_round_rate, 2091 .set_rate = clk_zonda_pll_set_rate, 2092}; 2093EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2094 2095void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2096 const struct alpha_pll_config *config) 2097{ 2098 u32 lval = config->l; 2099 2100 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2101 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2102 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2103 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2104 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2105 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2106 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2107 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2108 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2109 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2110 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2111 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2112 2113 /* Disable PLL output */ 2114 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2115 2116 /* Set operation mode to STANDBY and de-assert the reset */ 2117 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2118 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2119} 2120EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2121 2122static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2123{ 2124 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2125 struct regmap *regmap = pll->clkr.regmap; 2126 u32 val; 2127 int ret; 2128 2129 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2130 if (ret) 2131 return ret; 2132 2133 /* If in FSM mode, just vote for it */ 2134 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2135 ret = clk_enable_regmap(hw); 2136 if (ret) 2137 return ret; 2138 return wait_for_pll_enable_lock(pll); 2139 } 2140 2141 /* Check if PLL is already enabled */ 2142 ret = trion_pll_is_enabled(pll, regmap); 2143 if (ret < 0) { 2144 return ret; 2145 } else if (ret) { 2146 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2147 return 0; 2148 } 2149 2150 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2151 if (ret) 2152 return ret; 2153 2154 /* Set operation mode to RUN */ 2155 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2156 2157 ret = wait_for_pll_enable_lock(pll); 2158 if (ret) 2159 return ret; 2160 2161 /* Enable the PLL outputs */ 2162 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2163 if (ret) 2164 return ret; 2165 2166 /* Enable the global PLL outputs */ 2167 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2168 if (ret) 2169 return ret; 2170 2171 /* Ensure that the write above goes through before returning. */ 2172 mb(); 2173 return ret; 2174} 2175 2176static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2177{ 2178 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2179 struct regmap *regmap = pll->clkr.regmap; 2180 u32 val; 2181 int ret; 2182 2183 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2184 if (ret) 2185 return; 2186 2187 /* If in FSM mode, just unvote it */ 2188 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2189 clk_disable_regmap(hw); 2190 return; 2191 } 2192 2193 /* Disable the global PLL output */ 2194 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2195 if (ret) 2196 return; 2197 2198 /* Disable the PLL outputs */ 2199 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2200 if (ret) 2201 return; 2202 2203 /* Place the PLL mode in STANDBY */ 2204 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2205 2206 if (reset) 2207 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2208} 2209 2210static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2211{ 2212 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2213 struct clk_hw *p; 2214 u32 val = 0; 2215 int ret; 2216 2217 /* Return early if calibration is not needed. */ 2218 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2219 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2220 return 0; 2221 2222 p = clk_hw_get_parent(hw); 2223 if (!p) 2224 return -EINVAL; 2225 2226 ret = alpha_pll_lucid_evo_enable(hw); 2227 if (ret) 2228 return ret; 2229 2230 _alpha_pll_lucid_evo_disable(hw, reset); 2231 2232 return 0; 2233} 2234 2235static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2236{ 2237 _alpha_pll_lucid_evo_disable(hw, false); 2238} 2239 2240static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2241{ 2242 return _alpha_pll_lucid_evo_prepare(hw, false); 2243} 2244 2245static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2246{ 2247 _alpha_pll_lucid_evo_disable(hw, true); 2248} 2249 2250static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2251{ 2252 return _alpha_pll_lucid_evo_prepare(hw, true); 2253} 2254 2255static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2256 unsigned long parent_rate) 2257{ 2258 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2259 struct regmap *regmap = pll->clkr.regmap; 2260 u32 l, frac; 2261 2262 regmap_read(regmap, PLL_L_VAL(pll), &l); 2263 l &= LUCID_EVO_PLL_L_VAL_MASK; 2264 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2265 2266 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2267} 2268 2269static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2270 unsigned long parent_rate) 2271{ 2272 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2273} 2274 2275const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2276 .enable = alpha_pll_lucid_evo_enable, 2277 .disable = alpha_pll_lucid_evo_disable, 2278 .is_enabled = clk_trion_pll_is_enabled, 2279 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2280 .round_rate = clk_alpha_pll_round_rate, 2281}; 2282EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2283 2284const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2285 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2286 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2287 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2288}; 2289EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2290 2291const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2292 .prepare = alpha_pll_lucid_evo_prepare, 2293 .enable = alpha_pll_lucid_evo_enable, 2294 .disable = alpha_pll_lucid_evo_disable, 2295 .is_enabled = clk_trion_pll_is_enabled, 2296 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2297 .round_rate = clk_alpha_pll_round_rate, 2298 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2299}; 2300EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2301 2302const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2303 .prepare = alpha_pll_reset_lucid_evo_prepare, 2304 .enable = alpha_pll_lucid_evo_enable, 2305 .disable = alpha_pll_reset_lucid_evo_disable, 2306 .is_enabled = clk_trion_pll_is_enabled, 2307 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2308 .round_rate = clk_alpha_pll_round_rate, 2309 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2310}; 2311EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2312 2313void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2314 const struct alpha_pll_config *config) 2315{ 2316 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2317 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2318 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2319 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2320 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2321 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2322 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2323 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2324 2325 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2326 2327 regmap_update_bits(regmap, PLL_MODE(pll), 2328 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2329 PLL_RESET_N | PLL_BYPASSNL); 2330} 2331EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2332 2333static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2334 unsigned long parent_rate) 2335{ 2336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2337 u32 l; 2338 2339 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2340 2341 return parent_rate * l; 2342} 2343 2344static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2345 unsigned long *prate) 2346{ 2347 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2348 unsigned long min_freq, max_freq; 2349 u32 l; 2350 u64 a; 2351 2352 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2353 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2354 return rate; 2355 2356 min_freq = pll->vco_table[0].min_freq; 2357 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2358 2359 return clamp(rate, min_freq, max_freq); 2360} 2361 2362const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2363 .enable = alpha_pll_lucid_5lpe_enable, 2364 .disable = alpha_pll_lucid_5lpe_disable, 2365 .is_enabled = clk_trion_pll_is_enabled, 2366 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2367 .round_rate = clk_rivian_evo_pll_round_rate, 2368}; 2369EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2370 2371void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2372 const struct alpha_pll_config *config) 2373{ 2374 u32 val, val_u, mask, mask_u; 2375 2376 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2377 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2378 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2379 2380 if (pll_has_64bit_config(pll)) 2381 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2382 config->config_ctl_hi_val); 2383 2384 if (pll_alpha_width(pll) > 32) 2385 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2386 2387 val = config->main_output_mask; 2388 val |= config->aux_output_mask; 2389 val |= config->aux2_output_mask; 2390 val |= config->early_output_mask; 2391 val |= config->pre_div_val; 2392 val |= config->post_div_val; 2393 val |= config->vco_val; 2394 val |= config->alpha_en_mask; 2395 val |= config->alpha_mode_mask; 2396 2397 mask = config->main_output_mask; 2398 mask |= config->aux_output_mask; 2399 mask |= config->aux2_output_mask; 2400 mask |= config->early_output_mask; 2401 mask |= config->pre_div_mask; 2402 mask |= config->post_div_mask; 2403 mask |= config->vco_mask; 2404 mask |= config->alpha_en_mask; 2405 mask |= config->alpha_mode_mask; 2406 2407 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2408 2409 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2410 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2411 val_u |= config->lock_det; 2412 2413 mask_u = config->status_mask; 2414 mask_u |= config->lock_det; 2415 2416 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2417 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2418 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2419 2420 if (pll->flags & SUPPORTS_FSM_MODE) 2421 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2422} 2423EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2424 2425static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2426 struct clk_rate_request *req) 2427{ 2428 u32 l; 2429 u64 a; 2430 2431 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2432 &l, &a, ALPHA_REG_BITWIDTH); 2433 2434 return 0; 2435} 2436 2437static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2438 unsigned long prate) 2439{ 2440 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2441 int ret; 2442 u32 l; 2443 u64 a; 2444 2445 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2446 2447 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2448 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2449 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2450 a >> ALPHA_BITWIDTH); 2451 2452 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2453 PLL_ALPHA_EN, PLL_ALPHA_EN); 2454 2455 if (!clk_hw_is_enabled(hw)) 2456 return 0; 2457 2458 /* 2459 * Stromer PLL supports Dynamic programming. 2460 * It allows the PLL frequency to be changed on-the-fly without first 2461 * execution of a shutdown procedure followed by a bring up procedure. 2462 */ 2463 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2464 PLL_UPDATE); 2465 2466 ret = wait_for_pll_update(pll); 2467 if (ret) 2468 return ret; 2469 2470 return wait_for_pll_enable_lock(pll); 2471} 2472 2473const struct clk_ops clk_alpha_pll_stromer_ops = { 2474 .enable = clk_alpha_pll_enable, 2475 .disable = clk_alpha_pll_disable, 2476 .is_enabled = clk_alpha_pll_is_enabled, 2477 .recalc_rate = clk_alpha_pll_recalc_rate, 2478 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2479 .set_rate = clk_alpha_pll_stromer_set_rate, 2480}; 2481EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2482 2483static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2484 unsigned long rate, 2485 unsigned long prate) 2486{ 2487 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2488 u32 l, alpha_width = pll_alpha_width(pll); 2489 int ret, pll_mode; 2490 u64 a; 2491 2492 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2493 2494 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2495 if (ret) 2496 return ret; 2497 2498 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2499 2500 /* Delay of 2 output clock ticks required until output is disabled */ 2501 udelay(1); 2502 2503 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2504 2505 if (alpha_width > ALPHA_BITWIDTH) 2506 a <<= alpha_width - ALPHA_BITWIDTH; 2507 2508 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2509 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2510 a >> ALPHA_BITWIDTH); 2511 2512 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2513 2514 /* Wait five micro seconds or more */ 2515 udelay(5); 2516 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2517 PLL_RESET_N); 2518 2519 /* The lock time should be less than 50 micro seconds worst case */ 2520 usleep_range(50, 60); 2521 2522 ret = wait_for_pll_enable_lock(pll); 2523 if (ret) { 2524 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2525 clk_hw_get_name(hw), ret); 2526 return ret; 2527 } 2528 2529 if (pll_mode & PLL_OUTCTRL) 2530 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2531 PLL_OUTCTRL); 2532 2533 return 0; 2534} 2535 2536const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2537 .prepare = clk_alpha_pll_enable, 2538 .unprepare = clk_alpha_pll_disable, 2539 .is_enabled = clk_alpha_pll_is_enabled, 2540 .recalc_rate = clk_alpha_pll_recalc_rate, 2541 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2542 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2543}; 2544EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2545