1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk-provider.h> 7#include <linux/module.h> 8#include <linux/platform_device.h> 9#include <linux/regmap.h> 10 11#include <dt-bindings/clock/qcom,camcc-sdm845.h> 12 13#include "common.h" 14#include "clk-alpha-pll.h" 15#include "clk-branch.h" 16#include "clk-rcg.h" 17#include "clk-regmap.h" 18#include "gdsc.h" 19 20enum { 21 P_BI_TCXO, 22 P_CAM_CC_PLL0_OUT_EVEN, 23 P_CAM_CC_PLL1_OUT_EVEN, 24 P_CAM_CC_PLL2_OUT_EVEN, 25 P_CAM_CC_PLL3_OUT_EVEN, 26}; 27 28static struct clk_alpha_pll cam_cc_pll0 = { 29 .offset = 0x0, 30 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 31 .clkr = { 32 .hw.init = &(struct clk_init_data){ 33 .name = "cam_cc_pll0", 34 .parent_data = &(const struct clk_parent_data){ 35 .fw_name = "bi_tcxo", .name = "bi_tcxo", 36 }, 37 .num_parents = 1, 38 .ops = &clk_alpha_pll_fabia_ops, 39 }, 40 }, 41}; 42 43static const struct clk_div_table post_div_table_fabia_even[] = { 44 { 0x0, 1 }, 45 { 0x1, 2 }, 46 { } 47}; 48 49static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 50 .offset = 0x0, 51 .post_div_shift = 8, 52 .post_div_table = post_div_table_fabia_even, 53 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 54 .width = 4, 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 56 .clkr.hw.init = &(struct clk_init_data){ 57 .name = "cam_cc_pll0_out_even", 58 .parent_hws = (const struct clk_hw*[]){ 59 &cam_cc_pll0.clkr.hw, 60 }, 61 .num_parents = 1, 62 .ops = &clk_alpha_pll_postdiv_fabia_ops, 63 }, 64}; 65 66static struct clk_alpha_pll cam_cc_pll1 = { 67 .offset = 0x1000, 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 69 .clkr = { 70 .hw.init = &(struct clk_init_data){ 71 .name = "cam_cc_pll1", 72 .parent_data = &(const struct clk_parent_data){ 73 .fw_name = "bi_tcxo", .name = "bi_tcxo", 74 }, 75 .num_parents = 1, 76 .ops = &clk_alpha_pll_fabia_ops, 77 }, 78 }, 79}; 80 81static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 82 .offset = 0x1000, 83 .post_div_shift = 8, 84 .post_div_table = post_div_table_fabia_even, 85 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 86 .width = 4, 87 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 88 .clkr.hw.init = &(struct clk_init_data){ 89 .name = "cam_cc_pll1_out_even", 90 .parent_hws = (const struct clk_hw*[]){ 91 &cam_cc_pll1.clkr.hw, 92 }, 93 .num_parents = 1, 94 .ops = &clk_alpha_pll_postdiv_fabia_ops, 95 }, 96}; 97 98static struct clk_alpha_pll cam_cc_pll2 = { 99 .offset = 0x2000, 100 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 101 .clkr = { 102 .hw.init = &(struct clk_init_data){ 103 .name = "cam_cc_pll2", 104 .parent_data = &(const struct clk_parent_data){ 105 .fw_name = "bi_tcxo", .name = "bi_tcxo", 106 }, 107 .num_parents = 1, 108 .ops = &clk_alpha_pll_fabia_ops, 109 }, 110 }, 111}; 112 113static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { 114 .offset = 0x2000, 115 .post_div_shift = 8, 116 .post_div_table = post_div_table_fabia_even, 117 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 118 .width = 4, 119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 120 .clkr.hw.init = &(struct clk_init_data){ 121 .name = "cam_cc_pll2_out_even", 122 .parent_hws = (const struct clk_hw*[]){ 123 &cam_cc_pll2.clkr.hw, 124 }, 125 .num_parents = 1, 126 .ops = &clk_alpha_pll_postdiv_fabia_ops, 127 }, 128}; 129 130static struct clk_alpha_pll cam_cc_pll3 = { 131 .offset = 0x3000, 132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 133 .clkr = { 134 .hw.init = &(struct clk_init_data){ 135 .name = "cam_cc_pll3", 136 .parent_data = &(const struct clk_parent_data){ 137 .fw_name = "bi_tcxo", .name = "bi_tcxo", 138 }, 139 .num_parents = 1, 140 .ops = &clk_alpha_pll_fabia_ops, 141 }, 142 }, 143}; 144 145static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 146 .offset = 0x3000, 147 .post_div_shift = 8, 148 .post_div_table = post_div_table_fabia_even, 149 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 150 .width = 4, 151 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 152 .clkr.hw.init = &(struct clk_init_data){ 153 .name = "cam_cc_pll3_out_even", 154 .parent_hws = (const struct clk_hw*[]){ 155 &cam_cc_pll3.clkr.hw, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_postdiv_fabia_ops, 159 }, 160}; 161 162static const struct parent_map cam_cc_parent_map_0[] = { 163 { P_BI_TCXO, 0 }, 164 { P_CAM_CC_PLL2_OUT_EVEN, 1 }, 165 { P_CAM_CC_PLL1_OUT_EVEN, 2 }, 166 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 167 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 168}; 169 170static const struct clk_parent_data cam_cc_parent_data_0[] = { 171 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 172 { .hw = &cam_cc_pll2_out_even.clkr.hw }, 173 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 174 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 175 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 176}; 177 178static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 179 F(19200000, P_BI_TCXO, 1, 0, 0), 180 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 181 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 182 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 183 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 184 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 185 { } 186}; 187 188/* 189 * As per HW design, some of the CAMCC RCGs needs to 190 * move to XO clock during their clock disable so using 191 * clk_rcg2_shared_ops for such RCGs. This is required 192 * to power down the camera memories gracefully. 193 * Also, use CLK_SET_RATE_PARENT flag for the RCGs which 194 * have CAM_CC_PLL2_OUT_EVEN PLL as parent in frequency 195 * table and requires reconfiguration of the PLL frequency. 196 */ 197static struct clk_rcg2 cam_cc_bps_clk_src = { 198 .cmd_rcgr = 0x600c, 199 .mnd_width = 0, 200 .hid_width = 5, 201 .parent_map = cam_cc_parent_map_0, 202 .freq_tbl = ftbl_cam_cc_bps_clk_src, 203 .clkr.hw.init = &(struct clk_init_data){ 204 .name = "cam_cc_bps_clk_src", 205 .parent_data = cam_cc_parent_data_0, 206 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 207 .flags = CLK_SET_RATE_PARENT, 208 .ops = &clk_rcg2_shared_ops, 209 }, 210}; 211 212static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = { 213 F(19200000, P_BI_TCXO, 1, 0, 0), 214 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 215 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 216 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 217 { } 218}; 219 220static struct clk_rcg2 cam_cc_cci_clk_src = { 221 .cmd_rcgr = 0xb0d8, 222 .mnd_width = 8, 223 .hid_width = 5, 224 .parent_map = cam_cc_parent_map_0, 225 .freq_tbl = ftbl_cam_cc_cci_clk_src, 226 .clkr.hw.init = &(struct clk_init_data){ 227 .name = "cam_cc_cci_clk_src", 228 .parent_data = cam_cc_parent_data_0, 229 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 230 .ops = &clk_rcg2_ops, 231 }, 232}; 233 234static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 235 F(19200000, P_BI_TCXO, 1, 0, 0), 236 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 237 { } 238}; 239 240static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 241 .cmd_rcgr = 0x9060, 242 .mnd_width = 0, 243 .hid_width = 5, 244 .parent_map = cam_cc_parent_map_0, 245 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 246 .clkr.hw.init = &(struct clk_init_data){ 247 .name = "cam_cc_cphy_rx_clk_src", 248 .parent_data = cam_cc_parent_data_0, 249 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 250 .ops = &clk_rcg2_ops, 251 }, 252}; 253 254static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 255 F(19200000, P_BI_TCXO, 1, 0, 0), 256 F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0), 257 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0), 258 { } 259}; 260 261static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 262 .cmd_rcgr = 0x5004, 263 .mnd_width = 0, 264 .hid_width = 5, 265 .parent_map = cam_cc_parent_map_0, 266 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 267 .clkr.hw.init = &(struct clk_init_data){ 268 .name = "cam_cc_csi0phytimer_clk_src", 269 .parent_data = cam_cc_parent_data_0, 270 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 271 .flags = CLK_SET_RATE_PARENT, 272 .ops = &clk_rcg2_ops, 273 }, 274}; 275 276static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 277 .cmd_rcgr = 0x5028, 278 .mnd_width = 0, 279 .hid_width = 5, 280 .parent_map = cam_cc_parent_map_0, 281 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 282 .clkr.hw.init = &(struct clk_init_data){ 283 .name = "cam_cc_csi1phytimer_clk_src", 284 .parent_data = cam_cc_parent_data_0, 285 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 286 .flags = CLK_SET_RATE_PARENT, 287 .ops = &clk_rcg2_ops, 288 }, 289}; 290 291static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 292 .cmd_rcgr = 0x504c, 293 .mnd_width = 0, 294 .hid_width = 5, 295 .parent_map = cam_cc_parent_map_0, 296 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 297 .clkr.hw.init = &(struct clk_init_data){ 298 .name = "cam_cc_csi2phytimer_clk_src", 299 .parent_data = cam_cc_parent_data_0, 300 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 301 .flags = CLK_SET_RATE_PARENT, 302 .ops = &clk_rcg2_ops, 303 }, 304}; 305 306static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 307 .cmd_rcgr = 0x5070, 308 .mnd_width = 0, 309 .hid_width = 5, 310 .parent_map = cam_cc_parent_map_0, 311 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 312 .clkr.hw.init = &(struct clk_init_data){ 313 .name = "cam_cc_csi3phytimer_clk_src", 314 .parent_data = cam_cc_parent_data_0, 315 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 316 .flags = CLK_SET_RATE_PARENT, 317 .ops = &clk_rcg2_ops, 318 }, 319}; 320 321static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 322 F(19200000, P_BI_TCXO, 1, 0, 0), 323 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 324 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 325 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 326 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 327 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 328 { } 329}; 330 331static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 332 .cmd_rcgr = 0x6038, 333 .mnd_width = 0, 334 .hid_width = 5, 335 .parent_map = cam_cc_parent_map_0, 336 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 337 .clkr.hw.init = &(struct clk_init_data){ 338 .name = "cam_cc_fast_ahb_clk_src", 339 .parent_data = cam_cc_parent_data_0, 340 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 341 .ops = &clk_rcg2_ops, 342 }, 343}; 344 345static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 346 F(19200000, P_BI_TCXO, 1, 0, 0), 347 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 348 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 349 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 350 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 351 { } 352}; 353 354static struct clk_rcg2 cam_cc_fd_core_clk_src = { 355 .cmd_rcgr = 0xb0b0, 356 .mnd_width = 0, 357 .hid_width = 5, 358 .parent_map = cam_cc_parent_map_0, 359 .freq_tbl = ftbl_cam_cc_fd_core_clk_src, 360 .clkr.hw.init = &(struct clk_init_data){ 361 .name = "cam_cc_fd_core_clk_src", 362 .parent_data = cam_cc_parent_data_0, 363 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 364 .ops = &clk_rcg2_shared_ops, 365 }, 366}; 367 368static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 369 F(19200000, P_BI_TCXO, 1, 0, 0), 370 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 371 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 372 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 373 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 374 { } 375}; 376 377static struct clk_rcg2 cam_cc_icp_clk_src = { 378 .cmd_rcgr = 0xb088, 379 .mnd_width = 0, 380 .hid_width = 5, 381 .parent_map = cam_cc_parent_map_0, 382 .freq_tbl = ftbl_cam_cc_icp_clk_src, 383 .clkr.hw.init = &(struct clk_init_data){ 384 .name = "cam_cc_icp_clk_src", 385 .parent_data = cam_cc_parent_data_0, 386 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 387 .ops = &clk_rcg2_shared_ops, 388 }, 389}; 390 391static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { 392 F(19200000, P_BI_TCXO, 1, 0, 0), 393 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 394 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0), 395 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 396 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 397 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 398 { } 399}; 400 401static struct clk_rcg2 cam_cc_ife_0_clk_src = { 402 .cmd_rcgr = 0x900c, 403 .mnd_width = 0, 404 .hid_width = 5, 405 .parent_map = cam_cc_parent_map_0, 406 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 407 .clkr.hw.init = &(struct clk_init_data){ 408 .name = "cam_cc_ife_0_clk_src", 409 .parent_data = cam_cc_parent_data_0, 410 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 411 .flags = CLK_SET_RATE_PARENT, 412 .ops = &clk_rcg2_shared_ops, 413 }, 414}; 415 416static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { 417 F(19200000, P_BI_TCXO, 1, 0, 0), 418 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), 419 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 420 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 421 { } 422}; 423 424static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { 425 .cmd_rcgr = 0x9038, 426 .mnd_width = 0, 427 .hid_width = 5, 428 .parent_map = cam_cc_parent_map_0, 429 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 430 .clkr.hw.init = &(struct clk_init_data){ 431 .name = "cam_cc_ife_0_csid_clk_src", 432 .parent_data = cam_cc_parent_data_0, 433 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 434 .ops = &clk_rcg2_shared_ops, 435 }, 436}; 437 438static struct clk_rcg2 cam_cc_ife_1_clk_src = { 439 .cmd_rcgr = 0xa00c, 440 .mnd_width = 0, 441 .hid_width = 5, 442 .parent_map = cam_cc_parent_map_0, 443 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 444 .clkr.hw.init = &(struct clk_init_data){ 445 .name = "cam_cc_ife_1_clk_src", 446 .parent_data = cam_cc_parent_data_0, 447 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 448 .flags = CLK_SET_RATE_PARENT, 449 .ops = &clk_rcg2_shared_ops, 450 }, 451}; 452 453static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 454 .cmd_rcgr = 0xa030, 455 .mnd_width = 0, 456 .hid_width = 5, 457 .parent_map = cam_cc_parent_map_0, 458 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 459 .clkr.hw.init = &(struct clk_init_data){ 460 .name = "cam_cc_ife_1_csid_clk_src", 461 .parent_data = cam_cc_parent_data_0, 462 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 463 .ops = &clk_rcg2_shared_ops, 464 }, 465}; 466 467static struct clk_rcg2 cam_cc_ife_lite_clk_src = { 468 .cmd_rcgr = 0xb004, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = cam_cc_parent_map_0, 472 .freq_tbl = ftbl_cam_cc_ife_0_clk_src, 473 .clkr.hw.init = &(struct clk_init_data){ 474 .name = "cam_cc_ife_lite_clk_src", 475 .parent_data = cam_cc_parent_data_0, 476 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 477 .flags = CLK_SET_RATE_PARENT, 478 .ops = &clk_rcg2_shared_ops, 479 }, 480}; 481 482static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 483 .cmd_rcgr = 0xb024, 484 .mnd_width = 0, 485 .hid_width = 5, 486 .parent_map = cam_cc_parent_map_0, 487 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, 488 .clkr.hw.init = &(struct clk_init_data){ 489 .name = "cam_cc_ife_lite_csid_clk_src", 490 .parent_data = cam_cc_parent_data_0, 491 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 492 .ops = &clk_rcg2_shared_ops, 493 }, 494}; 495 496static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { 497 F(19200000, P_BI_TCXO, 1, 0, 0), 498 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 499 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 500 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), 501 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), 502 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0), 503 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), 504 { } 505}; 506 507static struct clk_rcg2 cam_cc_ipe_0_clk_src = { 508 .cmd_rcgr = 0x700c, 509 .mnd_width = 0, 510 .hid_width = 5, 511 .parent_map = cam_cc_parent_map_0, 512 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 513 .clkr.hw.init = &(struct clk_init_data){ 514 .name = "cam_cc_ipe_0_clk_src", 515 .parent_data = cam_cc_parent_data_0, 516 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 517 .flags = CLK_SET_RATE_PARENT, 518 .ops = &clk_rcg2_shared_ops, 519 }, 520}; 521 522static struct clk_rcg2 cam_cc_ipe_1_clk_src = { 523 .cmd_rcgr = 0x800c, 524 .mnd_width = 0, 525 .hid_width = 5, 526 .parent_map = cam_cc_parent_map_0, 527 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, 528 .clkr.hw.init = &(struct clk_init_data){ 529 .name = "cam_cc_ipe_1_clk_src", 530 .parent_data = cam_cc_parent_data_0, 531 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 532 .flags = CLK_SET_RATE_PARENT, 533 .ops = &clk_rcg2_shared_ops, 534 }, 535}; 536 537static struct clk_rcg2 cam_cc_jpeg_clk_src = { 538 .cmd_rcgr = 0xb04c, 539 .mnd_width = 0, 540 .hid_width = 5, 541 .parent_map = cam_cc_parent_map_0, 542 .freq_tbl = ftbl_cam_cc_bps_clk_src, 543 .clkr.hw.init = &(struct clk_init_data){ 544 .name = "cam_cc_jpeg_clk_src", 545 .parent_data = cam_cc_parent_data_0, 546 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 547 .flags = CLK_SET_RATE_PARENT, 548 .ops = &clk_rcg2_shared_ops, 549 }, 550}; 551 552static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 553 F(19200000, P_BI_TCXO, 1, 0, 0), 554 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 555 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 556 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0), 557 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0), 558 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 559 { } 560}; 561 562static struct clk_rcg2 cam_cc_lrme_clk_src = { 563 .cmd_rcgr = 0xb0f8, 564 .mnd_width = 0, 565 .hid_width = 5, 566 .parent_map = cam_cc_parent_map_0, 567 .freq_tbl = ftbl_cam_cc_lrme_clk_src, 568 .clkr.hw.init = &(struct clk_init_data){ 569 .name = "cam_cc_lrme_clk_src", 570 .parent_data = cam_cc_parent_data_0, 571 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 572 .flags = CLK_SET_RATE_PARENT, 573 .ops = &clk_rcg2_shared_ops, 574 }, 575}; 576 577static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 578 F(19200000, P_BI_TCXO, 1, 0, 0), 579 F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 2), 580 F(33333333, P_CAM_CC_PLL0_OUT_EVEN, 2, 1, 9), 581 F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0), 582 { } 583}; 584 585static struct clk_rcg2 cam_cc_mclk0_clk_src = { 586 .cmd_rcgr = 0x4004, 587 .mnd_width = 8, 588 .hid_width = 5, 589 .parent_map = cam_cc_parent_map_0, 590 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 591 .clkr.hw.init = &(struct clk_init_data){ 592 .name = "cam_cc_mclk0_clk_src", 593 .parent_data = cam_cc_parent_data_0, 594 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_rcg2_ops, 597 }, 598}; 599 600static struct clk_rcg2 cam_cc_mclk1_clk_src = { 601 .cmd_rcgr = 0x4024, 602 .mnd_width = 8, 603 .hid_width = 5, 604 .parent_map = cam_cc_parent_map_0, 605 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 606 .clkr.hw.init = &(struct clk_init_data){ 607 .name = "cam_cc_mclk1_clk_src", 608 .parent_data = cam_cc_parent_data_0, 609 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 610 .flags = CLK_SET_RATE_PARENT, 611 .ops = &clk_rcg2_ops, 612 }, 613}; 614 615static struct clk_rcg2 cam_cc_mclk2_clk_src = { 616 .cmd_rcgr = 0x4044, 617 .mnd_width = 8, 618 .hid_width = 5, 619 .parent_map = cam_cc_parent_map_0, 620 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 621 .clkr.hw.init = &(struct clk_init_data){ 622 .name = "cam_cc_mclk2_clk_src", 623 .parent_data = cam_cc_parent_data_0, 624 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 625 .flags = CLK_SET_RATE_PARENT, 626 .ops = &clk_rcg2_ops, 627 }, 628}; 629 630static struct clk_rcg2 cam_cc_mclk3_clk_src = { 631 .cmd_rcgr = 0x4064, 632 .mnd_width = 8, 633 .hid_width = 5, 634 .parent_map = cam_cc_parent_map_0, 635 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 636 .clkr.hw.init = &(struct clk_init_data){ 637 .name = "cam_cc_mclk3_clk_src", 638 .parent_data = cam_cc_parent_data_0, 639 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 640 .flags = CLK_SET_RATE_PARENT, 641 .ops = &clk_rcg2_ops, 642 }, 643}; 644 645static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 646 F(19200000, P_BI_TCXO, 1, 0, 0), 647 F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0), 648 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), 649 F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0), 650 F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0), 651 { } 652}; 653 654static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 655 .cmd_rcgr = 0x6054, 656 .mnd_width = 0, 657 .hid_width = 5, 658 .parent_map = cam_cc_parent_map_0, 659 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 660 .clkr.hw.init = &(struct clk_init_data){ 661 .name = "cam_cc_slow_ahb_clk_src", 662 .parent_data = cam_cc_parent_data_0, 663 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 664 .flags = CLK_SET_RATE_PARENT, 665 .ops = &clk_rcg2_ops, 666 }, 667}; 668 669static struct clk_branch cam_cc_bps_ahb_clk = { 670 .halt_reg = 0x606c, 671 .halt_check = BRANCH_HALT, 672 .clkr = { 673 .enable_reg = 0x606c, 674 .enable_mask = BIT(0), 675 .hw.init = &(struct clk_init_data){ 676 .name = "cam_cc_bps_ahb_clk", 677 .parent_hws = (const struct clk_hw*[]){ 678 &cam_cc_slow_ahb_clk_src.clkr.hw, 679 }, 680 .num_parents = 1, 681 .flags = CLK_SET_RATE_PARENT, 682 .ops = &clk_branch2_ops, 683 }, 684 }, 685}; 686 687static struct clk_branch cam_cc_bps_areg_clk = { 688 .halt_reg = 0x6050, 689 .halt_check = BRANCH_HALT, 690 .clkr = { 691 .enable_reg = 0x6050, 692 .enable_mask = BIT(0), 693 .hw.init = &(struct clk_init_data){ 694 .name = "cam_cc_bps_areg_clk", 695 .parent_hws = (const struct clk_hw*[]){ 696 &cam_cc_fast_ahb_clk_src.clkr.hw, 697 }, 698 .num_parents = 1, 699 .flags = CLK_SET_RATE_PARENT, 700 .ops = &clk_branch2_ops, 701 }, 702 }, 703}; 704 705static struct clk_branch cam_cc_bps_axi_clk = { 706 .halt_reg = 0x6034, 707 .halt_check = BRANCH_HALT, 708 .clkr = { 709 .enable_reg = 0x6034, 710 .enable_mask = BIT(0), 711 .hw.init = &(struct clk_init_data){ 712 .name = "cam_cc_bps_axi_clk", 713 .ops = &clk_branch2_ops, 714 }, 715 }, 716}; 717 718static struct clk_branch cam_cc_bps_clk = { 719 .halt_reg = 0x6024, 720 .halt_check = BRANCH_HALT, 721 .clkr = { 722 .enable_reg = 0x6024, 723 .enable_mask = BIT(0), 724 .hw.init = &(struct clk_init_data){ 725 .name = "cam_cc_bps_clk", 726 .parent_hws = (const struct clk_hw*[]){ 727 &cam_cc_bps_clk_src.clkr.hw, 728 }, 729 .num_parents = 1, 730 .flags = CLK_SET_RATE_PARENT, 731 .ops = &clk_branch2_ops, 732 }, 733 }, 734}; 735 736static struct clk_branch cam_cc_camnoc_atb_clk = { 737 .halt_reg = 0xb12c, 738 .halt_check = BRANCH_HALT, 739 .clkr = { 740 .enable_reg = 0xb12c, 741 .enable_mask = BIT(0), 742 .hw.init = &(struct clk_init_data){ 743 .name = "cam_cc_camnoc_atb_clk", 744 .ops = &clk_branch2_ops, 745 }, 746 }, 747}; 748 749static struct clk_branch cam_cc_camnoc_axi_clk = { 750 .halt_reg = 0xb124, 751 .halt_check = BRANCH_HALT, 752 .clkr = { 753 .enable_reg = 0xb124, 754 .enable_mask = BIT(0), 755 .hw.init = &(struct clk_init_data){ 756 .name = "cam_cc_camnoc_axi_clk", 757 .ops = &clk_branch2_ops, 758 }, 759 }, 760}; 761 762static struct clk_branch cam_cc_cci_clk = { 763 .halt_reg = 0xb0f0, 764 .halt_check = BRANCH_HALT, 765 .clkr = { 766 .enable_reg = 0xb0f0, 767 .enable_mask = BIT(0), 768 .hw.init = &(struct clk_init_data){ 769 .name = "cam_cc_cci_clk", 770 .parent_hws = (const struct clk_hw*[]){ 771 &cam_cc_cci_clk_src.clkr.hw, 772 }, 773 .num_parents = 1, 774 .flags = CLK_SET_RATE_PARENT, 775 .ops = &clk_branch2_ops, 776 }, 777 }, 778}; 779 780static struct clk_branch cam_cc_cpas_ahb_clk = { 781 .halt_reg = 0xb11c, 782 .halt_check = BRANCH_HALT, 783 .clkr = { 784 .enable_reg = 0xb11c, 785 .enable_mask = BIT(0), 786 .hw.init = &(struct clk_init_data){ 787 .name = "cam_cc_cpas_ahb_clk", 788 .parent_hws = (const struct clk_hw*[]){ 789 &cam_cc_slow_ahb_clk_src.clkr.hw, 790 }, 791 .num_parents = 1, 792 .flags = CLK_SET_RATE_PARENT, 793 .ops = &clk_branch2_ops, 794 }, 795 }, 796}; 797 798static struct clk_branch cam_cc_csi0phytimer_clk = { 799 .halt_reg = 0x501c, 800 .halt_check = BRANCH_HALT, 801 .clkr = { 802 .enable_reg = 0x501c, 803 .enable_mask = BIT(0), 804 .hw.init = &(struct clk_init_data){ 805 .name = "cam_cc_csi0phytimer_clk", 806 .parent_hws = (const struct clk_hw*[]){ 807 &cam_cc_csi0phytimer_clk_src.clkr.hw, 808 }, 809 .num_parents = 1, 810 .flags = CLK_SET_RATE_PARENT, 811 .ops = &clk_branch2_ops, 812 }, 813 }, 814}; 815 816static struct clk_branch cam_cc_csi1phytimer_clk = { 817 .halt_reg = 0x5040, 818 .halt_check = BRANCH_HALT, 819 .clkr = { 820 .enable_reg = 0x5040, 821 .enable_mask = BIT(0), 822 .hw.init = &(struct clk_init_data){ 823 .name = "cam_cc_csi1phytimer_clk", 824 .parent_hws = (const struct clk_hw*[]){ 825 &cam_cc_csi1phytimer_clk_src.clkr.hw, 826 }, 827 .num_parents = 1, 828 .flags = CLK_SET_RATE_PARENT, 829 .ops = &clk_branch2_ops, 830 }, 831 }, 832}; 833 834static struct clk_branch cam_cc_csi2phytimer_clk = { 835 .halt_reg = 0x5064, 836 .halt_check = BRANCH_HALT, 837 .clkr = { 838 .enable_reg = 0x5064, 839 .enable_mask = BIT(0), 840 .hw.init = &(struct clk_init_data){ 841 .name = "cam_cc_csi2phytimer_clk", 842 .parent_hws = (const struct clk_hw*[]){ 843 &cam_cc_csi2phytimer_clk_src.clkr.hw, 844 }, 845 .num_parents = 1, 846 .flags = CLK_SET_RATE_PARENT, 847 .ops = &clk_branch2_ops, 848 }, 849 }, 850}; 851 852static struct clk_branch cam_cc_csi3phytimer_clk = { 853 .halt_reg = 0x5088, 854 .halt_check = BRANCH_HALT, 855 .clkr = { 856 .enable_reg = 0x5088, 857 .enable_mask = BIT(0), 858 .hw.init = &(struct clk_init_data){ 859 .name = "cam_cc_csi3phytimer_clk", 860 .parent_hws = (const struct clk_hw*[]){ 861 &cam_cc_csi3phytimer_clk_src.clkr.hw, 862 }, 863 .num_parents = 1, 864 .flags = CLK_SET_RATE_PARENT, 865 .ops = &clk_branch2_ops, 866 }, 867 }, 868}; 869 870static struct clk_branch cam_cc_csiphy0_clk = { 871 .halt_reg = 0x5020, 872 .halt_check = BRANCH_HALT, 873 .clkr = { 874 .enable_reg = 0x5020, 875 .enable_mask = BIT(0), 876 .hw.init = &(struct clk_init_data){ 877 .name = "cam_cc_csiphy0_clk", 878 .parent_hws = (const struct clk_hw*[]){ 879 &cam_cc_cphy_rx_clk_src.clkr.hw, 880 }, 881 .num_parents = 1, 882 .flags = CLK_SET_RATE_PARENT, 883 .ops = &clk_branch2_ops, 884 }, 885 }, 886}; 887 888static struct clk_branch cam_cc_csiphy1_clk = { 889 .halt_reg = 0x5044, 890 .halt_check = BRANCH_HALT, 891 .clkr = { 892 .enable_reg = 0x5044, 893 .enable_mask = BIT(0), 894 .hw.init = &(struct clk_init_data){ 895 .name = "cam_cc_csiphy1_clk", 896 .parent_hws = (const struct clk_hw*[]){ 897 &cam_cc_cphy_rx_clk_src.clkr.hw, 898 }, 899 .num_parents = 1, 900 .flags = CLK_SET_RATE_PARENT, 901 .ops = &clk_branch2_ops, 902 }, 903 }, 904}; 905 906static struct clk_branch cam_cc_csiphy2_clk = { 907 .halt_reg = 0x5068, 908 .halt_check = BRANCH_HALT, 909 .clkr = { 910 .enable_reg = 0x5068, 911 .enable_mask = BIT(0), 912 .hw.init = &(struct clk_init_data){ 913 .name = "cam_cc_csiphy2_clk", 914 .parent_hws = (const struct clk_hw*[]){ 915 &cam_cc_cphy_rx_clk_src.clkr.hw, 916 }, 917 .num_parents = 1, 918 .flags = CLK_SET_RATE_PARENT, 919 .ops = &clk_branch2_ops, 920 }, 921 }, 922}; 923 924static struct clk_branch cam_cc_csiphy3_clk = { 925 .halt_reg = 0x508c, 926 .halt_check = BRANCH_HALT, 927 .clkr = { 928 .enable_reg = 0x508c, 929 .enable_mask = BIT(0), 930 .hw.init = &(struct clk_init_data){ 931 .name = "cam_cc_csiphy3_clk", 932 .parent_hws = (const struct clk_hw*[]){ 933 &cam_cc_cphy_rx_clk_src.clkr.hw, 934 }, 935 .num_parents = 1, 936 .flags = CLK_SET_RATE_PARENT, 937 .ops = &clk_branch2_ops, 938 }, 939 }, 940}; 941 942static struct clk_branch cam_cc_fd_core_clk = { 943 .halt_reg = 0xb0c8, 944 .halt_check = BRANCH_HALT, 945 .clkr = { 946 .enable_reg = 0xb0c8, 947 .enable_mask = BIT(0), 948 .hw.init = &(struct clk_init_data){ 949 .name = "cam_cc_fd_core_clk", 950 .parent_hws = (const struct clk_hw*[]){ 951 &cam_cc_fd_core_clk_src.clkr.hw, 952 }, 953 .num_parents = 1, 954 .flags = CLK_SET_RATE_PARENT, 955 .ops = &clk_branch2_ops, 956 }, 957 }, 958}; 959 960static struct clk_branch cam_cc_fd_core_uar_clk = { 961 .halt_reg = 0xb0d0, 962 .halt_check = BRANCH_HALT, 963 .clkr = { 964 .enable_reg = 0xb0d0, 965 .enable_mask = BIT(0), 966 .hw.init = &(struct clk_init_data){ 967 .name = "cam_cc_fd_core_uar_clk", 968 .parent_hws = (const struct clk_hw*[]){ 969 &cam_cc_fd_core_clk_src.clkr.hw, 970 }, 971 .num_parents = 1, 972 .ops = &clk_branch2_ops, 973 }, 974 }, 975}; 976 977static struct clk_branch cam_cc_icp_apb_clk = { 978 .halt_reg = 0xb084, 979 .halt_check = BRANCH_HALT, 980 .clkr = { 981 .enable_reg = 0xb084, 982 .enable_mask = BIT(0), 983 .hw.init = &(struct clk_init_data){ 984 .name = "cam_cc_icp_apb_clk", 985 .ops = &clk_branch2_ops, 986 }, 987 }, 988}; 989 990static struct clk_branch cam_cc_icp_atb_clk = { 991 .halt_reg = 0xb078, 992 .halt_check = BRANCH_HALT, 993 .clkr = { 994 .enable_reg = 0xb078, 995 .enable_mask = BIT(0), 996 .hw.init = &(struct clk_init_data){ 997 .name = "cam_cc_icp_atb_clk", 998 .ops = &clk_branch2_ops, 999 }, 1000 }, 1001}; 1002 1003static struct clk_branch cam_cc_icp_clk = { 1004 .halt_reg = 0xb0a0, 1005 .halt_check = BRANCH_HALT, 1006 .clkr = { 1007 .enable_reg = 0xb0a0, 1008 .enable_mask = BIT(0), 1009 .hw.init = &(struct clk_init_data){ 1010 .name = "cam_cc_icp_clk", 1011 .parent_hws = (const struct clk_hw*[]){ 1012 &cam_cc_icp_clk_src.clkr.hw, 1013 }, 1014 .num_parents = 1, 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_branch2_ops, 1017 }, 1018 }, 1019}; 1020 1021static struct clk_branch cam_cc_icp_cti_clk = { 1022 .halt_reg = 0xb07c, 1023 .halt_check = BRANCH_HALT, 1024 .clkr = { 1025 .enable_reg = 0xb07c, 1026 .enable_mask = BIT(0), 1027 .hw.init = &(struct clk_init_data){ 1028 .name = "cam_cc_icp_cti_clk", 1029 .ops = &clk_branch2_ops, 1030 }, 1031 }, 1032}; 1033 1034static struct clk_branch cam_cc_icp_ts_clk = { 1035 .halt_reg = 0xb080, 1036 .halt_check = BRANCH_HALT, 1037 .clkr = { 1038 .enable_reg = 0xb080, 1039 .enable_mask = BIT(0), 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "cam_cc_icp_ts_clk", 1042 .ops = &clk_branch2_ops, 1043 }, 1044 }, 1045}; 1046 1047static struct clk_branch cam_cc_ife_0_axi_clk = { 1048 .halt_reg = 0x907c, 1049 .halt_check = BRANCH_HALT, 1050 .clkr = { 1051 .enable_reg = 0x907c, 1052 .enable_mask = BIT(0), 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "cam_cc_ife_0_axi_clk", 1055 .ops = &clk_branch2_ops, 1056 }, 1057 }, 1058}; 1059 1060static struct clk_branch cam_cc_ife_0_clk = { 1061 .halt_reg = 0x9024, 1062 .halt_check = BRANCH_HALT, 1063 .clkr = { 1064 .enable_reg = 0x9024, 1065 .enable_mask = BIT(0), 1066 .hw.init = &(struct clk_init_data){ 1067 .name = "cam_cc_ife_0_clk", 1068 .parent_hws = (const struct clk_hw*[]){ 1069 &cam_cc_ife_0_clk_src.clkr.hw, 1070 }, 1071 .num_parents = 1, 1072 .flags = CLK_SET_RATE_PARENT, 1073 .ops = &clk_branch2_ops, 1074 }, 1075 }, 1076}; 1077 1078static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { 1079 .halt_reg = 0x9078, 1080 .halt_check = BRANCH_HALT, 1081 .clkr = { 1082 .enable_reg = 0x9078, 1083 .enable_mask = BIT(0), 1084 .hw.init = &(struct clk_init_data){ 1085 .name = "cam_cc_ife_0_cphy_rx_clk", 1086 .parent_hws = (const struct clk_hw*[]){ 1087 &cam_cc_cphy_rx_clk_src.clkr.hw, 1088 }, 1089 .num_parents = 1, 1090 .flags = CLK_SET_RATE_PARENT, 1091 .ops = &clk_branch2_ops, 1092 }, 1093 }, 1094}; 1095 1096static struct clk_branch cam_cc_ife_0_csid_clk = { 1097 .halt_reg = 0x9050, 1098 .halt_check = BRANCH_HALT, 1099 .clkr = { 1100 .enable_reg = 0x9050, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(struct clk_init_data){ 1103 .name = "cam_cc_ife_0_csid_clk", 1104 .parent_hws = (const struct clk_hw*[]){ 1105 &cam_cc_ife_0_csid_clk_src.clkr.hw, 1106 }, 1107 .num_parents = 1, 1108 .flags = CLK_SET_RATE_PARENT, 1109 .ops = &clk_branch2_ops, 1110 }, 1111 }, 1112}; 1113 1114static struct clk_branch cam_cc_ife_0_dsp_clk = { 1115 .halt_reg = 0x9034, 1116 .halt_check = BRANCH_HALT, 1117 .clkr = { 1118 .enable_reg = 0x9034, 1119 .enable_mask = BIT(0), 1120 .hw.init = &(struct clk_init_data){ 1121 .name = "cam_cc_ife_0_dsp_clk", 1122 .parent_hws = (const struct clk_hw*[]){ 1123 &cam_cc_ife_0_clk_src.clkr.hw, 1124 }, 1125 .num_parents = 1, 1126 .ops = &clk_branch2_ops, 1127 }, 1128 }, 1129}; 1130 1131static struct clk_branch cam_cc_ife_1_axi_clk = { 1132 .halt_reg = 0xa054, 1133 .halt_check = BRANCH_HALT, 1134 .clkr = { 1135 .enable_reg = 0xa054, 1136 .enable_mask = BIT(0), 1137 .hw.init = &(struct clk_init_data){ 1138 .name = "cam_cc_ife_1_axi_clk", 1139 .ops = &clk_branch2_ops, 1140 }, 1141 }, 1142}; 1143 1144static struct clk_branch cam_cc_ife_1_clk = { 1145 .halt_reg = 0xa024, 1146 .halt_check = BRANCH_HALT, 1147 .clkr = { 1148 .enable_reg = 0xa024, 1149 .enable_mask = BIT(0), 1150 .hw.init = &(struct clk_init_data){ 1151 .name = "cam_cc_ife_1_clk", 1152 .parent_hws = (const struct clk_hw*[]){ 1153 &cam_cc_ife_1_clk_src.clkr.hw, 1154 }, 1155 .num_parents = 1, 1156 .flags = CLK_SET_RATE_PARENT, 1157 .ops = &clk_branch2_ops, 1158 }, 1159 }, 1160}; 1161 1162static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { 1163 .halt_reg = 0xa050, 1164 .halt_check = BRANCH_HALT, 1165 .clkr = { 1166 .enable_reg = 0xa050, 1167 .enable_mask = BIT(0), 1168 .hw.init = &(struct clk_init_data){ 1169 .name = "cam_cc_ife_1_cphy_rx_clk", 1170 .parent_hws = (const struct clk_hw*[]){ 1171 &cam_cc_cphy_rx_clk_src.clkr.hw, 1172 }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178}; 1179 1180static struct clk_branch cam_cc_ife_1_csid_clk = { 1181 .halt_reg = 0xa048, 1182 .halt_check = BRANCH_HALT, 1183 .clkr = { 1184 .enable_reg = 0xa048, 1185 .enable_mask = BIT(0), 1186 .hw.init = &(struct clk_init_data){ 1187 .name = "cam_cc_ife_1_csid_clk", 1188 .parent_hws = (const struct clk_hw*[]){ 1189 &cam_cc_ife_1_csid_clk_src.clkr.hw, 1190 }, 1191 .num_parents = 1, 1192 .flags = CLK_SET_RATE_PARENT, 1193 .ops = &clk_branch2_ops, 1194 }, 1195 }, 1196}; 1197 1198static struct clk_branch cam_cc_ife_1_dsp_clk = { 1199 .halt_reg = 0xa02c, 1200 .halt_check = BRANCH_HALT, 1201 .clkr = { 1202 .enable_reg = 0xa02c, 1203 .enable_mask = BIT(0), 1204 .hw.init = &(struct clk_init_data){ 1205 .name = "cam_cc_ife_1_dsp_clk", 1206 .parent_hws = (const struct clk_hw*[]){ 1207 &cam_cc_ife_1_clk_src.clkr.hw, 1208 }, 1209 .num_parents = 1, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213}; 1214 1215static struct clk_branch cam_cc_ife_lite_clk = { 1216 .halt_reg = 0xb01c, 1217 .halt_check = BRANCH_HALT, 1218 .clkr = { 1219 .enable_reg = 0xb01c, 1220 .enable_mask = BIT(0), 1221 .hw.init = &(struct clk_init_data){ 1222 .name = "cam_cc_ife_lite_clk", 1223 .parent_hws = (const struct clk_hw*[]){ 1224 &cam_cc_ife_lite_clk_src.clkr.hw, 1225 }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_branch2_ops, 1229 }, 1230 }, 1231}; 1232 1233static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { 1234 .halt_reg = 0xb044, 1235 .halt_check = BRANCH_HALT, 1236 .clkr = { 1237 .enable_reg = 0xb044, 1238 .enable_mask = BIT(0), 1239 .hw.init = &(struct clk_init_data){ 1240 .name = "cam_cc_ife_lite_cphy_rx_clk", 1241 .parent_hws = (const struct clk_hw*[]){ 1242 &cam_cc_cphy_rx_clk_src.clkr.hw, 1243 }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT, 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249}; 1250 1251static struct clk_branch cam_cc_ife_lite_csid_clk = { 1252 .halt_reg = 0xb03c, 1253 .halt_check = BRANCH_HALT, 1254 .clkr = { 1255 .enable_reg = 0xb03c, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "cam_cc_ife_lite_csid_clk", 1259 .parent_hws = (const struct clk_hw*[]){ 1260 &cam_cc_ife_lite_csid_clk_src.clkr.hw, 1261 }, 1262 .num_parents = 1, 1263 .flags = CLK_SET_RATE_PARENT, 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267}; 1268 1269static struct clk_branch cam_cc_ipe_0_ahb_clk = { 1270 .halt_reg = 0x703c, 1271 .halt_check = BRANCH_HALT, 1272 .clkr = { 1273 .enable_reg = 0x703c, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "cam_cc_ipe_0_ahb_clk", 1277 .parent_hws = (const struct clk_hw*[]){ 1278 &cam_cc_slow_ahb_clk_src.clkr.hw, 1279 }, 1280 .num_parents = 1, 1281 .flags = CLK_SET_RATE_PARENT, 1282 .ops = &clk_branch2_ops, 1283 }, 1284 }, 1285}; 1286 1287static struct clk_branch cam_cc_ipe_0_areg_clk = { 1288 .halt_reg = 0x7038, 1289 .halt_check = BRANCH_HALT, 1290 .clkr = { 1291 .enable_reg = 0x7038, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "cam_cc_ipe_0_areg_clk", 1295 .parent_hws = (const struct clk_hw*[]){ 1296 &cam_cc_fast_ahb_clk_src.clkr.hw, 1297 }, 1298 .num_parents = 1, 1299 .flags = CLK_SET_RATE_PARENT, 1300 .ops = &clk_branch2_ops, 1301 }, 1302 }, 1303}; 1304 1305static struct clk_branch cam_cc_ipe_0_axi_clk = { 1306 .halt_reg = 0x7034, 1307 .halt_check = BRANCH_HALT, 1308 .clkr = { 1309 .enable_reg = 0x7034, 1310 .enable_mask = BIT(0), 1311 .hw.init = &(struct clk_init_data){ 1312 .name = "cam_cc_ipe_0_axi_clk", 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316}; 1317 1318static struct clk_branch cam_cc_ipe_0_clk = { 1319 .halt_reg = 0x7024, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x7024, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "cam_cc_ipe_0_clk", 1326 .parent_hws = (const struct clk_hw*[]){ 1327 &cam_cc_ipe_0_clk_src.clkr.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334}; 1335 1336static struct clk_branch cam_cc_ipe_1_ahb_clk = { 1337 .halt_reg = 0x803c, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x803c, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(struct clk_init_data){ 1343 .name = "cam_cc_ipe_1_ahb_clk", 1344 .parent_hws = (const struct clk_hw*[]){ 1345 &cam_cc_slow_ahb_clk_src.clkr.hw, 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352}; 1353 1354static struct clk_branch cam_cc_ipe_1_areg_clk = { 1355 .halt_reg = 0x8038, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x8038, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(struct clk_init_data){ 1361 .name = "cam_cc_ipe_1_areg_clk", 1362 .parent_hws = (const struct clk_hw*[]){ 1363 &cam_cc_fast_ahb_clk_src.clkr.hw, 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370}; 1371 1372static struct clk_branch cam_cc_ipe_1_axi_clk = { 1373 .halt_reg = 0x8034, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x8034, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "cam_cc_ipe_1_axi_clk", 1380 .ops = &clk_branch2_ops, 1381 }, 1382 }, 1383}; 1384 1385static struct clk_branch cam_cc_ipe_1_clk = { 1386 .halt_reg = 0x8024, 1387 .halt_check = BRANCH_HALT, 1388 .clkr = { 1389 .enable_reg = 0x8024, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "cam_cc_ipe_1_clk", 1393 .parent_hws = (const struct clk_hw*[]){ 1394 &cam_cc_ipe_1_clk_src.clkr.hw, 1395 }, 1396 .num_parents = 1, 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401}; 1402 1403static struct clk_branch cam_cc_jpeg_clk = { 1404 .halt_reg = 0xb064, 1405 .halt_check = BRANCH_HALT, 1406 .clkr = { 1407 .enable_reg = 0xb064, 1408 .enable_mask = BIT(0), 1409 .hw.init = &(struct clk_init_data){ 1410 .name = "cam_cc_jpeg_clk", 1411 .parent_hws = (const struct clk_hw*[]){ 1412 &cam_cc_jpeg_clk_src.clkr.hw, 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419}; 1420 1421static struct clk_branch cam_cc_lrme_clk = { 1422 .halt_reg = 0xb110, 1423 .halt_check = BRANCH_HALT, 1424 .clkr = { 1425 .enable_reg = 0xb110, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "cam_cc_lrme_clk", 1429 .parent_hws = (const struct clk_hw*[]){ 1430 &cam_cc_lrme_clk_src.clkr.hw, 1431 }, 1432 .num_parents = 1, 1433 .flags = CLK_SET_RATE_PARENT, 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437}; 1438 1439static struct clk_branch cam_cc_mclk0_clk = { 1440 .halt_reg = 0x401c, 1441 .halt_check = BRANCH_HALT, 1442 .clkr = { 1443 .enable_reg = 0x401c, 1444 .enable_mask = BIT(0), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "cam_cc_mclk0_clk", 1447 .parent_hws = (const struct clk_hw*[]){ 1448 &cam_cc_mclk0_clk_src.clkr.hw, 1449 }, 1450 .num_parents = 1, 1451 .flags = CLK_SET_RATE_PARENT, 1452 .ops = &clk_branch2_ops, 1453 }, 1454 }, 1455}; 1456 1457static struct clk_branch cam_cc_mclk1_clk = { 1458 .halt_reg = 0x403c, 1459 .halt_check = BRANCH_HALT, 1460 .clkr = { 1461 .enable_reg = 0x403c, 1462 .enable_mask = BIT(0), 1463 .hw.init = &(struct clk_init_data){ 1464 .name = "cam_cc_mclk1_clk", 1465 .parent_hws = (const struct clk_hw*[]){ 1466 &cam_cc_mclk1_clk_src.clkr.hw, 1467 }, 1468 .num_parents = 1, 1469 .flags = CLK_SET_RATE_PARENT, 1470 .ops = &clk_branch2_ops, 1471 }, 1472 }, 1473}; 1474 1475static struct clk_branch cam_cc_mclk2_clk = { 1476 .halt_reg = 0x405c, 1477 .halt_check = BRANCH_HALT, 1478 .clkr = { 1479 .enable_reg = 0x405c, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "cam_cc_mclk2_clk", 1483 .parent_hws = (const struct clk_hw*[]){ 1484 &cam_cc_mclk2_clk_src.clkr.hw, 1485 }, 1486 .num_parents = 1, 1487 .flags = CLK_SET_RATE_PARENT, 1488 .ops = &clk_branch2_ops, 1489 }, 1490 }, 1491}; 1492 1493static struct clk_branch cam_cc_mclk3_clk = { 1494 .halt_reg = 0x407c, 1495 .halt_check = BRANCH_HALT, 1496 .clkr = { 1497 .enable_reg = 0x407c, 1498 .enable_mask = BIT(0), 1499 .hw.init = &(struct clk_init_data){ 1500 .name = "cam_cc_mclk3_clk", 1501 .parent_hws = (const struct clk_hw*[]){ 1502 &cam_cc_mclk3_clk_src.clkr.hw, 1503 }, 1504 .num_parents = 1, 1505 .flags = CLK_SET_RATE_PARENT, 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509}; 1510 1511static struct clk_branch cam_cc_soc_ahb_clk = { 1512 .halt_reg = 0xb13c, 1513 .halt_check = BRANCH_HALT, 1514 .clkr = { 1515 .enable_reg = 0xb13c, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(struct clk_init_data){ 1518 .name = "cam_cc_soc_ahb_clk", 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522}; 1523 1524static struct clk_branch cam_cc_sys_tmr_clk = { 1525 .halt_reg = 0xb0a8, 1526 .halt_check = BRANCH_HALT, 1527 .clkr = { 1528 .enable_reg = 0xb0a8, 1529 .enable_mask = BIT(0), 1530 .hw.init = &(struct clk_init_data){ 1531 .name = "cam_cc_sys_tmr_clk", 1532 .ops = &clk_branch2_ops, 1533 }, 1534 }, 1535}; 1536 1537static struct gdsc titan_top_gdsc; 1538 1539static struct gdsc bps_gdsc = { 1540 .gdscr = 0x6004, 1541 .pd = { 1542 .name = "bps_gdsc", 1543 }, 1544 .flags = HW_CTRL | POLL_CFG_GDSCR, 1545 .pwrsts = PWRSTS_OFF_ON, 1546}; 1547 1548static struct gdsc ipe_0_gdsc = { 1549 .gdscr = 0x7004, 1550 .pd = { 1551 .name = "ipe_0_gdsc", 1552 }, 1553 .flags = HW_CTRL | POLL_CFG_GDSCR, 1554 .pwrsts = PWRSTS_OFF_ON, 1555}; 1556 1557static struct gdsc ipe_1_gdsc = { 1558 .gdscr = 0x8004, 1559 .pd = { 1560 .name = "ipe_1_gdsc", 1561 }, 1562 .flags = HW_CTRL | POLL_CFG_GDSCR, 1563 .pwrsts = PWRSTS_OFF_ON, 1564}; 1565 1566static struct gdsc ife_0_gdsc = { 1567 .gdscr = 0x9004, 1568 .pd = { 1569 .name = "ife_0_gdsc", 1570 }, 1571 .flags = POLL_CFG_GDSCR, 1572 .parent = &titan_top_gdsc.pd, 1573 .pwrsts = PWRSTS_OFF_ON, 1574}; 1575 1576static struct gdsc ife_1_gdsc = { 1577 .gdscr = 0xa004, 1578 .pd = { 1579 .name = "ife_1_gdsc", 1580 }, 1581 .flags = POLL_CFG_GDSCR, 1582 .parent = &titan_top_gdsc.pd, 1583 .pwrsts = PWRSTS_OFF_ON, 1584}; 1585 1586static struct gdsc titan_top_gdsc = { 1587 .gdscr = 0xb134, 1588 .pd = { 1589 .name = "titan_top_gdsc", 1590 }, 1591 .flags = POLL_CFG_GDSCR, 1592 .pwrsts = PWRSTS_OFF_ON, 1593}; 1594 1595static struct clk_regmap *cam_cc_sdm845_clocks[] = { 1596 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1597 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1598 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, 1599 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1600 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1601 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1602 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, 1603 [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr, 1604 [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr, 1605 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1606 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1607 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1608 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1609 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 1610 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 1611 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 1612 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 1613 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 1614 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 1615 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 1616 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 1617 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 1618 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 1619 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 1620 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr, 1621 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr, 1622 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr, 1623 [CAM_CC_ICP_APB_CLK] = &cam_cc_icp_apb_clk.clkr, 1624 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 1625 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 1626 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 1627 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 1628 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 1629 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, 1630 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, 1631 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, 1632 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, 1633 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, 1634 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, 1635 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, 1636 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, 1637 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, 1638 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, 1639 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, 1640 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, 1641 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, 1642 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, 1643 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, 1644 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, 1645 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, 1646 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, 1647 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, 1648 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, 1649 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, 1650 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, 1651 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, 1652 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, 1653 [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, 1654 [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr, 1655 [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr, 1656 [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, 1657 [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr, 1658 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, 1659 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, 1660 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, 1661 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, 1662 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 1663 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 1664 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 1665 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 1666 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 1667 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 1668 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 1669 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 1670 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 1671 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 1672 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 1673 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 1674 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 1675 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, 1676 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 1677 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 1678 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 1679 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 1680 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 1681}; 1682 1683static struct gdsc *cam_cc_sdm845_gdscs[] = { 1684 [BPS_GDSC] = &bps_gdsc, 1685 [IPE_0_GDSC] = &ipe_0_gdsc, 1686 [IPE_1_GDSC] = &ipe_1_gdsc, 1687 [IFE_0_GDSC] = &ife_0_gdsc, 1688 [IFE_1_GDSC] = &ife_1_gdsc, 1689 [TITAN_TOP_GDSC] = &titan_top_gdsc, 1690}; 1691 1692static const struct regmap_config cam_cc_sdm845_regmap_config = { 1693 .reg_bits = 32, 1694 .reg_stride = 4, 1695 .val_bits = 32, 1696 .max_register = 0xd004, 1697 .fast_io = true, 1698}; 1699 1700static const struct qcom_cc_desc cam_cc_sdm845_desc = { 1701 .config = &cam_cc_sdm845_regmap_config, 1702 .clks = cam_cc_sdm845_clocks, 1703 .num_clks = ARRAY_SIZE(cam_cc_sdm845_clocks), 1704 .gdscs = cam_cc_sdm845_gdscs, 1705 .num_gdscs = ARRAY_SIZE(cam_cc_sdm845_gdscs), 1706}; 1707 1708static const struct of_device_id cam_cc_sdm845_match_table[] = { 1709 { .compatible = "qcom,sdm845-camcc" }, 1710 { } 1711}; 1712MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table); 1713 1714static int cam_cc_sdm845_probe(struct platform_device *pdev) 1715{ 1716 struct regmap *regmap; 1717 struct alpha_pll_config cam_cc_pll_config = { }; 1718 1719 regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc); 1720 if (IS_ERR(regmap)) 1721 return PTR_ERR(regmap); 1722 1723 cam_cc_pll_config.l = 0x1f; 1724 cam_cc_pll_config.alpha = 0x4000; 1725 clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config); 1726 1727 cam_cc_pll_config.l = 0x2a; 1728 cam_cc_pll_config.alpha = 0x1556; 1729 clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config); 1730 1731 cam_cc_pll_config.l = 0x32; 1732 cam_cc_pll_config.alpha = 0x0; 1733 clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config); 1734 1735 cam_cc_pll_config.l = 0x14; 1736 clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config); 1737 1738 return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap); 1739} 1740 1741static struct platform_driver cam_cc_sdm845_driver = { 1742 .probe = cam_cc_sdm845_probe, 1743 .driver = { 1744 .name = "sdm845-camcc", 1745 .of_match_table = cam_cc_sdm845_match_table, 1746 }, 1747}; 1748 1749static int __init cam_cc_sdm845_init(void) 1750{ 1751 return platform_driver_register(&cam_cc_sdm845_driver); 1752} 1753subsys_initcall(cam_cc_sdm845_init); 1754 1755static void __exit cam_cc_sdm845_exit(void) 1756{ 1757 platform_driver_unregister(&cam_cc_sdm845_driver); 1758} 1759module_exit(cam_cc_sdm845_exit); 1760 1761MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver"); 1762MODULE_LICENSE("GPL v2"); 1763