162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Qualcomm A7 PLL driver 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2020, Linaro Limited 662306a36Sopenharmony_ci * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 762306a36Sopenharmony_ci */ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <linux/clk-provider.h> 1062306a36Sopenharmony_ci#include <linux/module.h> 1162306a36Sopenharmony_ci#include <linux/platform_device.h> 1262306a36Sopenharmony_ci#include <linux/regmap.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci#include "clk-alpha-pll.h" 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci#define LUCID_PLL_OFF_L_VAL 0x04 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_cistatic const struct pll_vco lucid_vco[] = { 1962306a36Sopenharmony_ci { 249600000, 2000000000, 0 }, 2062306a36Sopenharmony_ci}; 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_cistatic struct clk_alpha_pll a7pll = { 2362306a36Sopenharmony_ci .offset = 0x100, 2462306a36Sopenharmony_ci .vco_table = lucid_vco, 2562306a36Sopenharmony_ci .num_vco = ARRAY_SIZE(lucid_vco), 2662306a36Sopenharmony_ci .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 2762306a36Sopenharmony_ci .clkr = { 2862306a36Sopenharmony_ci .hw.init = &(struct clk_init_data){ 2962306a36Sopenharmony_ci .name = "a7pll", 3062306a36Sopenharmony_ci .parent_data = &(const struct clk_parent_data){ 3162306a36Sopenharmony_ci .fw_name = "bi_tcxo", 3262306a36Sopenharmony_ci }, 3362306a36Sopenharmony_ci .num_parents = 1, 3462306a36Sopenharmony_ci .ops = &clk_alpha_pll_lucid_ops, 3562306a36Sopenharmony_ci }, 3662306a36Sopenharmony_ci }, 3762306a36Sopenharmony_ci}; 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_cistatic const struct alpha_pll_config a7pll_config = { 4062306a36Sopenharmony_ci .l = 0x39, 4162306a36Sopenharmony_ci .config_ctl_val = 0x20485699, 4262306a36Sopenharmony_ci .config_ctl_hi_val = 0x2261, 4362306a36Sopenharmony_ci .config_ctl_hi1_val = 0x029A699C, 4462306a36Sopenharmony_ci .user_ctl_val = 0x1, 4562306a36Sopenharmony_ci .user_ctl_hi_val = 0x805, 4662306a36Sopenharmony_ci}; 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_cistatic const struct regmap_config a7pll_regmap_config = { 4962306a36Sopenharmony_ci .reg_bits = 32, 5062306a36Sopenharmony_ci .reg_stride = 4, 5162306a36Sopenharmony_ci .val_bits = 32, 5262306a36Sopenharmony_ci .max_register = 0x1000, 5362306a36Sopenharmony_ci .fast_io = true, 5462306a36Sopenharmony_ci}; 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_cistatic int qcom_a7pll_probe(struct platform_device *pdev) 5762306a36Sopenharmony_ci{ 5862306a36Sopenharmony_ci struct device *dev = &pdev->dev; 5962306a36Sopenharmony_ci struct regmap *regmap; 6062306a36Sopenharmony_ci void __iomem *base; 6162306a36Sopenharmony_ci u32 l_val; 6262306a36Sopenharmony_ci int ret; 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci base = devm_platform_ioremap_resource(pdev, 0); 6562306a36Sopenharmony_ci if (IS_ERR(base)) 6662306a36Sopenharmony_ci return PTR_ERR(base); 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ci regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config); 6962306a36Sopenharmony_ci if (IS_ERR(regmap)) 7062306a36Sopenharmony_ci return PTR_ERR(regmap); 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ci /* Configure PLL only if the l_val is zero */ 7362306a36Sopenharmony_ci regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val); 7462306a36Sopenharmony_ci if (!l_val) 7562306a36Sopenharmony_ci clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config); 7662306a36Sopenharmony_ci 7762306a36Sopenharmony_ci ret = devm_clk_register_regmap(dev, &a7pll.clkr); 7862306a36Sopenharmony_ci if (ret) 7962306a36Sopenharmony_ci return ret; 8062306a36Sopenharmony_ci 8162306a36Sopenharmony_ci return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 8262306a36Sopenharmony_ci &a7pll.clkr.hw); 8362306a36Sopenharmony_ci} 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_cistatic const struct of_device_id qcom_a7pll_match_table[] = { 8662306a36Sopenharmony_ci { .compatible = "qcom,sdx55-a7pll" }, 8762306a36Sopenharmony_ci { } 8862306a36Sopenharmony_ci}; 8962306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, qcom_a7pll_match_table); 9062306a36Sopenharmony_ci 9162306a36Sopenharmony_cistatic struct platform_driver qcom_a7pll_driver = { 9262306a36Sopenharmony_ci .probe = qcom_a7pll_probe, 9362306a36Sopenharmony_ci .driver = { 9462306a36Sopenharmony_ci .name = "qcom-a7pll", 9562306a36Sopenharmony_ci .of_match_table = qcom_a7pll_match_table, 9662306a36Sopenharmony_ci }, 9762306a36Sopenharmony_ci}; 9862306a36Sopenharmony_cimodule_platform_driver(qcom_a7pll_driver); 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ciMODULE_DESCRIPTION("Qualcomm A7 PLL Driver"); 10162306a36Sopenharmony_ciMODULE_LICENSE("GPL v2"); 102