162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Purna Chandra Mandal,<purna.mandal@microchip.com> 462306a36Sopenharmony_ci * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci#ifndef __MICROCHIP_CLK_PIC32_H_ 762306a36Sopenharmony_ci#define __MICROCHIP_CLK_PIC32_H_ 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <linux/clk-provider.h> 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* PIC32 clock data */ 1262306a36Sopenharmony_cistruct pic32_clk_common { 1362306a36Sopenharmony_ci struct device *dev; 1462306a36Sopenharmony_ci void __iomem *iobase; 1562306a36Sopenharmony_ci spinlock_t reg_lock; /* clock lock */ 1662306a36Sopenharmony_ci}; 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* System PLL clock */ 1962306a36Sopenharmony_cistruct pic32_sys_pll_data { 2062306a36Sopenharmony_ci struct clk_init_data init_data; 2162306a36Sopenharmony_ci const u32 ctrl_reg; 2262306a36Sopenharmony_ci const u32 status_reg; 2362306a36Sopenharmony_ci const u32 lock_mask; 2462306a36Sopenharmony_ci}; 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci/* System clock */ 2762306a36Sopenharmony_cistruct pic32_sys_clk_data { 2862306a36Sopenharmony_ci struct clk_init_data init_data; 2962306a36Sopenharmony_ci const u32 mux_reg; 3062306a36Sopenharmony_ci const u32 slew_reg; 3162306a36Sopenharmony_ci const u32 *parent_map; 3262306a36Sopenharmony_ci const u32 slew_div; 3362306a36Sopenharmony_ci}; 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci/* Reference Oscillator clock */ 3662306a36Sopenharmony_cistruct pic32_ref_osc_data { 3762306a36Sopenharmony_ci struct clk_init_data init_data; 3862306a36Sopenharmony_ci const u32 ctrl_reg; 3962306a36Sopenharmony_ci const u32 *parent_map; 4062306a36Sopenharmony_ci}; 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci/* Peripheral Bus clock */ 4362306a36Sopenharmony_cistruct pic32_periph_clk_data { 4462306a36Sopenharmony_ci struct clk_init_data init_data; 4562306a36Sopenharmony_ci const u32 ctrl_reg; 4662306a36Sopenharmony_ci}; 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci/* External Secondary Oscillator clock */ 4962306a36Sopenharmony_cistruct pic32_sec_osc_data { 5062306a36Sopenharmony_ci struct clk_init_data init_data; 5162306a36Sopenharmony_ci const u32 enable_reg; 5262306a36Sopenharmony_ci const u32 status_reg; 5362306a36Sopenharmony_ci const u32 enable_mask; 5462306a36Sopenharmony_ci const u32 status_mask; 5562306a36Sopenharmony_ci const unsigned long fixed_rate; 5662306a36Sopenharmony_ci}; 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ciextern const struct clk_ops pic32_pbclk_ops; 5962306a36Sopenharmony_ciextern const struct clk_ops pic32_sclk_ops; 6062306a36Sopenharmony_ciextern const struct clk_ops pic32_sclk_no_div_ops; 6162306a36Sopenharmony_ciextern const struct clk_ops pic32_spll_ops; 6262306a36Sopenharmony_ciextern const struct clk_ops pic32_roclk_ops; 6362306a36Sopenharmony_ciextern const struct clk_ops pic32_sosc_ops; 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_cistruct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data, 6662306a36Sopenharmony_ci struct pic32_clk_common *core); 6762306a36Sopenharmony_cistruct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data, 6862306a36Sopenharmony_ci struct pic32_clk_common *core); 6962306a36Sopenharmony_cistruct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data, 7062306a36Sopenharmony_ci struct pic32_clk_common *core); 7162306a36Sopenharmony_cistruct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data, 7262306a36Sopenharmony_ci struct pic32_clk_common *core); 7362306a36Sopenharmony_cistruct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data, 7462306a36Sopenharmony_ci struct pic32_clk_common *core); 7562306a36Sopenharmony_ci 7662306a36Sopenharmony_ci#endif /* __MICROCHIP_CLK_PIC32_H_*/ 77