1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Amlogic A1 Peripherals Clock Controller internals 4 * 5 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 6 * Author: Jian Hu <jian.hu@amlogic.com> 7 * 8 * Copyright (c) 2023, SberDevices. All Rights Reserved. 9 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 10 */ 11 12#ifndef __A1_PERIPHERALS_H 13#define __A1_PERIPHERALS_H 14 15/* peripherals clock controller register offset */ 16#define SYS_OSCIN_CTRL 0x0 17#define RTC_BY_OSCIN_CTRL0 0x4 18#define RTC_BY_OSCIN_CTRL1 0x8 19#define RTC_CTRL 0xc 20#define SYS_CLK_CTRL0 0x10 21#define SYS_CLK_EN0 0x1c 22#define SYS_CLK_EN1 0x20 23#define AXI_CLK_EN 0x24 24#define DSPA_CLK_EN 0x28 25#define DSPB_CLK_EN 0x2c 26#define DSPA_CLK_CTRL0 0x30 27#define DSPB_CLK_CTRL0 0x34 28#define CLK12_24_CTRL 0x38 29#define GEN_CLK_CTRL 0x3c 30#define SAR_ADC_CLK_CTRL 0xc0 31#define PWM_CLK_AB_CTRL 0xc4 32#define PWM_CLK_CD_CTRL 0xc8 33#define PWM_CLK_EF_CTRL 0xcc 34#define SPICC_CLK_CTRL 0xd0 35#define TS_CLK_CTRL 0xd4 36#define SPIFC_CLK_CTRL 0xd8 37#define USB_BUSCLK_CTRL 0xdc 38#define SD_EMMC_CLK_CTRL 0xe0 39#define CECA_CLK_CTRL0 0xe4 40#define CECA_CLK_CTRL1 0xe8 41#define CECB_CLK_CTRL0 0xec 42#define CECB_CLK_CTRL1 0xf0 43#define PSRAM_CLK_CTRL 0xf4 44#define DMC_CLK_CTRL 0xf8 45 46#endif /* __A1_PERIPHERALS_H */ 47