1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
5 */
6
7#ifndef __CLK_PLLFH_H
8#define __CLK_PLLFH_H
9
10#include "clk-pll.h"
11
12struct fh_pll_state {
13	void __iomem *base;
14	u32 fh_enable;
15	u32 ssc_rate;
16};
17
18struct fh_pll_data {
19	int pll_id;
20	int fh_id;
21	int fh_ver;
22	u32 fhx_offset;
23	u32 dds_mask;
24	u32 slope0_value;
25	u32 slope1_value;
26	u32 sfstrx_en;
27	u32 frddsx_en;
28	u32 fhctlx_en;
29	u32 tgl_org;
30	u32 dvfs_tri;
31	u32 pcwchg;
32	u32 dt_val;
33	u32 df_val;
34	u32 updnlmt_shft;
35	u32 msk_frddsx_dys;
36	u32 msk_frddsx_dts;
37};
38
39struct mtk_pllfh_data {
40	struct fh_pll_state state;
41	const struct fh_pll_data data;
42};
43
44struct fh_pll_regs {
45	void __iomem *reg_hp_en;
46	void __iomem *reg_clk_con;
47	void __iomem *reg_rst_con;
48	void __iomem *reg_slope0;
49	void __iomem *reg_slope1;
50	void __iomem *reg_cfg;
51	void __iomem *reg_updnlmt;
52	void __iomem *reg_dds;
53	void __iomem *reg_dvfs;
54	void __iomem *reg_mon;
55};
56
57struct mtk_fh {
58	struct mtk_clk_pll clk_pll;
59	struct fh_pll_regs regs;
60	struct mtk_pllfh_data *pllfh_data;
61	const struct fh_operation *ops;
62	spinlock_t *lock;
63};
64
65struct fh_operation {
66	int (*hopping)(struct mtk_fh *fh, unsigned int new_dds,
67		       unsigned int postdiv);
68	int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
69};
70
71int mtk_clk_register_pllfhs(struct device_node *node,
72			    const struct mtk_pll_data *plls, int num_plls,
73			    struct mtk_pllfh_data *pllfhs, int num_pllfhs,
74			    struct clk_hw_onecell_data *clk_data);
75
76void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
77			       struct mtk_pllfh_data *pllfhs, int num_fhs,
78			       struct clk_hw_onecell_data *clk_data);
79
80void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
81		    int num_pllfhs);
82
83#endif /* __CLK_PLLFH_H */
84