162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright (C) 2022 MediaTek Inc.
462306a36Sopenharmony_ci */
562306a36Sopenharmony_ci
662306a36Sopenharmony_ci#include <dt-bindings/clock/mediatek,mt8365-clk.h>
762306a36Sopenharmony_ci#include <linux/clk-provider.h>
862306a36Sopenharmony_ci#include <linux/platform_device.h>
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#include "clk-gate.h"
1162306a36Sopenharmony_ci#include "clk-mtk.h"
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_cistatic const struct mtk_gate_regs vdec0_cg_regs = {
1462306a36Sopenharmony_ci	.set_ofs = 0x0,
1562306a36Sopenharmony_ci	.clr_ofs = 0x4,
1662306a36Sopenharmony_ci	.sta_ofs = 0x0,
1762306a36Sopenharmony_ci};
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_cistatic const struct mtk_gate_regs vdec1_cg_regs = {
2062306a36Sopenharmony_ci	.set_ofs = 0x8,
2162306a36Sopenharmony_ci	.clr_ofs = 0xc,
2262306a36Sopenharmony_ci	.sta_ofs = 0x8,
2362306a36Sopenharmony_ci};
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci#define GATE_VDEC0(_id, _name, _parent, _shift) \
2662306a36Sopenharmony_ci		GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
2762306a36Sopenharmony_ci			 &mtk_clk_gate_ops_setclr_inv)
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci#define GATE_VDEC1(_id, _name, _parent, _shift) \
3062306a36Sopenharmony_ci		GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
3162306a36Sopenharmony_ci			 &mtk_clk_gate_ops_setclr_inv)
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_cistatic const struct mtk_gate vdec_clks[] = {
3462306a36Sopenharmony_ci	/* VDEC0 */
3562306a36Sopenharmony_ci	GATE_VDEC0(CLK_VDEC_VDEC, "vdec_fvdec_ck", "mm_sel", 0),
3662306a36Sopenharmony_ci	/* VDEC1 */
3762306a36Sopenharmony_ci	GATE_VDEC1(CLK_VDEC_LARB1, "vdec_flarb1_ck", "mm_sel", 0),
3862306a36Sopenharmony_ci};
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_cistatic const struct mtk_clk_desc vdec_desc = {
4162306a36Sopenharmony_ci	.clks = vdec_clks,
4262306a36Sopenharmony_ci	.num_clks = ARRAY_SIZE(vdec_clks),
4362306a36Sopenharmony_ci};
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_cistatic const struct of_device_id of_match_clk_mt8365_vdec[] = {
4662306a36Sopenharmony_ci	{
4762306a36Sopenharmony_ci		.compatible = "mediatek,mt8365-vdecsys",
4862306a36Sopenharmony_ci		.data = &vdec_desc,
4962306a36Sopenharmony_ci	}, {
5062306a36Sopenharmony_ci		/* sentinel */
5162306a36Sopenharmony_ci	}
5262306a36Sopenharmony_ci};
5362306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, of_match_clk_mt8365_vdec);
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_cistatic struct platform_driver clk_mt8365_vdec_drv = {
5662306a36Sopenharmony_ci	.probe = mtk_clk_simple_probe,
5762306a36Sopenharmony_ci	.remove_new = mtk_clk_simple_remove,
5862306a36Sopenharmony_ci	.driver = {
5962306a36Sopenharmony_ci		.name = "clk-mt8365-vdec",
6062306a36Sopenharmony_ci		.of_match_table = of_match_clk_mt8365_vdec,
6162306a36Sopenharmony_ci	},
6262306a36Sopenharmony_ci};
6362306a36Sopenharmony_cimodule_platform_driver(clk_mt8365_vdec_drv);
6462306a36Sopenharmony_ciMODULE_LICENSE("GPL");
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