162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
262306a36Sopenharmony_ci//
362306a36Sopenharmony_ci// Copyright (c) 2021 MediaTek Inc.
462306a36Sopenharmony_ci// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
562306a36Sopenharmony_ci
662306a36Sopenharmony_ci#include <linux/clk-provider.h>
762306a36Sopenharmony_ci#include <linux/mod_devicetable.h>
862306a36Sopenharmony_ci#include <linux/platform_device.h>
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#include "clk-mtk.h"
1162306a36Sopenharmony_ci#include "clk-gate.h"
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#include <dt-bindings/clock/mt8192-clk.h>
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_cistatic const struct mtk_gate_regs vdec0_cg_regs = {
1662306a36Sopenharmony_ci	.set_ofs = 0x0,
1762306a36Sopenharmony_ci	.clr_ofs = 0x4,
1862306a36Sopenharmony_ci	.sta_ofs = 0x0,
1962306a36Sopenharmony_ci};
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_cistatic const struct mtk_gate_regs vdec1_cg_regs = {
2262306a36Sopenharmony_ci	.set_ofs = 0x200,
2362306a36Sopenharmony_ci	.clr_ofs = 0x204,
2462306a36Sopenharmony_ci	.sta_ofs = 0x200,
2562306a36Sopenharmony_ci};
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_cistatic const struct mtk_gate_regs vdec2_cg_regs = {
2862306a36Sopenharmony_ci	.set_ofs = 0x8,
2962306a36Sopenharmony_ci	.clr_ofs = 0xc,
3062306a36Sopenharmony_ci	.sta_ofs = 0x8,
3162306a36Sopenharmony_ci};
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci#define GATE_VDEC0(_id, _name, _parent, _shift)	\
3462306a36Sopenharmony_ci	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci#define GATE_VDEC1(_id, _name, _parent, _shift)	\
3762306a36Sopenharmony_ci	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci#define GATE_VDEC2(_id, _name, _parent, _shift)	\
4062306a36Sopenharmony_ci	GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_cistatic const struct mtk_gate vdec_clks[] = {
4362306a36Sopenharmony_ci	/* VDEC0 */
4462306a36Sopenharmony_ci	GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
4562306a36Sopenharmony_ci	GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
4662306a36Sopenharmony_ci	/* VDEC1 */
4762306a36Sopenharmony_ci	GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
4862306a36Sopenharmony_ci	GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
4962306a36Sopenharmony_ci	/* VDEC2 */
5062306a36Sopenharmony_ci	GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
5162306a36Sopenharmony_ci};
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_cistatic const struct mtk_gate vdec_soc_clks[] = {
5462306a36Sopenharmony_ci	/* VDEC_SOC0 */
5562306a36Sopenharmony_ci	GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
5662306a36Sopenharmony_ci	GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
5762306a36Sopenharmony_ci	/* VDEC_SOC1 */
5862306a36Sopenharmony_ci	GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
5962306a36Sopenharmony_ci	GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
6062306a36Sopenharmony_ci	/* VDEC_SOC2 */
6162306a36Sopenharmony_ci	GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
6262306a36Sopenharmony_ci};
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_cistatic const struct mtk_clk_desc vdec_desc = {
6562306a36Sopenharmony_ci	.clks = vdec_clks,
6662306a36Sopenharmony_ci	.num_clks = ARRAY_SIZE(vdec_clks),
6762306a36Sopenharmony_ci};
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_cistatic const struct mtk_clk_desc vdec_soc_desc = {
7062306a36Sopenharmony_ci	.clks = vdec_soc_clks,
7162306a36Sopenharmony_ci	.num_clks = ARRAY_SIZE(vdec_soc_clks),
7262306a36Sopenharmony_ci};
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_cistatic const struct of_device_id of_match_clk_mt8192_vdec[] = {
7562306a36Sopenharmony_ci	{
7662306a36Sopenharmony_ci		.compatible = "mediatek,mt8192-vdecsys",
7762306a36Sopenharmony_ci		.data = &vdec_desc,
7862306a36Sopenharmony_ci	}, {
7962306a36Sopenharmony_ci		.compatible = "mediatek,mt8192-vdecsys_soc",
8062306a36Sopenharmony_ci		.data = &vdec_soc_desc,
8162306a36Sopenharmony_ci	}, {
8262306a36Sopenharmony_ci		/* sentinel */
8362306a36Sopenharmony_ci	}
8462306a36Sopenharmony_ci};
8562306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec);
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_cistatic struct platform_driver clk_mt8192_vdec_drv = {
8862306a36Sopenharmony_ci	.probe = mtk_clk_simple_probe,
8962306a36Sopenharmony_ci	.remove_new = mtk_clk_simple_remove,
9062306a36Sopenharmony_ci	.driver = {
9162306a36Sopenharmony_ci		.name = "clk-mt8192-vdec",
9262306a36Sopenharmony_ci		.of_match_table = of_match_clk_mt8192_vdec,
9362306a36Sopenharmony_ci	},
9462306a36Sopenharmony_ci};
9562306a36Sopenharmony_cimodule_platform_driver(clk_mt8192_vdec_drv);
9662306a36Sopenharmony_ciMODULE_LICENSE("GPL");
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