162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
262306a36Sopenharmony_ci//
362306a36Sopenharmony_ci// Copyright (c) 2022 MediaTek Inc.
462306a36Sopenharmony_ci// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
562306a36Sopenharmony_ci
662306a36Sopenharmony_ci#include <linux/clk-provider.h>
762306a36Sopenharmony_ci#include <linux/platform_device.h>
862306a36Sopenharmony_ci#include <dt-bindings/clock/mt8186-clk.h>
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#include "clk-gate.h"
1162306a36Sopenharmony_ci#include "clk-mtk.h"
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_cistatic const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
1462306a36Sopenharmony_ci	.set_ofs = 0xe08,
1562306a36Sopenharmony_ci	.clr_ofs = 0xe04,
1662306a36Sopenharmony_ci	.sta_ofs = 0xe00,
1762306a36Sopenharmony_ci};
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift)			\
2062306a36Sopenharmony_ci	GATE_MTK(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_cistatic const struct mtk_gate imp_iic_wrap_clks[] = {
2362306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0,
2462306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c0", "infra_ao_i2c_ap", 0),
2562306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1,
2662306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c1", "infra_ao_i2c_ap", 1),
2762306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2,
2862306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c2", "infra_ao_i2c_ap", 2),
2962306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3,
3062306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c3", "infra_ao_i2c_ap", 3),
3162306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4,
3262306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c4", "infra_ao_i2c_ap", 4),
3362306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5,
3462306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c5", "infra_ao_i2c_ap", 5),
3562306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6,
3662306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c6", "infra_ao_i2c_ap", 6),
3762306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7,
3862306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c7", "infra_ao_i2c_ap", 7),
3962306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8,
4062306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c8", "infra_ao_i2c_ap", 8),
4162306a36Sopenharmony_ci	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9,
4262306a36Sopenharmony_ci		"imp_iic_wrap_ap_clock_i2c9", "infra_ao_i2c_ap", 9),
4362306a36Sopenharmony_ci};
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_cistatic const struct mtk_clk_desc imp_iic_wrap_desc = {
4662306a36Sopenharmony_ci	.clks = imp_iic_wrap_clks,
4762306a36Sopenharmony_ci	.num_clks = ARRAY_SIZE(imp_iic_wrap_clks),
4862306a36Sopenharmony_ci};
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_cistatic const struct of_device_id of_match_clk_mt8186_imp_iic_wrap[] = {
5162306a36Sopenharmony_ci	{
5262306a36Sopenharmony_ci		.compatible = "mediatek,mt8186-imp_iic_wrap",
5362306a36Sopenharmony_ci		.data = &imp_iic_wrap_desc,
5462306a36Sopenharmony_ci	}, {
5562306a36Sopenharmony_ci		/* sentinel */
5662306a36Sopenharmony_ci	}
5762306a36Sopenharmony_ci};
5862306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, of_match_clk_mt8186_imp_iic_wrap);
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_cistatic struct platform_driver clk_mt8186_imp_iic_wrap_drv = {
6162306a36Sopenharmony_ci	.probe = mtk_clk_simple_probe,
6262306a36Sopenharmony_ci	.remove_new = mtk_clk_simple_remove,
6362306a36Sopenharmony_ci	.driver = {
6462306a36Sopenharmony_ci		.name = "clk-mt8186-imp_iic_wrap",
6562306a36Sopenharmony_ci		.of_match_table = of_match_clk_mt8186_imp_iic_wrap,
6662306a36Sopenharmony_ci	},
6762306a36Sopenharmony_ci};
6862306a36Sopenharmony_cimodule_platform_driver(clk_mt8186_imp_iic_wrap_drv);
6962306a36Sopenharmony_ciMODULE_LICENSE("GPL");
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