1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/module.h> 9#include <linux/of.h> 10#include <linux/of_address.h> 11#include <linux/platform_device.h> 12#include <linux/slab.h> 13#include <linux/mfd/syscon.h> 14#include <dt-bindings/clock/mt8135-clk.h> 15 16#include "clk-gate.h" 17#include "clk-mtk.h" 18#include "clk-pll.h" 19 20static DEFINE_SPINLOCK(mt8135_clk_lock); 21 22static const struct mtk_fixed_factor top_divs[] = { 23 FACTOR(CLK_DUMMY, "top_divs_dummy", "clk_null", 1, 1), 24 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), 25 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), 26 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), 27 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), 28 29 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), 30 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), 31 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), 32 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7), 33 34 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), 35 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), 36 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5), 37 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7), 38 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26), 39 40 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 41 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3), 42 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 43 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 44 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2), 45 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2), 46 47 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1), 48 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2), 49 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3), 50 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4), 51 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5), 52 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6), 53 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8), 54 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12), 55 56 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1), 57 58 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1), 59 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1), 60 61 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1), 62 63 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), 64 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), 65 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6), 66 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), 67 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), 68 69 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), 70 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), 71 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6), 72 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), 73 74 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1), 75 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), 76 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1), 77 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2), 78 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), 79 80 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1), 81 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4), 82 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8), 83 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16), 84 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24), 85 86 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 87 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 88 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 89 90 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1), 91 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1), 92 93 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1), 94 95 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2), 96 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3), 97 98 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2), 99 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4), 100 101 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), 102}; 103 104static const char * const axi_parents[] = { 105 "clk26m", 106 "syspll_d3", 107 "syspll_d4", 108 "syspll_d6", 109 "univpll_d5", 110 "univpll2_d2", 111 "syspll_d3p5" 112}; 113 114static const char * const smi_parents[] = { 115 "clk26m", 116 "clkph_mck", 117 "syspll_d2p5", 118 "syspll_d3", 119 "syspll_d8", 120 "univpll_d5", 121 "univpll1_d2", 122 "univpll1_d6", 123 "mmpll_d3", 124 "mmpll_d4", 125 "mmpll_d5", 126 "mmpll_d6", 127 "mmpll_d7", 128 "vdecpll", 129 "lvdspll" 130}; 131 132static const char * const mfg_parents[] = { 133 "clk26m", 134 "univpll1_d4", 135 "syspll_d2", 136 "syspll_d2p5", 137 "syspll_d3", 138 "univpll_d5", 139 "univpll1_d2", 140 "mmpll_d2", 141 "mmpll_d3", 142 "mmpll_d4", 143 "mmpll_d5", 144 "mmpll_d6", 145 "mmpll_d7" 146}; 147 148static const char * const irda_parents[] = { 149 "clk26m", 150 "univpll2_d8", 151 "univpll1_d6" 152}; 153 154static const char * const cam_parents[] = { 155 "clk26m", 156 "syspll_d3", 157 "syspll_d3p5", 158 "syspll_d4", 159 "univpll_d5", 160 "univpll2_d2", 161 "univpll_d7", 162 "univpll1_d4" 163}; 164 165static const char * const aud_intbus_parents[] = { 166 "clk26m", 167 "syspll_d6", 168 "univpll_d10" 169}; 170 171static const char * const jpg_parents[] = { 172 "clk26m", 173 "syspll_d5", 174 "syspll_d4", 175 "syspll_d3", 176 "univpll_d7", 177 "univpll2_d2", 178 "univpll_d5" 179}; 180 181static const char * const disp_parents[] = { 182 "clk26m", 183 "syspll_d3p5", 184 "syspll_d3", 185 "univpll2_d2", 186 "univpll_d5", 187 "univpll1_d2", 188 "lvdspll", 189 "vdecpll" 190}; 191 192static const char * const msdc30_parents[] = { 193 "clk26m", 194 "syspll_d6", 195 "syspll_d5", 196 "univpll1_d4", 197 "univpll2_d4", 198 "msdcpll" 199}; 200 201static const char * const usb20_parents[] = { 202 "clk26m", 203 "univpll2_d6", 204 "univpll1_d10" 205}; 206 207static const char * const venc_parents[] = { 208 "clk26m", 209 "syspll_d3", 210 "syspll_d8", 211 "univpll_d5", 212 "univpll1_d6", 213 "mmpll_d4", 214 "mmpll_d5", 215 "mmpll_d6" 216}; 217 218static const char * const spi_parents[] = { 219 "clk26m", 220 "syspll_d6", 221 "syspll_d8", 222 "syspll_d10", 223 "univpll1_d6", 224 "univpll1_d8" 225}; 226 227static const char * const uart_parents[] = { 228 "clk26m", 229 "univpll2_d8" 230}; 231 232static const char * const mem_parents[] = { 233 "clk26m", 234 "clkph_mck" 235}; 236 237static const char * const camtg_parents[] = { 238 "clk26m", 239 "univpll_d26", 240 "univpll1_d6", 241 "syspll_d16", 242 "syspll_d8" 243}; 244 245static const char * const audio_parents[] = { 246 "clk26m", 247 "syspll_d24" 248}; 249 250static const char * const fix_parents[] = { 251 "rtc32k", 252 "clk26m", 253 "univpll_d5", 254 "univpll_d7", 255 "univpll1_d2", 256 "univpll1_d4", 257 "univpll1_d6", 258 "univpll1_d8" 259}; 260 261static const char * const vdec_parents[] = { 262 "clk26m", 263 "vdecpll", 264 "clkph_mck", 265 "syspll_d2p5", 266 "syspll_d3", 267 "syspll_d3p5", 268 "syspll_d4", 269 "syspll_d5", 270 "syspll_d6", 271 "syspll_d8", 272 "univpll1_d2", 273 "univpll2_d2", 274 "univpll_d7", 275 "univpll_d10", 276 "univpll2_d4", 277 "lvdspll" 278}; 279 280static const char * const ddrphycfg_parents[] = { 281 "clk26m", 282 "axi_sel", 283 "syspll_d12" 284}; 285 286static const char * const dpilvds_parents[] = { 287 "clk26m", 288 "lvdspll", 289 "lvdspll_d2", 290 "lvdspll_d4", 291 "lvdspll_d8" 292}; 293 294static const char * const pmicspi_parents[] = { 295 "clk26m", 296 "univpll2_d6", 297 "syspll_d8", 298 "syspll_d10", 299 "univpll1_d10", 300 "mempll_mck_d4", 301 "univpll_d26", 302 "syspll_d24" 303}; 304 305static const char * const smi_mfg_as_parents[] = { 306 "clk26m", 307 "smi_sel", 308 "mfg_sel", 309 "mem_sel" 310}; 311 312static const char * const gcpu_parents[] = { 313 "clk26m", 314 "syspll_d4", 315 "univpll_d7", 316 "syspll_d5", 317 "syspll_d6" 318}; 319 320static const char * const dpi1_parents[] = { 321 "clk26m", 322 "tvhdmi_h_ck", 323 "tvhdmi_d2", 324 "tvhdmi_d4" 325}; 326 327static const char * const cci_parents[] = { 328 "clk26m", 329 "mainpll_537p3m", 330 "univpll_d3", 331 "syspll_d2p5", 332 "syspll_d3", 333 "syspll_d5" 334}; 335 336static const char * const apll_parents[] = { 337 "clk26m", 338 "apll_ck", 339 "apll_d4", 340 "apll_d8", 341 "apll_d16", 342 "apll_d24" 343}; 344 345static const char * const hdmipll_parents[] = { 346 "clk26m", 347 "hdmitx_clkdig_cts", 348 "hdmitx_clkdig_d2", 349 "hdmitx_clkdig_d3" 350}; 351 352static const struct mtk_composite top_muxes[] = { 353 /* CLK_CFG_0 */ 354 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 355 0x0140, 0, 3, INVALID_MUX_GATE_BIT), 356 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15), 357 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23), 358 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31), 359 /* CLK_CFG_1 */ 360 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7), 361 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 362 0x0144, 8, 2, 15), 363 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23), 364 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31), 365 /* CLK_CFG_2 */ 366 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7), 367 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15), 368 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23), 369 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31), 370 /* CLK_CFG_3 */ 371 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7), 372 /* CLK_CFG_4 */ 373 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15), 374 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23), 375 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31), 376 /* CLK_CFG_6 */ 377 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7), 378 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15), 379 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31), 380 /* CLK_CFG_7 */ 381 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7), 382 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15), 383 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 384 0x015c, 16, 2, 23), 385 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31), 386 /* CLK_CFG_8 */ 387 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7), 388 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15), 389 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents, 390 0x0164, 16, 2, 23), 391 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), 392 /* CLK_CFG_9 */ 393 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), 394 MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL), 395 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), 396 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), 397}; 398 399static const struct mtk_gate_regs infra_cg_regs = { 400 .set_ofs = 0x0040, 401 .clr_ofs = 0x0044, 402 .sta_ofs = 0x0048, 403}; 404 405#define GATE_ICG(_id, _name, _parent, _shift) \ 406 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 407 408#define GATE_ICG_AO(_id, _name, _parent, _shift) \ 409 GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \ 410 &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) 411 412static const struct mtk_gate infra_clks[] = { 413 GATE_DUMMY(CLK_DUMMY, "infra_dummy"), 414 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), 415 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 416 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), 417 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), 418 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 419 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), 420 GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 421 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), 422 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), 423 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), 424 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2), 425 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1), 426 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0), 427}; 428 429static const struct mtk_gate_regs peri0_cg_regs = { 430 .set_ofs = 0x0008, 431 .clr_ofs = 0x0010, 432 .sta_ofs = 0x0018, 433}; 434 435static const struct mtk_gate_regs peri1_cg_regs = { 436 .set_ofs = 0x000c, 437 .clr_ofs = 0x0014, 438 .sta_ofs = 0x001c, 439}; 440 441#define GATE_PERI0(_id, _name, _parent, _shift) \ 442 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 443 444#define GATE_PERI1(_id, _name, _parent, _shift) \ 445 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 446 447static const struct mtk_gate peri_gates[] = { 448 GATE_DUMMY(CLK_DUMMY, "peri_dummy"), 449 /* PERI0 */ 450 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), 451 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), 452 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29), 453 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28), 454 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27), 455 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26), 456 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25), 457 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24), 458 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23), 459 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22), 460 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21), 461 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20), 462 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19), 463 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18), 464 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17), 465 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16), 466 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15), 467 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14), 468 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13), 469 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 470 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 471 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 472 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 473 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), 474 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), 475 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), 476 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), 477 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), 478 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), 479 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), 480 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 481 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0), 482 /* PERI1 */ 483 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8), 484 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7), 485 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6), 486 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5), 487 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4), 488 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3), 489 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2), 490 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1), 491 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), 492}; 493 494static const char * const uart_ck_sel_parents[] = { 495 "clk26m", 496 "uart_sel", 497}; 498 499static const struct mtk_composite peri_clks[] = { 500 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), 501 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), 502 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), 503 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), 504}; 505 506static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 507static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 508 509static const struct mtk_clk_rst_desc clk_rst_desc[] = { 510 /* infrasys */ 511 { 512 .version = MTK_RST_SIMPLE, 513 .rst_bank_ofs = infrasys_rst_ofs, 514 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 515 }, 516 /* pericfg */ 517 { 518 .version = MTK_RST_SIMPLE, 519 .rst_bank_ofs = pericfg_rst_ofs, 520 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 521 } 522}; 523 524static const struct mtk_clk_desc infra_desc = { 525 .clks = infra_clks, 526 .num_clks = ARRAY_SIZE(infra_clks), 527 .rst_desc = &clk_rst_desc[0], 528}; 529 530static const struct mtk_clk_desc peri_desc = { 531 .clks = peri_gates, 532 .num_clks = ARRAY_SIZE(peri_gates), 533 .composite_clks = peri_clks, 534 .num_composite_clks = ARRAY_SIZE(peri_clks), 535 .clk_lock = &mt8135_clk_lock, 536 .rst_desc = &clk_rst_desc[1], 537}; 538 539static const struct mtk_clk_desc topck_desc = { 540 .factor_clks = top_divs, 541 .num_factor_clks = ARRAY_SIZE(top_divs), 542 .composite_clks = top_muxes, 543 .num_composite_clks = ARRAY_SIZE(top_muxes), 544 .clk_lock = &mt8135_clk_lock, 545}; 546 547static const struct of_device_id of_match_clk_mt8135[] = { 548 { .compatible = "mediatek,mt8135-infracfg", .data = &infra_desc }, 549 { .compatible = "mediatek,mt8135-pericfg", .data = &peri_desc }, 550 { .compatible = "mediatek,mt8135-topckgen", .data = &topck_desc }, 551 { /* sentinel */ } 552}; 553MODULE_DEVICE_TABLE(of, of_match_clk_mt8135); 554 555static struct platform_driver clk_mt8135_drv = { 556 .driver = { 557 .name = "clk-mt8135", 558 .of_match_table = of_match_clk_mt8135, 559 }, 560 .probe = mtk_clk_simple_probe, 561 .remove_new = mtk_clk_simple_remove, 562}; 563module_platform_driver(clk_mt8135_drv); 564 565MODULE_DESCRIPTION("MediaTek MT8135 clocks driver"); 566MODULE_LICENSE("GPL"); 567