162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2022 MediaTek Inc. 462306a36Sopenharmony_ci * Author: Edward-JW Yang <edward-jw.yang@mediatek.com> 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#ifndef __CLK_FHCTL_H 862306a36Sopenharmony_ci#define __CLK_FHCTL_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include "clk-pllfh.h" 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cienum fhctl_variant { 1362306a36Sopenharmony_ci FHCTL_PLLFH_V1, 1462306a36Sopenharmony_ci FHCTL_PLLFH_V2, 1562306a36Sopenharmony_ci}; 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_cistruct fhctl_offset { 1862306a36Sopenharmony_ci u32 offset_hp_en; 1962306a36Sopenharmony_ci u32 offset_clk_con; 2062306a36Sopenharmony_ci u32 offset_rst_con; 2162306a36Sopenharmony_ci u32 offset_slope0; 2262306a36Sopenharmony_ci u32 offset_slope1; 2362306a36Sopenharmony_ci u32 offset_cfg; 2462306a36Sopenharmony_ci u32 offset_updnlmt; 2562306a36Sopenharmony_ci u32 offset_dds; 2662306a36Sopenharmony_ci u32 offset_dvfs; 2762306a36Sopenharmony_ci u32 offset_mon; 2862306a36Sopenharmony_ci}; 2962306a36Sopenharmony_ciconst struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v); 3062306a36Sopenharmony_ciconst struct fh_operation *fhctl_get_ops(void); 3162306a36Sopenharmony_civoid fhctl_hw_init(struct mtk_fh *fh); 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#endif 34