162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2018 David Lechner <david@lechnology.com>
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#include <linux/clkdev.h>
962306a36Sopenharmony_ci#include <linux/clk/davinci.h>
1062306a36Sopenharmony_ci#include <linux/bitops.h>
1162306a36Sopenharmony_ci#include <linux/init.h>
1262306a36Sopenharmony_ci#include <linux/types.h>
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_ci#include "pll.h"
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_cistatic const struct davinci_pll_clk_info da830_pll_info = {
1762306a36Sopenharmony_ci	.name = "pll0",
1862306a36Sopenharmony_ci	.pllm_mask = GENMASK(4, 0),
1962306a36Sopenharmony_ci	.pllm_min = 4,
2062306a36Sopenharmony_ci	.pllm_max = 32,
2162306a36Sopenharmony_ci	.pllout_min_rate = 300000000,
2262306a36Sopenharmony_ci	.pllout_max_rate = 600000000,
2362306a36Sopenharmony_ci	.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
2462306a36Sopenharmony_ci};
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci/*
2762306a36Sopenharmony_ci * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
2862306a36Sopenharmony_ci * meaning that we could change the divider as long as we keep the correct
2962306a36Sopenharmony_ci * ratio between all of the clocks, but we don't support that because there is
3062306a36Sopenharmony_ci * currently not a need for it.
3162306a36Sopenharmony_ci */
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ciSYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
3462306a36Sopenharmony_ciSYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
3562306a36Sopenharmony_ciSYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
3662306a36Sopenharmony_ciSYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
3762306a36Sopenharmony_ciSYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
3862306a36Sopenharmony_ciSYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ciint da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
4162306a36Sopenharmony_ci{
4262306a36Sopenharmony_ci	struct clk *clk;
4362306a36Sopenharmony_ci
4462306a36Sopenharmony_ci	davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
4762306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
4862306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
5162306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ci	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
5462306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
5562306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_ci	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
5862306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
6162306a36Sopenharmony_ci	clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci	clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
6662306a36Sopenharmony_ci	clk_register_clkdev(clk, NULL, "i2c_davinci.1");
6762306a36Sopenharmony_ci	clk_register_clkdev(clk, "timer0", NULL);
6862306a36Sopenharmony_ci	clk_register_clkdev(clk, NULL, "davinci-wdt");
6962306a36Sopenharmony_ci
7062306a36Sopenharmony_ci	return 0;
7162306a36Sopenharmony_ci}
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