1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * UniNorth AGPGART routines. 4 */ 5#include <linux/module.h> 6#include <linux/of.h> 7#include <linux/pci.h> 8#include <linux/slab.h> 9#include <linux/init.h> 10#include <linux/pagemap.h> 11#include <linux/agp_backend.h> 12#include <linux/delay.h> 13#include <linux/vmalloc.h> 14#include <asm/uninorth.h> 15#include <asm/prom.h> 16#include <asm/pmac_feature.h> 17#include "agp.h" 18 19/* 20 * NOTES for uninorth3 (G5 AGP) supports : 21 * 22 * There maybe also possibility to have bigger cache line size for 23 * agp (see pmac_pci.c and look for cache line). Need to be investigated 24 * by someone. 25 * 26 * PAGE size are hardcoded but this may change, see asm/page.h. 27 * 28 * Jerome Glisse <j.glisse@gmail.com> 29 */ 30static int uninorth_rev; 31static int is_u3; 32static u32 scratch_value; 33 34#define DEFAULT_APERTURE_SIZE 256 35#define DEFAULT_APERTURE_STRING "256" 36static char *aperture = NULL; 37 38static int uninorth_fetch_size(void) 39{ 40 int i, size = 0; 41 struct aper_size_info_32 *values = 42 A_SIZE_32(agp_bridge->driver->aperture_sizes); 43 44 if (aperture) { 45 char *save = aperture; 46 47 size = memparse(aperture, &aperture) >> 20; 48 aperture = save; 49 50 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 51 if (size == values[i].size) 52 break; 53 54 if (i == agp_bridge->driver->num_aperture_sizes) { 55 dev_err(&agp_bridge->dev->dev, "invalid aperture size, " 56 "using default\n"); 57 size = 0; 58 aperture = NULL; 59 } 60 } 61 62 if (!size) { 63 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 64 if (values[i].size == DEFAULT_APERTURE_SIZE) 65 break; 66 } 67 68 agp_bridge->previous_size = 69 agp_bridge->current_size = (void *)(values + i); 70 agp_bridge->aperture_size_idx = i; 71 return values[i].size; 72} 73 74static void uninorth_tlbflush(struct agp_memory *mem) 75{ 76 u32 ctrl = UNI_N_CFG_GART_ENABLE; 77 78 if (is_u3) 79 ctrl |= U3_N_CFG_GART_PERFRD; 80 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 81 ctrl | UNI_N_CFG_GART_INVAL); 82 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 83 84 if (!mem && uninorth_rev <= 0x30) { 85 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 86 ctrl | UNI_N_CFG_GART_2xRESET); 87 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 88 ctrl); 89 } 90} 91 92static void uninorth_cleanup(void) 93{ 94 u32 tmp; 95 96 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); 97 if (!(tmp & UNI_N_CFG_GART_ENABLE)) 98 return; 99 tmp |= UNI_N_CFG_GART_INVAL; 100 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); 101 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); 102 103 if (uninorth_rev <= 0x30) { 104 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 105 UNI_N_CFG_GART_2xRESET); 106 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 107 0); 108 } 109} 110 111static int uninorth_configure(void) 112{ 113 struct aper_size_info_32 *current_size; 114 115 current_size = A_SIZE_32(agp_bridge->current_size); 116 117 dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n", 118 current_size->size_value); 119 120 /* aperture size and gatt addr */ 121 pci_write_config_dword(agp_bridge->dev, 122 UNI_N_CFG_GART_BASE, 123 (agp_bridge->gatt_bus_addr & 0xfffff000) 124 | current_size->size_value); 125 126 /* HACK ALERT 127 * UniNorth seem to be buggy enough not to handle properly when 128 * the AGP aperture isn't mapped at bus physical address 0 129 */ 130 agp_bridge->gart_bus_addr = 0; 131#ifdef CONFIG_PPC64 132 /* Assume U3 or later on PPC64 systems */ 133 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ 134 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, 135 (agp_bridge->gatt_bus_addr >> 32) & 0xf); 136#else 137 pci_write_config_dword(agp_bridge->dev, 138 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); 139#endif 140 141 if (is_u3) { 142 pci_write_config_dword(agp_bridge->dev, 143 UNI_N_CFG_GART_DUMMY_PAGE, 144 page_to_phys(agp_bridge->scratch_page_page) >> 12); 145 } 146 147 return 0; 148} 149 150static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 151{ 152 int i, num_entries; 153 void *temp; 154 u32 *gp; 155 int mask_type; 156 157 if (type != mem->type) 158 return -EINVAL; 159 160 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 161 if (mask_type != 0) { 162 /* We know nothing of memory types */ 163 return -EINVAL; 164 } 165 166 if (mem->page_count == 0) 167 return 0; 168 169 temp = agp_bridge->current_size; 170 num_entries = A_SIZE_32(temp)->num_entries; 171 172 if ((pg_start + mem->page_count) > num_entries) 173 return -EINVAL; 174 175 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 176 for (i = 0; i < mem->page_count; ++i) { 177 if (gp[i] != scratch_value) { 178 dev_info(&agp_bridge->dev->dev, 179 "uninorth_insert_memory: entry 0x%x occupied (%x)\n", 180 i, gp[i]); 181 return -EBUSY; 182 } 183 } 184 185 for (i = 0; i < mem->page_count; i++) { 186 if (is_u3) 187 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL; 188 else 189 gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 190 0x1UL); 191 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])), 192 (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000); 193 } 194 mb(); 195 uninorth_tlbflush(mem); 196 197 return 0; 198} 199 200static int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 201{ 202 size_t i; 203 u32 *gp; 204 int mask_type; 205 206 if (type != mem->type) 207 return -EINVAL; 208 209 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 210 if (mask_type != 0) { 211 /* We know nothing of memory types */ 212 return -EINVAL; 213 } 214 215 if (mem->page_count == 0) 216 return 0; 217 218 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 219 for (i = 0; i < mem->page_count; ++i) { 220 gp[i] = scratch_value; 221 } 222 mb(); 223 uninorth_tlbflush(mem); 224 225 return 0; 226} 227 228static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) 229{ 230 u32 command, scratch, status; 231 int timeout; 232 233 pci_read_config_dword(bridge->dev, 234 bridge->capndx + PCI_AGP_STATUS, 235 &status); 236 237 command = agp_collect_device_status(bridge, mode, status); 238 command |= PCI_AGP_COMMAND_AGP; 239 240 if (uninorth_rev == 0x21) { 241 /* 242 * Darwin disable AGP 4x on this revision, thus we 243 * may assume it's broken. This is an AGP2 controller. 244 */ 245 command &= ~AGPSTAT2_4X; 246 } 247 248 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { 249 /* 250 * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, 251 * 2.2 and 2.3, Darwin do so. 252 */ 253 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) 254 command = (command & ~AGPSTAT_RQ_DEPTH) 255 | (7 << AGPSTAT_RQ_DEPTH_SHIFT); 256 } 257 258 uninorth_tlbflush(NULL); 259 260 timeout = 0; 261 do { 262 pci_write_config_dword(bridge->dev, 263 bridge->capndx + PCI_AGP_COMMAND, 264 command); 265 pci_read_config_dword(bridge->dev, 266 bridge->capndx + PCI_AGP_COMMAND, 267 &scratch); 268 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); 269 if ((scratch & PCI_AGP_COMMAND_AGP) == 0) 270 dev_err(&bridge->dev->dev, "can't write UniNorth AGP " 271 "command register\n"); 272 273 if (uninorth_rev >= 0x30) { 274 /* This is an AGP V3 */ 275 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0); 276 } else { 277 /* AGP V2 */ 278 agp_device_command(command, false); 279 } 280 281 uninorth_tlbflush(NULL); 282} 283 284#ifdef CONFIG_PM 285/* 286 * These Power Management routines are _not_ called by the normal PCI PM layer, 287 * but directly by the video driver through function pointers in the device 288 * tree. 289 */ 290static int agp_uninorth_suspend(struct pci_dev *pdev) 291{ 292 struct agp_bridge_data *bridge; 293 u32 cmd; 294 u8 agp; 295 struct pci_dev *device = NULL; 296 297 bridge = agp_find_bridge(pdev); 298 if (bridge == NULL) 299 return -ENODEV; 300 301 /* Only one suspend supported */ 302 if (bridge->dev_private_data) 303 return 0; 304 305 /* turn off AGP on the video chip, if it was enabled */ 306 for_each_pci_dev(device) { 307 /* Don't touch the bridge yet, device first */ 308 if (device == pdev) 309 continue; 310 /* Only deal with devices on the same bus here, no Mac has a P2P 311 * bridge on the AGP port, and mucking around the entire PCI 312 * tree is source of problems on some machines because of a bug 313 * in some versions of pci_find_capability() when hitting a dead 314 * device 315 */ 316 if (device->bus != pdev->bus) 317 continue; 318 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 319 if (!agp) 320 continue; 321 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); 322 if (!(cmd & PCI_AGP_COMMAND_AGP)) 323 continue; 324 dev_info(&pdev->dev, "disabling AGP on device %s\n", 325 pci_name(device)); 326 cmd &= ~PCI_AGP_COMMAND_AGP; 327 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); 328 } 329 330 /* turn off AGP on the bridge */ 331 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); 332 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); 333 bridge->dev_private_data = (void *)(long)cmd; 334 if (cmd & PCI_AGP_COMMAND_AGP) { 335 dev_info(&pdev->dev, "disabling AGP on bridge\n"); 336 cmd &= ~PCI_AGP_COMMAND_AGP; 337 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); 338 } 339 /* turn off the GART */ 340 uninorth_cleanup(); 341 342 return 0; 343} 344 345static int agp_uninorth_resume(struct pci_dev *pdev) 346{ 347 struct agp_bridge_data *bridge; 348 u32 command; 349 350 bridge = agp_find_bridge(pdev); 351 if (bridge == NULL) 352 return -ENODEV; 353 354 command = (long)bridge->dev_private_data; 355 bridge->dev_private_data = NULL; 356 if (!(command & PCI_AGP_COMMAND_AGP)) 357 return 0; 358 359 uninorth_agp_enable(bridge, command); 360 361 return 0; 362} 363#endif /* CONFIG_PM */ 364 365static struct { 366 struct page **pages_arr; 367} uninorth_priv; 368 369static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) 370{ 371 char *table; 372 char *table_end; 373 int size; 374 int page_order; 375 int num_entries; 376 int i; 377 void *temp; 378 struct page *page; 379 380 /* We can't handle 2 level gatt's */ 381 if (bridge->driver->size_type == LVL2_APER_SIZE) 382 return -EINVAL; 383 384 table = NULL; 385 i = bridge->aperture_size_idx; 386 temp = bridge->current_size; 387 size = page_order = num_entries = 0; 388 389 do { 390 size = A_SIZE_32(temp)->size; 391 page_order = A_SIZE_32(temp)->page_order; 392 num_entries = A_SIZE_32(temp)->num_entries; 393 394 table = (char *) __get_free_pages(GFP_KERNEL, page_order); 395 396 if (table == NULL) { 397 i++; 398 bridge->current_size = A_IDX32(bridge); 399 } else { 400 bridge->aperture_size_idx = i; 401 } 402 } while (!table && (i < bridge->driver->num_aperture_sizes)); 403 404 if (table == NULL) 405 return -ENOMEM; 406 407 uninorth_priv.pages_arr = kmalloc_array(1 << page_order, 408 sizeof(struct page *), 409 GFP_KERNEL); 410 if (uninorth_priv.pages_arr == NULL) 411 goto enomem; 412 413 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 414 415 for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end); 416 page++, i++) { 417 SetPageReserved(page); 418 uninorth_priv.pages_arr[i] = page; 419 } 420 421 bridge->gatt_table_real = (u32 *) table; 422 /* Need to clear out any dirty data still sitting in caches */ 423 flush_dcache_range((unsigned long)table, 424 (unsigned long)table_end + 1); 425 bridge->gatt_table = vmap(uninorth_priv.pages_arr, (1 << page_order), 0, PAGE_KERNEL_NCG); 426 427 if (bridge->gatt_table == NULL) 428 goto enomem; 429 430 bridge->gatt_bus_addr = virt_to_phys(table); 431 432 if (is_u3) 433 scratch_value = (page_to_phys(agp_bridge->scratch_page_page) >> PAGE_SHIFT) | 0x80000000UL; 434 else 435 scratch_value = cpu_to_le32((page_to_phys(agp_bridge->scratch_page_page) & 0xFFFFF000UL) | 436 0x1UL); 437 for (i = 0; i < num_entries; i++) 438 bridge->gatt_table[i] = scratch_value; 439 440 return 0; 441 442enomem: 443 kfree(uninorth_priv.pages_arr); 444 if (table) 445 free_pages((unsigned long)table, page_order); 446 return -ENOMEM; 447} 448 449static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) 450{ 451 int page_order; 452 char *table, *table_end; 453 void *temp; 454 struct page *page; 455 456 temp = bridge->current_size; 457 page_order = A_SIZE_32(temp)->page_order; 458 459 /* Do not worry about freeing memory, because if this is 460 * called, then all agp memory is deallocated and removed 461 * from the table. 462 */ 463 464 vunmap(bridge->gatt_table); 465 kfree(uninorth_priv.pages_arr); 466 table = (char *) bridge->gatt_table_real; 467 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 468 469 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 470 ClearPageReserved(page); 471 472 free_pages((unsigned long) bridge->gatt_table_real, page_order); 473 474 return 0; 475} 476 477static void null_cache_flush(void) 478{ 479 mb(); 480} 481 482/* Setup function */ 483 484static const struct aper_size_info_32 uninorth_sizes[] = 485{ 486 {256, 65536, 6, 64}, 487 {128, 32768, 5, 32}, 488 {64, 16384, 4, 16}, 489 {32, 8192, 3, 8}, 490 {16, 4096, 2, 4}, 491 {8, 2048, 1, 2}, 492 {4, 1024, 0, 1} 493}; 494 495/* 496 * Not sure that u3 supports that high aperture sizes but it 497 * would strange if it did not :) 498 */ 499static const struct aper_size_info_32 u3_sizes[] = 500{ 501 {512, 131072, 7, 128}, 502 {256, 65536, 6, 64}, 503 {128, 32768, 5, 32}, 504 {64, 16384, 4, 16}, 505 {32, 8192, 3, 8}, 506 {16, 4096, 2, 4}, 507 {8, 2048, 1, 2}, 508 {4, 1024, 0, 1} 509}; 510 511const struct agp_bridge_driver uninorth_agp_driver = { 512 .owner = THIS_MODULE, 513 .aperture_sizes = (void *)uninorth_sizes, 514 .size_type = U32_APER_SIZE, 515 .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes), 516 .configure = uninorth_configure, 517 .fetch_size = uninorth_fetch_size, 518 .cleanup = uninorth_cleanup, 519 .tlb_flush = uninorth_tlbflush, 520 .mask_memory = agp_generic_mask_memory, 521 .masks = NULL, 522 .cache_flush = null_cache_flush, 523 .agp_enable = uninorth_agp_enable, 524 .create_gatt_table = uninorth_create_gatt_table, 525 .free_gatt_table = uninorth_free_gatt_table, 526 .insert_memory = uninorth_insert_memory, 527 .remove_memory = uninorth_remove_memory, 528 .alloc_by_type = agp_generic_alloc_by_type, 529 .free_by_type = agp_generic_free_by_type, 530 .agp_alloc_page = agp_generic_alloc_page, 531 .agp_alloc_pages = agp_generic_alloc_pages, 532 .agp_destroy_page = agp_generic_destroy_page, 533 .agp_destroy_pages = agp_generic_destroy_pages, 534 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 535 .cant_use_aperture = true, 536 .needs_scratch_page = true, 537}; 538 539const struct agp_bridge_driver u3_agp_driver = { 540 .owner = THIS_MODULE, 541 .aperture_sizes = (void *)u3_sizes, 542 .size_type = U32_APER_SIZE, 543 .num_aperture_sizes = ARRAY_SIZE(u3_sizes), 544 .configure = uninorth_configure, 545 .fetch_size = uninorth_fetch_size, 546 .cleanup = uninorth_cleanup, 547 .tlb_flush = uninorth_tlbflush, 548 .mask_memory = agp_generic_mask_memory, 549 .masks = NULL, 550 .cache_flush = null_cache_flush, 551 .agp_enable = uninorth_agp_enable, 552 .create_gatt_table = uninorth_create_gatt_table, 553 .free_gatt_table = uninorth_free_gatt_table, 554 .insert_memory = uninorth_insert_memory, 555 .remove_memory = uninorth_remove_memory, 556 .alloc_by_type = agp_generic_alloc_by_type, 557 .free_by_type = agp_generic_free_by_type, 558 .agp_alloc_page = agp_generic_alloc_page, 559 .agp_alloc_pages = agp_generic_alloc_pages, 560 .agp_destroy_page = agp_generic_destroy_page, 561 .agp_destroy_pages = agp_generic_destroy_pages, 562 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 563 .cant_use_aperture = true, 564 .needs_scratch_page = true, 565}; 566 567static struct agp_device_ids uninorth_agp_device_ids[] = { 568 { 569 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, 570 .chipset_name = "UniNorth", 571 }, 572 { 573 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, 574 .chipset_name = "UniNorth/Pangea", 575 }, 576 { 577 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, 578 .chipset_name = "UniNorth 1.5", 579 }, 580 { 581 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, 582 .chipset_name = "UniNorth 2", 583 }, 584 { 585 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, 586 .chipset_name = "U3", 587 }, 588 { 589 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, 590 .chipset_name = "U3L", 591 }, 592 { 593 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, 594 .chipset_name = "U3H", 595 }, 596 { 597 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP, 598 .chipset_name = "UniNorth/Intrepid2", 599 }, 600}; 601 602static int agp_uninorth_probe(struct pci_dev *pdev, 603 const struct pci_device_id *ent) 604{ 605 struct agp_device_ids *devs = uninorth_agp_device_ids; 606 struct agp_bridge_data *bridge; 607 struct device_node *uninorth_node; 608 u8 cap_ptr; 609 int j; 610 611 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 612 if (cap_ptr == 0) 613 return -ENODEV; 614 615 /* probe for known chipsets */ 616 for (j = 0; devs[j].chipset_name != NULL; ++j) { 617 if (pdev->device == devs[j].device_id) { 618 dev_info(&pdev->dev, "Apple %s chipset\n", 619 devs[j].chipset_name); 620 goto found; 621 } 622 } 623 624 dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n", 625 pdev->vendor, pdev->device); 626 return -ENODEV; 627 628 found: 629 /* Set revision to 0 if we could not read it. */ 630 uninorth_rev = 0; 631 is_u3 = 0; 632 /* Locate core99 Uni-N */ 633 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 634 /* Locate G5 u3 */ 635 if (uninorth_node == NULL) { 636 is_u3 = 1; 637 uninorth_node = of_find_node_by_name(NULL, "u3"); 638 } 639 if (uninorth_node) { 640 const int *revprop = of_get_property(uninorth_node, 641 "device-rev", NULL); 642 if (revprop != NULL) 643 uninorth_rev = *revprop & 0x3f; 644 of_node_put(uninorth_node); 645 } 646 647#ifdef CONFIG_PM 648 /* Inform platform of our suspend/resume caps */ 649 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); 650#endif 651 652 /* Allocate & setup our driver */ 653 bridge = agp_alloc_bridge(); 654 if (!bridge) 655 return -ENOMEM; 656 657 if (is_u3) 658 bridge->driver = &u3_agp_driver; 659 else 660 bridge->driver = &uninorth_agp_driver; 661 662 bridge->dev = pdev; 663 bridge->capndx = cap_ptr; 664 bridge->flags = AGP_ERRATA_FASTWRITES; 665 666 /* Fill in the mode register */ 667 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); 668 669 pci_set_drvdata(pdev, bridge); 670 return agp_add_bridge(bridge); 671} 672 673static void agp_uninorth_remove(struct pci_dev *pdev) 674{ 675 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 676 677#ifdef CONFIG_PM 678 /* Inform platform of our suspend/resume caps */ 679 pmac_register_agp_pm(pdev, NULL, NULL); 680#endif 681 682 agp_remove_bridge(bridge); 683 agp_put_bridge(bridge); 684} 685 686static const struct pci_device_id agp_uninorth_pci_table[] = { 687 { 688 .class = (PCI_CLASS_BRIDGE_HOST << 8), 689 .class_mask = ~0, 690 .vendor = PCI_VENDOR_ID_APPLE, 691 .device = PCI_ANY_ID, 692 .subvendor = PCI_ANY_ID, 693 .subdevice = PCI_ANY_ID, 694 }, 695 { } 696}; 697 698MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); 699 700static struct pci_driver agp_uninorth_pci_driver = { 701 .name = "agpgart-uninorth", 702 .id_table = agp_uninorth_pci_table, 703 .probe = agp_uninorth_probe, 704 .remove = agp_uninorth_remove, 705}; 706 707static int __init agp_uninorth_init(void) 708{ 709 if (agp_off) 710 return -EINVAL; 711 return pci_register_driver(&agp_uninorth_pci_driver); 712} 713 714static void __exit agp_uninorth_cleanup(void) 715{ 716 pci_unregister_driver(&agp_uninorth_pci_driver); 717} 718 719module_init(agp_uninorth_init); 720module_exit(agp_uninorth_cleanup); 721 722module_param(aperture, charp, 0); 723MODULE_PARM_DESC(aperture, 724 "Aperture size, must be power of two between 4MB and an\n" 725 "\t\tupper limit specific to the UniNorth revision.\n" 726 "\t\tDefault: " DEFAULT_APERTURE_STRING "M"); 727 728MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); 729MODULE_LICENSE("GPL"); 730