1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7#include <linux/bitfield.h> 8#include <linux/debugfs.h> 9#include <linux/device.h> 10#include <linux/dma-direction.h> 11#include <linux/dma-mapping.h> 12#include <linux/idr.h> 13#include <linux/interrupt.h> 14#include <linux/list.h> 15#include <linux/mhi.h> 16#include <linux/mod_devicetable.h> 17#include <linux/module.h> 18#include <linux/slab.h> 19#include <linux/vmalloc.h> 20#include <linux/wait.h> 21#include "internal.h" 22 23static DEFINE_IDA(mhi_controller_ida); 24 25const char * const mhi_ee_str[MHI_EE_MAX] = { 26 [MHI_EE_PBL] = "PRIMARY BOOTLOADER", 27 [MHI_EE_SBL] = "SECONDARY BOOTLOADER", 28 [MHI_EE_AMSS] = "MISSION MODE", 29 [MHI_EE_RDDM] = "RAMDUMP DOWNLOAD MODE", 30 [MHI_EE_WFW] = "WLAN FIRMWARE", 31 [MHI_EE_PTHRU] = "PASS THROUGH", 32 [MHI_EE_EDL] = "EMERGENCY DOWNLOAD", 33 [MHI_EE_FP] = "FLASH PROGRAMMER", 34 [MHI_EE_DISABLE_TRANSITION] = "DISABLE", 35 [MHI_EE_NOT_SUPPORTED] = "NOT SUPPORTED", 36}; 37 38const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = { 39 [DEV_ST_TRANSITION_PBL] = "PBL", 40 [DEV_ST_TRANSITION_READY] = "READY", 41 [DEV_ST_TRANSITION_SBL] = "SBL", 42 [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION MODE", 43 [DEV_ST_TRANSITION_FP] = "FLASH PROGRAMMER", 44 [DEV_ST_TRANSITION_SYS_ERR] = "SYS ERROR", 45 [DEV_ST_TRANSITION_DISABLE] = "DISABLE", 46}; 47 48const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = { 49 [MHI_CH_STATE_TYPE_RESET] = "RESET", 50 [MHI_CH_STATE_TYPE_STOP] = "STOP", 51 [MHI_CH_STATE_TYPE_START] = "START", 52}; 53 54static const char * const mhi_pm_state_str[] = { 55 [MHI_PM_STATE_DISABLE] = "DISABLE", 56 [MHI_PM_STATE_POR] = "POWER ON RESET", 57 [MHI_PM_STATE_M0] = "M0", 58 [MHI_PM_STATE_M2] = "M2", 59 [MHI_PM_STATE_M3_ENTER] = "M?->M3", 60 [MHI_PM_STATE_M3] = "M3", 61 [MHI_PM_STATE_M3_EXIT] = "M3->M0", 62 [MHI_PM_STATE_FW_DL_ERR] = "Firmware Download Error", 63 [MHI_PM_STATE_SYS_ERR_DETECT] = "SYS ERROR Detect", 64 [MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS ERROR Process", 65 [MHI_PM_STATE_SHUTDOWN_PROCESS] = "SHUTDOWN Process", 66 [MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "Linkdown or Error Fatal Detect", 67}; 68 69const char *to_mhi_pm_state_str(u32 state) 70{ 71 int index; 72 73 if (state) 74 index = __fls(state); 75 76 if (!state || index >= ARRAY_SIZE(mhi_pm_state_str)) 77 return "Invalid State"; 78 79 return mhi_pm_state_str[index]; 80} 81 82static ssize_t serial_number_show(struct device *dev, 83 struct device_attribute *attr, 84 char *buf) 85{ 86 struct mhi_device *mhi_dev = to_mhi_device(dev); 87 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 88 89 return sysfs_emit(buf, "Serial Number: %u\n", 90 mhi_cntrl->serial_number); 91} 92static DEVICE_ATTR_RO(serial_number); 93 94static ssize_t oem_pk_hash_show(struct device *dev, 95 struct device_attribute *attr, 96 char *buf) 97{ 98 struct mhi_device *mhi_dev = to_mhi_device(dev); 99 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 100 int i, cnt = 0; 101 102 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++) 103 cnt += sysfs_emit_at(buf, cnt, "OEMPKHASH[%d]: 0x%x\n", 104 i, mhi_cntrl->oem_pk_hash[i]); 105 106 return cnt; 107} 108static DEVICE_ATTR_RO(oem_pk_hash); 109 110static ssize_t soc_reset_store(struct device *dev, 111 struct device_attribute *attr, 112 const char *buf, 113 size_t count) 114{ 115 struct mhi_device *mhi_dev = to_mhi_device(dev); 116 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 117 118 mhi_soc_reset(mhi_cntrl); 119 return count; 120} 121static DEVICE_ATTR_WO(soc_reset); 122 123static struct attribute *mhi_dev_attrs[] = { 124 &dev_attr_serial_number.attr, 125 &dev_attr_oem_pk_hash.attr, 126 &dev_attr_soc_reset.attr, 127 NULL, 128}; 129ATTRIBUTE_GROUPS(mhi_dev); 130 131/* MHI protocol requires the transfer ring to be aligned with ring length */ 132static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl, 133 struct mhi_ring *ring, 134 u64 len) 135{ 136 ring->alloc_size = len + (len - 1); 137 ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 138 &ring->dma_handle, GFP_KERNEL); 139 if (!ring->pre_aligned) 140 return -ENOMEM; 141 142 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1); 143 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle); 144 145 return 0; 146} 147 148void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl) 149{ 150 int i; 151 struct mhi_event *mhi_event = mhi_cntrl->mhi_event; 152 153 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 154 if (mhi_event->offload_ev) 155 continue; 156 157 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); 158 } 159 160 free_irq(mhi_cntrl->irq[0], mhi_cntrl); 161} 162 163int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl) 164{ 165 struct mhi_event *mhi_event = mhi_cntrl->mhi_event; 166 struct device *dev = &mhi_cntrl->mhi_dev->dev; 167 unsigned long irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND; 168 int i, ret; 169 170 /* if controller driver has set irq_flags, use it */ 171 if (mhi_cntrl->irq_flags) 172 irq_flags = mhi_cntrl->irq_flags; 173 174 /* Setup BHI_INTVEC IRQ */ 175 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler, 176 mhi_intvec_threaded_handler, 177 irq_flags, 178 "bhi", mhi_cntrl); 179 if (ret) 180 return ret; 181 /* 182 * IRQs should be enabled during mhi_async_power_up(), so disable them explicitly here. 183 * Due to the use of IRQF_SHARED flag as default while requesting IRQs, we assume that 184 * IRQ_NOAUTOEN is not applicable. 185 */ 186 disable_irq(mhi_cntrl->irq[0]); 187 188 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 189 if (mhi_event->offload_ev) 190 continue; 191 192 if (mhi_event->irq >= mhi_cntrl->nr_irqs) { 193 dev_err(dev, "irq %d not available for event ring\n", 194 mhi_event->irq); 195 ret = -EINVAL; 196 goto error_request; 197 } 198 199 ret = request_irq(mhi_cntrl->irq[mhi_event->irq], 200 mhi_irq_handler, 201 irq_flags, 202 "mhi", mhi_event); 203 if (ret) { 204 dev_err(dev, "Error requesting irq:%d for ev:%d\n", 205 mhi_cntrl->irq[mhi_event->irq], i); 206 goto error_request; 207 } 208 209 disable_irq(mhi_cntrl->irq[mhi_event->irq]); 210 } 211 212 return 0; 213 214error_request: 215 for (--i, --mhi_event; i >= 0; i--, mhi_event--) { 216 if (mhi_event->offload_ev) 217 continue; 218 219 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); 220 } 221 free_irq(mhi_cntrl->irq[0], mhi_cntrl); 222 223 return ret; 224} 225 226void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl) 227{ 228 int i; 229 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt; 230 struct mhi_cmd *mhi_cmd; 231 struct mhi_event *mhi_event; 232 struct mhi_ring *ring; 233 234 mhi_cmd = mhi_cntrl->mhi_cmd; 235 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) { 236 ring = &mhi_cmd->ring; 237 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 238 ring->pre_aligned, ring->dma_handle); 239 ring->base = NULL; 240 ring->iommu_base = 0; 241 } 242 243 dma_free_coherent(mhi_cntrl->cntrl_dev, 244 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS, 245 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr); 246 247 mhi_event = mhi_cntrl->mhi_event; 248 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 249 if (mhi_event->offload_ev) 250 continue; 251 252 ring = &mhi_event->ring; 253 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 254 ring->pre_aligned, ring->dma_handle); 255 ring->base = NULL; 256 ring->iommu_base = 0; 257 } 258 259 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) * 260 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt, 261 mhi_ctxt->er_ctxt_addr); 262 263 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) * 264 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt, 265 mhi_ctxt->chan_ctxt_addr); 266 267 kfree(mhi_ctxt); 268 mhi_cntrl->mhi_ctxt = NULL; 269} 270 271int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) 272{ 273 struct mhi_ctxt *mhi_ctxt; 274 struct mhi_chan_ctxt *chan_ctxt; 275 struct mhi_event_ctxt *er_ctxt; 276 struct mhi_cmd_ctxt *cmd_ctxt; 277 struct mhi_chan *mhi_chan; 278 struct mhi_event *mhi_event; 279 struct mhi_cmd *mhi_cmd; 280 u32 tmp; 281 int ret = -ENOMEM, i; 282 283 atomic_set(&mhi_cntrl->dev_wake, 0); 284 atomic_set(&mhi_cntrl->pending_pkts, 0); 285 286 mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), GFP_KERNEL); 287 if (!mhi_ctxt) 288 return -ENOMEM; 289 290 /* Setup channel ctxt */ 291 mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev, 292 sizeof(*mhi_ctxt->chan_ctxt) * 293 mhi_cntrl->max_chan, 294 &mhi_ctxt->chan_ctxt_addr, 295 GFP_KERNEL); 296 if (!mhi_ctxt->chan_ctxt) 297 goto error_alloc_chan_ctxt; 298 299 mhi_chan = mhi_cntrl->mhi_chan; 300 chan_ctxt = mhi_ctxt->chan_ctxt; 301 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) { 302 /* Skip if it is an offload channel */ 303 if (mhi_chan->offload_ch) 304 continue; 305 306 tmp = le32_to_cpu(chan_ctxt->chcfg); 307 tmp &= ~CHAN_CTX_CHSTATE_MASK; 308 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED); 309 tmp &= ~CHAN_CTX_BRSTMODE_MASK; 310 tmp |= FIELD_PREP(CHAN_CTX_BRSTMODE_MASK, mhi_chan->db_cfg.brstmode); 311 tmp &= ~CHAN_CTX_POLLCFG_MASK; 312 tmp |= FIELD_PREP(CHAN_CTX_POLLCFG_MASK, mhi_chan->db_cfg.pollcfg); 313 chan_ctxt->chcfg = cpu_to_le32(tmp); 314 315 chan_ctxt->chtype = cpu_to_le32(mhi_chan->type); 316 chan_ctxt->erindex = cpu_to_le32(mhi_chan->er_index); 317 318 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 319 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp; 320 } 321 322 /* Setup event context */ 323 mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev, 324 sizeof(*mhi_ctxt->er_ctxt) * 325 mhi_cntrl->total_ev_rings, 326 &mhi_ctxt->er_ctxt_addr, 327 GFP_KERNEL); 328 if (!mhi_ctxt->er_ctxt) 329 goto error_alloc_er_ctxt; 330 331 er_ctxt = mhi_ctxt->er_ctxt; 332 mhi_event = mhi_cntrl->mhi_event; 333 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, 334 mhi_event++) { 335 struct mhi_ring *ring = &mhi_event->ring; 336 337 /* Skip if it is an offload event */ 338 if (mhi_event->offload_ev) 339 continue; 340 341 tmp = le32_to_cpu(er_ctxt->intmod); 342 tmp &= ~EV_CTX_INTMODC_MASK; 343 tmp &= ~EV_CTX_INTMODT_MASK; 344 tmp |= FIELD_PREP(EV_CTX_INTMODT_MASK, mhi_event->intmod); 345 er_ctxt->intmod = cpu_to_le32(tmp); 346 347 er_ctxt->ertype = cpu_to_le32(MHI_ER_TYPE_VALID); 348 er_ctxt->msivec = cpu_to_le32(mhi_event->irq); 349 mhi_event->db_cfg.db_mode = true; 350 351 ring->el_size = sizeof(struct mhi_ring_element); 352 ring->len = ring->el_size * ring->elements; 353 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len); 354 if (ret) 355 goto error_alloc_er; 356 357 /* 358 * If the read pointer equals to the write pointer, then the 359 * ring is empty 360 */ 361 ring->rp = ring->wp = ring->base; 362 er_ctxt->rbase = cpu_to_le64(ring->iommu_base); 363 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase; 364 er_ctxt->rlen = cpu_to_le64(ring->len); 365 ring->ctxt_wp = &er_ctxt->wp; 366 } 367 368 /* Setup cmd context */ 369 ret = -ENOMEM; 370 mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev, 371 sizeof(*mhi_ctxt->cmd_ctxt) * 372 NR_OF_CMD_RINGS, 373 &mhi_ctxt->cmd_ctxt_addr, 374 GFP_KERNEL); 375 if (!mhi_ctxt->cmd_ctxt) 376 goto error_alloc_er; 377 378 mhi_cmd = mhi_cntrl->mhi_cmd; 379 cmd_ctxt = mhi_ctxt->cmd_ctxt; 380 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) { 381 struct mhi_ring *ring = &mhi_cmd->ring; 382 383 ring->el_size = sizeof(struct mhi_ring_element); 384 ring->elements = CMD_EL_PER_RING; 385 ring->len = ring->el_size * ring->elements; 386 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len); 387 if (ret) 388 goto error_alloc_cmd; 389 390 ring->rp = ring->wp = ring->base; 391 cmd_ctxt->rbase = cpu_to_le64(ring->iommu_base); 392 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase; 393 cmd_ctxt->rlen = cpu_to_le64(ring->len); 394 ring->ctxt_wp = &cmd_ctxt->wp; 395 } 396 397 mhi_cntrl->mhi_ctxt = mhi_ctxt; 398 399 return 0; 400 401error_alloc_cmd: 402 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) { 403 struct mhi_ring *ring = &mhi_cmd->ring; 404 405 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 406 ring->pre_aligned, ring->dma_handle); 407 } 408 dma_free_coherent(mhi_cntrl->cntrl_dev, 409 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS, 410 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr); 411 i = mhi_cntrl->total_ev_rings; 412 mhi_event = mhi_cntrl->mhi_event + i; 413 414error_alloc_er: 415 for (--i, --mhi_event; i >= 0; i--, mhi_event--) { 416 struct mhi_ring *ring = &mhi_event->ring; 417 418 if (mhi_event->offload_ev) 419 continue; 420 421 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 422 ring->pre_aligned, ring->dma_handle); 423 } 424 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) * 425 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt, 426 mhi_ctxt->er_ctxt_addr); 427 428error_alloc_er_ctxt: 429 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) * 430 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt, 431 mhi_ctxt->chan_ctxt_addr); 432 433error_alloc_chan_ctxt: 434 kfree(mhi_ctxt); 435 436 return ret; 437} 438 439int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 440{ 441 u32 val; 442 int i, ret; 443 struct mhi_chan *mhi_chan; 444 struct mhi_event *mhi_event; 445 void __iomem *base = mhi_cntrl->regs; 446 struct device *dev = &mhi_cntrl->mhi_dev->dev; 447 struct { 448 u32 offset; 449 u32 val; 450 } reg_info[] = { 451 { 452 CCABAP_HIGHER, 453 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr), 454 }, 455 { 456 CCABAP_LOWER, 457 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr), 458 }, 459 { 460 ECABAP_HIGHER, 461 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr), 462 }, 463 { 464 ECABAP_LOWER, 465 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr), 466 }, 467 { 468 CRCBAP_HIGHER, 469 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr), 470 }, 471 { 472 CRCBAP_LOWER, 473 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr), 474 }, 475 { 476 MHICTRLBASE_HIGHER, 477 upper_32_bits(mhi_cntrl->iova_start), 478 }, 479 { 480 MHICTRLBASE_LOWER, 481 lower_32_bits(mhi_cntrl->iova_start), 482 }, 483 { 484 MHIDATABASE_HIGHER, 485 upper_32_bits(mhi_cntrl->iova_start), 486 }, 487 { 488 MHIDATABASE_LOWER, 489 lower_32_bits(mhi_cntrl->iova_start), 490 }, 491 { 492 MHICTRLLIMIT_HIGHER, 493 upper_32_bits(mhi_cntrl->iova_stop), 494 }, 495 { 496 MHICTRLLIMIT_LOWER, 497 lower_32_bits(mhi_cntrl->iova_stop), 498 }, 499 { 500 MHIDATALIMIT_HIGHER, 501 upper_32_bits(mhi_cntrl->iova_stop), 502 }, 503 { 504 MHIDATALIMIT_LOWER, 505 lower_32_bits(mhi_cntrl->iova_stop), 506 }, 507 {0, 0} 508 }; 509 510 dev_dbg(dev, "Initializing MHI registers\n"); 511 512 /* Read channel db offset */ 513 ret = mhi_read_reg(mhi_cntrl, base, CHDBOFF, &val); 514 if (ret) { 515 dev_err(dev, "Unable to read CHDBOFF register\n"); 516 return -EIO; 517 } 518 519 if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) { 520 dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n", 521 val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)); 522 return -ERANGE; 523 } 524 525 /* Setup wake db */ 526 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); 527 mhi_cntrl->wake_set = false; 528 529 /* Setup channel db address for each channel in tre_ring */ 530 mhi_chan = mhi_cntrl->mhi_chan; 531 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++) 532 mhi_chan->tre_ring.db_addr = base + val; 533 534 /* Read event ring db offset */ 535 ret = mhi_read_reg(mhi_cntrl, base, ERDBOFF, &val); 536 if (ret) { 537 dev_err(dev, "Unable to read ERDBOFF register\n"); 538 return -EIO; 539 } 540 541 if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) { 542 dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n", 543 val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)); 544 return -ERANGE; 545 } 546 547 /* Setup event db address for each ev_ring */ 548 mhi_event = mhi_cntrl->mhi_event; 549 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) { 550 if (mhi_event->offload_ev) 551 continue; 552 553 mhi_event->ring.db_addr = base + val; 554 } 555 556 /* Setup DB register for primary CMD rings */ 557 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER; 558 559 /* Write to MMIO registers */ 560 for (i = 0; reg_info[i].offset; i++) 561 mhi_write_reg(mhi_cntrl, base, reg_info[i].offset, 562 reg_info[i].val); 563 564 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK, 565 mhi_cntrl->total_ev_rings); 566 if (ret) { 567 dev_err(dev, "Unable to write MHICFG register\n"); 568 return ret; 569 } 570 571 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK, 572 mhi_cntrl->hw_ev_rings); 573 if (ret) { 574 dev_err(dev, "Unable to write MHICFG register\n"); 575 return ret; 576 } 577 578 return 0; 579} 580 581void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, 582 struct mhi_chan *mhi_chan) 583{ 584 struct mhi_ring *buf_ring; 585 struct mhi_ring *tre_ring; 586 struct mhi_chan_ctxt *chan_ctxt; 587 u32 tmp; 588 589 buf_ring = &mhi_chan->buf_ring; 590 tre_ring = &mhi_chan->tre_ring; 591 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan]; 592 593 if (!chan_ctxt->rbase) /* Already uninitialized */ 594 return; 595 596 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size, 597 tre_ring->pre_aligned, tre_ring->dma_handle); 598 vfree(buf_ring->base); 599 600 buf_ring->base = tre_ring->base = NULL; 601 tre_ring->ctxt_wp = NULL; 602 chan_ctxt->rbase = 0; 603 chan_ctxt->rlen = 0; 604 chan_ctxt->rp = 0; 605 chan_ctxt->wp = 0; 606 607 tmp = le32_to_cpu(chan_ctxt->chcfg); 608 tmp &= ~CHAN_CTX_CHSTATE_MASK; 609 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED); 610 chan_ctxt->chcfg = cpu_to_le32(tmp); 611 612 /* Update to all cores */ 613 smp_wmb(); 614} 615 616int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, 617 struct mhi_chan *mhi_chan) 618{ 619 struct mhi_ring *buf_ring; 620 struct mhi_ring *tre_ring; 621 struct mhi_chan_ctxt *chan_ctxt; 622 u32 tmp; 623 int ret; 624 625 buf_ring = &mhi_chan->buf_ring; 626 tre_ring = &mhi_chan->tre_ring; 627 tre_ring->el_size = sizeof(struct mhi_ring_element); 628 tre_ring->len = tre_ring->el_size * tre_ring->elements; 629 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan]; 630 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len); 631 if (ret) 632 return -ENOMEM; 633 634 buf_ring->el_size = sizeof(struct mhi_buf_info); 635 buf_ring->len = buf_ring->el_size * buf_ring->elements; 636 buf_ring->base = vzalloc(buf_ring->len); 637 638 if (!buf_ring->base) { 639 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size, 640 tre_ring->pre_aligned, tre_ring->dma_handle); 641 return -ENOMEM; 642 } 643 644 tmp = le32_to_cpu(chan_ctxt->chcfg); 645 tmp &= ~CHAN_CTX_CHSTATE_MASK; 646 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_ENABLED); 647 chan_ctxt->chcfg = cpu_to_le32(tmp); 648 649 chan_ctxt->rbase = cpu_to_le64(tre_ring->iommu_base); 650 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase; 651 chan_ctxt->rlen = cpu_to_le64(tre_ring->len); 652 tre_ring->ctxt_wp = &chan_ctxt->wp; 653 654 tre_ring->rp = tre_ring->wp = tre_ring->base; 655 buf_ring->rp = buf_ring->wp = buf_ring->base; 656 mhi_chan->db_cfg.db_mode = 1; 657 658 /* Update to all cores */ 659 smp_wmb(); 660 661 return 0; 662} 663 664static int parse_ev_cfg(struct mhi_controller *mhi_cntrl, 665 const struct mhi_controller_config *config) 666{ 667 struct mhi_event *mhi_event; 668 const struct mhi_event_config *event_cfg; 669 struct device *dev = mhi_cntrl->cntrl_dev; 670 int i, num; 671 672 num = config->num_events; 673 mhi_cntrl->total_ev_rings = num; 674 mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event), 675 GFP_KERNEL); 676 if (!mhi_cntrl->mhi_event) 677 return -ENOMEM; 678 679 /* Populate event ring */ 680 mhi_event = mhi_cntrl->mhi_event; 681 for (i = 0; i < num; i++) { 682 event_cfg = &config->event_cfg[i]; 683 684 mhi_event->er_index = i; 685 mhi_event->ring.elements = event_cfg->num_elements; 686 mhi_event->intmod = event_cfg->irq_moderation_ms; 687 mhi_event->irq = event_cfg->irq; 688 689 if (event_cfg->channel != U32_MAX) { 690 /* This event ring has a dedicated channel */ 691 mhi_event->chan = event_cfg->channel; 692 if (mhi_event->chan >= mhi_cntrl->max_chan) { 693 dev_err(dev, 694 "Event Ring channel not available\n"); 695 goto error_ev_cfg; 696 } 697 698 mhi_event->mhi_chan = 699 &mhi_cntrl->mhi_chan[mhi_event->chan]; 700 } 701 702 /* Priority is fixed to 1 for now */ 703 mhi_event->priority = 1; 704 705 mhi_event->db_cfg.brstmode = event_cfg->mode; 706 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode)) 707 goto error_ev_cfg; 708 709 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE) 710 mhi_event->db_cfg.process_db = mhi_db_brstmode; 711 else 712 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable; 713 714 mhi_event->data_type = event_cfg->data_type; 715 716 switch (mhi_event->data_type) { 717 case MHI_ER_DATA: 718 mhi_event->process_event = mhi_process_data_event_ring; 719 break; 720 case MHI_ER_CTRL: 721 mhi_event->process_event = mhi_process_ctrl_ev_ring; 722 break; 723 default: 724 dev_err(dev, "Event Ring type not supported\n"); 725 goto error_ev_cfg; 726 } 727 728 mhi_event->hw_ring = event_cfg->hardware_event; 729 if (mhi_event->hw_ring) 730 mhi_cntrl->hw_ev_rings++; 731 else 732 mhi_cntrl->sw_ev_rings++; 733 734 mhi_event->cl_manage = event_cfg->client_managed; 735 mhi_event->offload_ev = event_cfg->offload_channel; 736 mhi_event++; 737 } 738 739 return 0; 740 741error_ev_cfg: 742 743 kfree(mhi_cntrl->mhi_event); 744 return -EINVAL; 745} 746 747static int parse_ch_cfg(struct mhi_controller *mhi_cntrl, 748 const struct mhi_controller_config *config) 749{ 750 const struct mhi_channel_config *ch_cfg; 751 struct device *dev = mhi_cntrl->cntrl_dev; 752 int i; 753 u32 chan; 754 755 mhi_cntrl->max_chan = config->max_channels; 756 757 /* 758 * The allocation of MHI channels can exceed 32KB in some scenarios, 759 * so to avoid any memory possible allocation failures, vzalloc is 760 * used here 761 */ 762 mhi_cntrl->mhi_chan = vcalloc(mhi_cntrl->max_chan, 763 sizeof(*mhi_cntrl->mhi_chan)); 764 if (!mhi_cntrl->mhi_chan) 765 return -ENOMEM; 766 767 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans); 768 769 /* Populate channel configurations */ 770 for (i = 0; i < config->num_channels; i++) { 771 struct mhi_chan *mhi_chan; 772 773 ch_cfg = &config->ch_cfg[i]; 774 775 chan = ch_cfg->num; 776 if (chan >= mhi_cntrl->max_chan) { 777 dev_err(dev, "Channel %d not available\n", chan); 778 goto error_chan_cfg; 779 } 780 781 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 782 mhi_chan->name = ch_cfg->name; 783 mhi_chan->chan = chan; 784 785 mhi_chan->tre_ring.elements = ch_cfg->num_elements; 786 if (!mhi_chan->tre_ring.elements) 787 goto error_chan_cfg; 788 789 /* 790 * For some channels, local ring length should be bigger than 791 * the transfer ring length due to internal logical channels 792 * in device. So host can queue much more buffers than transfer 793 * ring length. Example, RSC channels should have a larger local 794 * channel length than transfer ring length. 795 */ 796 mhi_chan->buf_ring.elements = ch_cfg->local_elements; 797 if (!mhi_chan->buf_ring.elements) 798 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements; 799 mhi_chan->er_index = ch_cfg->event_ring; 800 mhi_chan->dir = ch_cfg->dir; 801 802 /* 803 * For most channels, chtype is identical to channel directions. 804 * So, if it is not defined then assign channel direction to 805 * chtype 806 */ 807 mhi_chan->type = ch_cfg->type; 808 if (!mhi_chan->type) 809 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir; 810 811 mhi_chan->ee_mask = ch_cfg->ee_mask; 812 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg; 813 mhi_chan->lpm_notify = ch_cfg->lpm_notify; 814 mhi_chan->offload_ch = ch_cfg->offload_channel; 815 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch; 816 mhi_chan->pre_alloc = ch_cfg->auto_queue; 817 mhi_chan->wake_capable = ch_cfg->wake_capable; 818 819 /* 820 * If MHI host allocates buffers, then the channel direction 821 * should be DMA_FROM_DEVICE 822 */ 823 if (mhi_chan->pre_alloc && mhi_chan->dir != DMA_FROM_DEVICE) { 824 dev_err(dev, "Invalid channel configuration\n"); 825 goto error_chan_cfg; 826 } 827 828 /* 829 * Bi-directional and direction less channel must be an 830 * offload channel 831 */ 832 if ((mhi_chan->dir == DMA_BIDIRECTIONAL || 833 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) { 834 dev_err(dev, "Invalid channel configuration\n"); 835 goto error_chan_cfg; 836 } 837 838 if (!mhi_chan->offload_ch) { 839 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell; 840 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) { 841 dev_err(dev, "Invalid Door bell mode\n"); 842 goto error_chan_cfg; 843 } 844 } 845 846 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE) 847 mhi_chan->db_cfg.process_db = mhi_db_brstmode; 848 else 849 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable; 850 851 mhi_chan->configured = true; 852 853 if (mhi_chan->lpm_notify) 854 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans); 855 } 856 857 return 0; 858 859error_chan_cfg: 860 vfree(mhi_cntrl->mhi_chan); 861 862 return -EINVAL; 863} 864 865static int parse_config(struct mhi_controller *mhi_cntrl, 866 const struct mhi_controller_config *config) 867{ 868 int ret; 869 870 /* Parse MHI channel configuration */ 871 ret = parse_ch_cfg(mhi_cntrl, config); 872 if (ret) 873 return ret; 874 875 /* Parse MHI event configuration */ 876 ret = parse_ev_cfg(mhi_cntrl, config); 877 if (ret) 878 goto error_ev_cfg; 879 880 mhi_cntrl->timeout_ms = config->timeout_ms; 881 if (!mhi_cntrl->timeout_ms) 882 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS; 883 884 mhi_cntrl->bounce_buf = config->use_bounce_buf; 885 mhi_cntrl->buffer_len = config->buf_len; 886 if (!mhi_cntrl->buffer_len) 887 mhi_cntrl->buffer_len = MHI_MAX_MTU; 888 889 /* By default, host is allowed to ring DB in both M0 and M2 states */ 890 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2; 891 if (config->m2_no_db) 892 mhi_cntrl->db_access &= ~MHI_PM_M2; 893 894 return 0; 895 896error_ev_cfg: 897 vfree(mhi_cntrl->mhi_chan); 898 899 return ret; 900} 901 902int mhi_register_controller(struct mhi_controller *mhi_cntrl, 903 const struct mhi_controller_config *config) 904{ 905 struct mhi_event *mhi_event; 906 struct mhi_chan *mhi_chan; 907 struct mhi_cmd *mhi_cmd; 908 struct mhi_device *mhi_dev; 909 u32 soc_info; 910 int ret, i; 911 912 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs || 913 !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put || 914 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg || 915 !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || 916 !mhi_cntrl->irq || !mhi_cntrl->reg_len) 917 return -EINVAL; 918 919 ret = parse_config(mhi_cntrl, config); 920 if (ret) 921 return -EINVAL; 922 923 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS, 924 sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL); 925 if (!mhi_cntrl->mhi_cmd) { 926 ret = -ENOMEM; 927 goto err_free_event; 928 } 929 930 INIT_LIST_HEAD(&mhi_cntrl->transition_list); 931 mutex_init(&mhi_cntrl->pm_mutex); 932 rwlock_init(&mhi_cntrl->pm_lock); 933 spin_lock_init(&mhi_cntrl->transition_lock); 934 spin_lock_init(&mhi_cntrl->wlock); 935 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker); 936 init_waitqueue_head(&mhi_cntrl->state_event); 937 938 mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI); 939 if (!mhi_cntrl->hiprio_wq) { 940 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n"); 941 ret = -ENOMEM; 942 goto err_free_cmd; 943 } 944 945 mhi_cmd = mhi_cntrl->mhi_cmd; 946 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) 947 spin_lock_init(&mhi_cmd->lock); 948 949 mhi_event = mhi_cntrl->mhi_event; 950 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 951 /* Skip for offload events */ 952 if (mhi_event->offload_ev) 953 continue; 954 955 mhi_event->mhi_cntrl = mhi_cntrl; 956 spin_lock_init(&mhi_event->lock); 957 if (mhi_event->data_type == MHI_ER_CTRL) 958 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task, 959 (ulong)mhi_event); 960 else 961 tasklet_init(&mhi_event->task, mhi_ev_task, 962 (ulong)mhi_event); 963 } 964 965 mhi_chan = mhi_cntrl->mhi_chan; 966 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 967 mutex_init(&mhi_chan->mutex); 968 init_completion(&mhi_chan->completion); 969 rwlock_init(&mhi_chan->lock); 970 971 /* used in setting bei field of TRE */ 972 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; 973 mhi_chan->intmod = mhi_event->intmod; 974 } 975 976 if (mhi_cntrl->bounce_buf) { 977 mhi_cntrl->map_single = mhi_map_single_use_bb; 978 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb; 979 } else { 980 mhi_cntrl->map_single = mhi_map_single_no_bb; 981 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb; 982 } 983 984 /* Read the MHI device info */ 985 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, 986 SOC_HW_VERSION_OFFS, &soc_info); 987 if (ret) 988 goto err_destroy_wq; 989 990 mhi_cntrl->family_number = FIELD_GET(SOC_HW_VERSION_FAM_NUM_BMSK, soc_info); 991 mhi_cntrl->device_number = FIELD_GET(SOC_HW_VERSION_DEV_NUM_BMSK, soc_info); 992 mhi_cntrl->major_version = FIELD_GET(SOC_HW_VERSION_MAJOR_VER_BMSK, soc_info); 993 mhi_cntrl->minor_version = FIELD_GET(SOC_HW_VERSION_MINOR_VER_BMSK, soc_info); 994 995 mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL); 996 if (mhi_cntrl->index < 0) { 997 ret = mhi_cntrl->index; 998 goto err_destroy_wq; 999 } 1000 1001 ret = mhi_init_irq_setup(mhi_cntrl); 1002 if (ret) 1003 goto err_ida_free; 1004 1005 /* Register controller with MHI bus */ 1006 mhi_dev = mhi_alloc_device(mhi_cntrl); 1007 if (IS_ERR(mhi_dev)) { 1008 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n"); 1009 ret = PTR_ERR(mhi_dev); 1010 goto error_setup_irq; 1011 } 1012 1013 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER; 1014 mhi_dev->mhi_cntrl = mhi_cntrl; 1015 dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index); 1016 mhi_dev->name = dev_name(&mhi_dev->dev); 1017 1018 /* Init wakeup source */ 1019 device_init_wakeup(&mhi_dev->dev, true); 1020 1021 ret = device_add(&mhi_dev->dev); 1022 if (ret) 1023 goto err_release_dev; 1024 1025 mhi_cntrl->mhi_dev = mhi_dev; 1026 1027 mhi_create_debugfs(mhi_cntrl); 1028 1029 return 0; 1030 1031err_release_dev: 1032 put_device(&mhi_dev->dev); 1033error_setup_irq: 1034 mhi_deinit_free_irq(mhi_cntrl); 1035err_ida_free: 1036 ida_free(&mhi_controller_ida, mhi_cntrl->index); 1037err_destroy_wq: 1038 destroy_workqueue(mhi_cntrl->hiprio_wq); 1039err_free_cmd: 1040 kfree(mhi_cntrl->mhi_cmd); 1041err_free_event: 1042 kfree(mhi_cntrl->mhi_event); 1043 vfree(mhi_cntrl->mhi_chan); 1044 1045 return ret; 1046} 1047EXPORT_SYMBOL_GPL(mhi_register_controller); 1048 1049void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) 1050{ 1051 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev; 1052 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan; 1053 unsigned int i; 1054 1055 mhi_deinit_free_irq(mhi_cntrl); 1056 mhi_destroy_debugfs(mhi_cntrl); 1057 1058 destroy_workqueue(mhi_cntrl->hiprio_wq); 1059 kfree(mhi_cntrl->mhi_cmd); 1060 kfree(mhi_cntrl->mhi_event); 1061 1062 /* Drop the references to MHI devices created for channels */ 1063 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 1064 if (!mhi_chan->mhi_dev) 1065 continue; 1066 1067 put_device(&mhi_chan->mhi_dev->dev); 1068 } 1069 vfree(mhi_cntrl->mhi_chan); 1070 1071 device_del(&mhi_dev->dev); 1072 put_device(&mhi_dev->dev); 1073 1074 ida_free(&mhi_controller_ida, mhi_cntrl->index); 1075} 1076EXPORT_SYMBOL_GPL(mhi_unregister_controller); 1077 1078struct mhi_controller *mhi_alloc_controller(void) 1079{ 1080 struct mhi_controller *mhi_cntrl; 1081 1082 mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL); 1083 1084 return mhi_cntrl; 1085} 1086EXPORT_SYMBOL_GPL(mhi_alloc_controller); 1087 1088void mhi_free_controller(struct mhi_controller *mhi_cntrl) 1089{ 1090 kfree(mhi_cntrl); 1091} 1092EXPORT_SYMBOL_GPL(mhi_free_controller); 1093 1094int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) 1095{ 1096 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1097 u32 bhi_off, bhie_off; 1098 int ret; 1099 1100 mutex_lock(&mhi_cntrl->pm_mutex); 1101 1102 ret = mhi_init_dev_ctxt(mhi_cntrl); 1103 if (ret) 1104 goto error_dev_ctxt; 1105 1106 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off); 1107 if (ret) { 1108 dev_err(dev, "Error getting BHI offset\n"); 1109 goto error_reg_offset; 1110 } 1111 1112 if (bhi_off >= mhi_cntrl->reg_len) { 1113 dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n", 1114 bhi_off, mhi_cntrl->reg_len); 1115 ret = -ERANGE; 1116 goto error_reg_offset; 1117 } 1118 mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off; 1119 1120 if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) { 1121 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, 1122 &bhie_off); 1123 if (ret) { 1124 dev_err(dev, "Error getting BHIE offset\n"); 1125 goto error_reg_offset; 1126 } 1127 1128 if (bhie_off >= mhi_cntrl->reg_len) { 1129 dev_err(dev, 1130 "BHIe offset: 0x%x is out of range: 0x%zx\n", 1131 bhie_off, mhi_cntrl->reg_len); 1132 ret = -ERANGE; 1133 goto error_reg_offset; 1134 } 1135 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off; 1136 } 1137 1138 if (mhi_cntrl->rddm_size) { 1139 /* 1140 * This controller supports RDDM, so we need to manually clear 1141 * BHIE RX registers since POR values are undefined. 1142 */ 1143 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS, 1144 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS + 1145 4); 1146 /* 1147 * Allocate RDDM table for debugging purpose if specified 1148 */ 1149 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, 1150 mhi_cntrl->rddm_size); 1151 if (mhi_cntrl->rddm_image) { 1152 ret = mhi_rddm_prepare(mhi_cntrl, 1153 mhi_cntrl->rddm_image); 1154 if (ret) { 1155 mhi_free_bhie_table(mhi_cntrl, 1156 mhi_cntrl->rddm_image); 1157 goto error_reg_offset; 1158 } 1159 } 1160 } 1161 1162 mutex_unlock(&mhi_cntrl->pm_mutex); 1163 1164 return 0; 1165 1166error_reg_offset: 1167 mhi_deinit_dev_ctxt(mhi_cntrl); 1168 1169error_dev_ctxt: 1170 mutex_unlock(&mhi_cntrl->pm_mutex); 1171 1172 return ret; 1173} 1174EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up); 1175 1176void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl) 1177{ 1178 if (mhi_cntrl->fbc_image) { 1179 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); 1180 mhi_cntrl->fbc_image = NULL; 1181 } 1182 1183 if (mhi_cntrl->rddm_image) { 1184 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); 1185 mhi_cntrl->rddm_image = NULL; 1186 } 1187 1188 mhi_cntrl->bhi = NULL; 1189 mhi_cntrl->bhie = NULL; 1190 1191 mhi_deinit_dev_ctxt(mhi_cntrl); 1192} 1193EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down); 1194 1195static void mhi_release_device(struct device *dev) 1196{ 1197 struct mhi_device *mhi_dev = to_mhi_device(dev); 1198 1199 /* 1200 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI 1201 * devices for the channels will only get created if the mhi_dev 1202 * associated with it is NULL. This scenario will happen during the 1203 * controller suspend and resume. 1204 */ 1205 if (mhi_dev->ul_chan) 1206 mhi_dev->ul_chan->mhi_dev = NULL; 1207 1208 if (mhi_dev->dl_chan) 1209 mhi_dev->dl_chan->mhi_dev = NULL; 1210 1211 kfree(mhi_dev); 1212} 1213 1214struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl) 1215{ 1216 struct mhi_device *mhi_dev; 1217 struct device *dev; 1218 1219 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL); 1220 if (!mhi_dev) 1221 return ERR_PTR(-ENOMEM); 1222 1223 dev = &mhi_dev->dev; 1224 device_initialize(dev); 1225 dev->bus = &mhi_bus_type; 1226 dev->release = mhi_release_device; 1227 1228 if (mhi_cntrl->mhi_dev) { 1229 /* for MHI client devices, parent is the MHI controller device */ 1230 dev->parent = &mhi_cntrl->mhi_dev->dev; 1231 } else { 1232 /* for MHI controller device, parent is the bus device (e.g. pci device) */ 1233 dev->parent = mhi_cntrl->cntrl_dev; 1234 } 1235 1236 mhi_dev->mhi_cntrl = mhi_cntrl; 1237 mhi_dev->dev_wake = 0; 1238 1239 return mhi_dev; 1240} 1241 1242static int mhi_driver_probe(struct device *dev) 1243{ 1244 struct mhi_device *mhi_dev = to_mhi_device(dev); 1245 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1246 struct device_driver *drv = dev->driver; 1247 struct mhi_driver *mhi_drv = to_mhi_driver(drv); 1248 struct mhi_event *mhi_event; 1249 struct mhi_chan *ul_chan = mhi_dev->ul_chan; 1250 struct mhi_chan *dl_chan = mhi_dev->dl_chan; 1251 int ret; 1252 1253 /* Bring device out of LPM */ 1254 ret = mhi_device_get_sync(mhi_dev); 1255 if (ret) 1256 return ret; 1257 1258 ret = -EINVAL; 1259 1260 if (ul_chan) { 1261 /* 1262 * If channel supports LPM notifications then status_cb should 1263 * be provided 1264 */ 1265 if (ul_chan->lpm_notify && !mhi_drv->status_cb) 1266 goto exit_probe; 1267 1268 /* For non-offload channels then xfer_cb should be provided */ 1269 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb) 1270 goto exit_probe; 1271 1272 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb; 1273 } 1274 1275 ret = -EINVAL; 1276 if (dl_chan) { 1277 /* 1278 * If channel supports LPM notifications then status_cb should 1279 * be provided 1280 */ 1281 if (dl_chan->lpm_notify && !mhi_drv->status_cb) 1282 goto exit_probe; 1283 1284 /* For non-offload channels then xfer_cb should be provided */ 1285 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb) 1286 goto exit_probe; 1287 1288 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index]; 1289 1290 /* 1291 * If the channel event ring is managed by client, then 1292 * status_cb must be provided so that the framework can 1293 * notify pending data 1294 */ 1295 if (mhi_event->cl_manage && !mhi_drv->status_cb) 1296 goto exit_probe; 1297 1298 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb; 1299 } 1300 1301 /* Call the user provided probe function */ 1302 ret = mhi_drv->probe(mhi_dev, mhi_dev->id); 1303 if (ret) 1304 goto exit_probe; 1305 1306 mhi_device_put(mhi_dev); 1307 1308 return ret; 1309 1310exit_probe: 1311 mhi_unprepare_from_transfer(mhi_dev); 1312 1313 mhi_device_put(mhi_dev); 1314 1315 return ret; 1316} 1317 1318static int mhi_driver_remove(struct device *dev) 1319{ 1320 struct mhi_device *mhi_dev = to_mhi_device(dev); 1321 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver); 1322 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1323 struct mhi_chan *mhi_chan; 1324 enum mhi_ch_state ch_state[] = { 1325 MHI_CH_STATE_DISABLED, 1326 MHI_CH_STATE_DISABLED 1327 }; 1328 int dir; 1329 1330 /* Skip if it is a controller device */ 1331 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) 1332 return 0; 1333 1334 /* Reset both channels */ 1335 for (dir = 0; dir < 2; dir++) { 1336 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; 1337 1338 if (!mhi_chan) 1339 continue; 1340 1341 /* Wake all threads waiting for completion */ 1342 write_lock_irq(&mhi_chan->lock); 1343 mhi_chan->ccs = MHI_EV_CC_INVALID; 1344 complete_all(&mhi_chan->completion); 1345 write_unlock_irq(&mhi_chan->lock); 1346 1347 /* Set the channel state to disabled */ 1348 mutex_lock(&mhi_chan->mutex); 1349 write_lock_irq(&mhi_chan->lock); 1350 ch_state[dir] = mhi_chan->ch_state; 1351 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED; 1352 write_unlock_irq(&mhi_chan->lock); 1353 1354 /* Reset the non-offload channel */ 1355 if (!mhi_chan->offload_ch) 1356 mhi_reset_chan(mhi_cntrl, mhi_chan); 1357 1358 mutex_unlock(&mhi_chan->mutex); 1359 } 1360 1361 mhi_drv->remove(mhi_dev); 1362 1363 /* De-init channel if it was enabled */ 1364 for (dir = 0; dir < 2; dir++) { 1365 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; 1366 1367 if (!mhi_chan) 1368 continue; 1369 1370 mutex_lock(&mhi_chan->mutex); 1371 1372 if ((ch_state[dir] == MHI_CH_STATE_ENABLED || 1373 ch_state[dir] == MHI_CH_STATE_STOP) && 1374 !mhi_chan->offload_ch) 1375 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); 1376 1377 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 1378 1379 mutex_unlock(&mhi_chan->mutex); 1380 } 1381 1382 while (mhi_dev->dev_wake) 1383 mhi_device_put(mhi_dev); 1384 1385 return 0; 1386} 1387 1388int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner) 1389{ 1390 struct device_driver *driver = &mhi_drv->driver; 1391 1392 if (!mhi_drv->probe || !mhi_drv->remove) 1393 return -EINVAL; 1394 1395 driver->bus = &mhi_bus_type; 1396 driver->owner = owner; 1397 driver->probe = mhi_driver_probe; 1398 driver->remove = mhi_driver_remove; 1399 1400 return driver_register(driver); 1401} 1402EXPORT_SYMBOL_GPL(__mhi_driver_register); 1403 1404void mhi_driver_unregister(struct mhi_driver *mhi_drv) 1405{ 1406 driver_unregister(&mhi_drv->driver); 1407} 1408EXPORT_SYMBOL_GPL(mhi_driver_unregister); 1409 1410static int mhi_uevent(const struct device *dev, struct kobj_uevent_env *env) 1411{ 1412 const struct mhi_device *mhi_dev = to_mhi_device(dev); 1413 1414 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT, 1415 mhi_dev->name); 1416} 1417 1418static int mhi_match(struct device *dev, struct device_driver *drv) 1419{ 1420 struct mhi_device *mhi_dev = to_mhi_device(dev); 1421 struct mhi_driver *mhi_drv = to_mhi_driver(drv); 1422 const struct mhi_device_id *id; 1423 1424 /* 1425 * If the device is a controller type then there is no client driver 1426 * associated with it 1427 */ 1428 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) 1429 return 0; 1430 1431 for (id = mhi_drv->id_table; id->chan[0]; id++) 1432 if (!strcmp(mhi_dev->name, id->chan)) { 1433 mhi_dev->id = id; 1434 return 1; 1435 } 1436 1437 return 0; 1438}; 1439 1440struct bus_type mhi_bus_type = { 1441 .name = "mhi", 1442 .dev_name = "mhi", 1443 .match = mhi_match, 1444 .uevent = mhi_uevent, 1445 .dev_groups = mhi_dev_groups, 1446}; 1447 1448static int __init mhi_init(void) 1449{ 1450 mhi_debugfs_init(); 1451 return bus_register(&mhi_bus_type); 1452} 1453 1454static void __exit mhi_exit(void) 1455{ 1456 mhi_debugfs_exit(); 1457 bus_unregister(&mhi_bus_type); 1458} 1459 1460postcore_initcall(mhi_init); 1461module_exit(mhi_exit); 1462 1463MODULE_LICENSE("GPL v2"); 1464MODULE_DESCRIPTION("Modem Host Interface"); 1465