162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#ifndef DRIVER_ATM_ENI_H 862306a36Sopenharmony_ci#define DRIVER_ATM_ENI_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include <linux/atm.h> 1162306a36Sopenharmony_ci#include <linux/atmdev.h> 1262306a36Sopenharmony_ci#include <linux/interrupt.h> 1362306a36Sopenharmony_ci#include <linux/sonet.h> 1462306a36Sopenharmony_ci#include <linux/skbuff.h> 1562306a36Sopenharmony_ci#include <linux/time.h> 1662306a36Sopenharmony_ci#include <linux/pci.h> 1762306a36Sopenharmony_ci#include <linux/spinlock.h> 1862306a36Sopenharmony_ci#include <linux/atomic.h> 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci#include "midway.h" 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#define DEV_LABEL "eni" 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci#define UBR_BUFFER (128*1024) /* UBR buffer size */ 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci#define RX_DMA_BUF 8 /* burst and skip a few things */ 2862306a36Sopenharmony_ci#define TX_DMA_BUF 100 /* should be enough for 64 kB */ 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci#define DEFAULT_RX_MULT 300 /* max_sdu*3 */ 3162306a36Sopenharmony_ci#define DEFAULT_TX_MULT 300 /* max_sdu*3 */ 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#define ENI_ZEROES_SIZE 4 /* need that many DMA-able zero bytes */ 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_cistruct eni_free { 3762306a36Sopenharmony_ci void __iomem *start; /* counting in bytes */ 3862306a36Sopenharmony_ci int order; 3962306a36Sopenharmony_ci}; 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_cistruct eni_tx { 4262306a36Sopenharmony_ci void __iomem *send; /* base, 0 if unused */ 4362306a36Sopenharmony_ci int prescaler; /* shaping prescaler */ 4462306a36Sopenharmony_ci int resolution; /* shaping divider */ 4562306a36Sopenharmony_ci unsigned long tx_pos; /* current TX write position */ 4662306a36Sopenharmony_ci unsigned long words; /* size of TX queue */ 4762306a36Sopenharmony_ci int index; /* TX channel number */ 4862306a36Sopenharmony_ci int reserved; /* reserved peak cell rate */ 4962306a36Sopenharmony_ci int shaping; /* shaped peak cell rate */ 5062306a36Sopenharmony_ci struct sk_buff_head backlog; /* queue of waiting TX buffers */ 5162306a36Sopenharmony_ci}; 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_cistruct eni_vcc { 5462306a36Sopenharmony_ci int (*rx)(struct atm_vcc *vcc); /* RX function, NULL if none */ 5562306a36Sopenharmony_ci void __iomem *recv; /* receive buffer */ 5662306a36Sopenharmony_ci unsigned long words; /* its size in words */ 5762306a36Sopenharmony_ci unsigned long descr; /* next descriptor (RX) */ 5862306a36Sopenharmony_ci unsigned long rx_pos; /* current RX descriptor pos */ 5962306a36Sopenharmony_ci struct eni_tx *tx; /* TXer, NULL if none */ 6062306a36Sopenharmony_ci int rxing; /* number of pending PDUs */ 6162306a36Sopenharmony_ci int servicing; /* number of waiting VCs (0 or 1) */ 6262306a36Sopenharmony_ci int txing; /* number of pending TX bytes */ 6362306a36Sopenharmony_ci ktime_t timestamp; /* for RX timing */ 6462306a36Sopenharmony_ci struct atm_vcc *next; /* next pending RX */ 6562306a36Sopenharmony_ci struct sk_buff *last; /* last PDU being DMAed (used to carry 6662306a36Sopenharmony_ci discard information) */ 6762306a36Sopenharmony_ci}; 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_cistruct eni_dev { 7062306a36Sopenharmony_ci /*-------------------------------- spinlock */ 7162306a36Sopenharmony_ci spinlock_t lock; /* sync with interrupt */ 7262306a36Sopenharmony_ci struct tasklet_struct task; /* tasklet for interrupt work */ 7362306a36Sopenharmony_ci u32 events; /* pending events */ 7462306a36Sopenharmony_ci /*-------------------------------- base pointers into Midway address 7562306a36Sopenharmony_ci space */ 7662306a36Sopenharmony_ci void __iomem *ioaddr; 7762306a36Sopenharmony_ci void __iomem *phy; /* PHY interface chip registers */ 7862306a36Sopenharmony_ci void __iomem *reg; /* register base */ 7962306a36Sopenharmony_ci void __iomem *ram; /* RAM base */ 8062306a36Sopenharmony_ci void __iomem *vci; /* VCI table */ 8162306a36Sopenharmony_ci void __iomem *rx_dma; /* RX DMA queue */ 8262306a36Sopenharmony_ci void __iomem *tx_dma; /* TX DMA queue */ 8362306a36Sopenharmony_ci void __iomem *service; /* service list */ 8462306a36Sopenharmony_ci /*-------------------------------- TX part */ 8562306a36Sopenharmony_ci struct eni_tx tx[NR_CHAN]; /* TX channels */ 8662306a36Sopenharmony_ci struct eni_tx *ubr; /* UBR channel */ 8762306a36Sopenharmony_ci struct sk_buff_head tx_queue; /* PDUs currently being TX DMAed*/ 8862306a36Sopenharmony_ci wait_queue_head_t tx_wait; /* for close */ 8962306a36Sopenharmony_ci int tx_bw; /* remaining bandwidth */ 9062306a36Sopenharmony_ci u32 dma[TX_DMA_BUF*2]; /* DMA request scratch area */ 9162306a36Sopenharmony_ci struct eni_zero { /* aligned "magic" zeroes */ 9262306a36Sopenharmony_ci u32 *addr; 9362306a36Sopenharmony_ci dma_addr_t dma; 9462306a36Sopenharmony_ci } zero; 9562306a36Sopenharmony_ci int tx_mult; /* buffer size multiplier (percent) */ 9662306a36Sopenharmony_ci /*-------------------------------- RX part */ 9762306a36Sopenharmony_ci u32 serv_read; /* host service read index */ 9862306a36Sopenharmony_ci struct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */ 9962306a36Sopenharmony_ci struct atm_vcc *slow,*last_slow; 10062306a36Sopenharmony_ci struct atm_vcc **rx_map; /* for fast lookups */ 10162306a36Sopenharmony_ci struct sk_buff_head rx_queue; /* PDUs currently being RX-DMAed */ 10262306a36Sopenharmony_ci wait_queue_head_t rx_wait; /* for close */ 10362306a36Sopenharmony_ci int rx_mult; /* buffer size multiplier (percent) */ 10462306a36Sopenharmony_ci /*-------------------------------- statistics */ 10562306a36Sopenharmony_ci unsigned long lost; /* number of lost cells (RX) */ 10662306a36Sopenharmony_ci /*-------------------------------- memory management */ 10762306a36Sopenharmony_ci unsigned long base_diff; /* virtual-real base address */ 10862306a36Sopenharmony_ci int free_len; /* free list length */ 10962306a36Sopenharmony_ci struct eni_free *free_list; /* free list */ 11062306a36Sopenharmony_ci int free_list_size; /* maximum size of free list */ 11162306a36Sopenharmony_ci /*-------------------------------- ENI links */ 11262306a36Sopenharmony_ci struct atm_dev *more; /* other ENI devices */ 11362306a36Sopenharmony_ci /*-------------------------------- general information */ 11462306a36Sopenharmony_ci int mem; /* RAM on board (in bytes) */ 11562306a36Sopenharmony_ci int asic; /* PCI interface type, 0 for FPGA */ 11662306a36Sopenharmony_ci unsigned int irq; /* IRQ */ 11762306a36Sopenharmony_ci struct pci_dev *pci_dev; /* PCI stuff */ 11862306a36Sopenharmony_ci}; 11962306a36Sopenharmony_ci 12062306a36Sopenharmony_ci 12162306a36Sopenharmony_ci#define ENI_DEV(d) ((struct eni_dev *) (d)->dev_data) 12262306a36Sopenharmony_ci#define ENI_VCC(d) ((struct eni_vcc *) (d)->dev_data) 12362306a36Sopenharmony_ci 12462306a36Sopenharmony_ci 12562306a36Sopenharmony_cistruct eni_skb_prv { 12662306a36Sopenharmony_ci struct atm_skb_data _; /* reserved */ 12762306a36Sopenharmony_ci unsigned long pos; /* position of next descriptor */ 12862306a36Sopenharmony_ci int size; /* PDU size in reassembly buffer */ 12962306a36Sopenharmony_ci dma_addr_t paddr; /* DMA handle */ 13062306a36Sopenharmony_ci}; 13162306a36Sopenharmony_ci 13262306a36Sopenharmony_ci#define ENI_PRV_SIZE(skb) (((struct eni_skb_prv *) (skb)->cb)->size) 13362306a36Sopenharmony_ci#define ENI_PRV_POS(skb) (((struct eni_skb_prv *) (skb)->cb)->pos) 13462306a36Sopenharmony_ci#define ENI_PRV_PADDR(skb) (((struct eni_skb_prv *) (skb)->cb)->paddr) 13562306a36Sopenharmony_ci 13662306a36Sopenharmony_ci#endif 137