1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * sata_promise.c - Promise SATA 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Mikael Pettersson 7 * Please ALWAYS copy linux-ide@vger.kernel.org 8 * on emails. 9 * 10 * Copyright 2003-2004 Red Hat, Inc. 11 * 12 * libata documentation is available via 'make {ps|pdf}docs', 13 * as Documentation/driver-api/libata.rst 14 * 15 * Hardware information only available under NDA. 16 */ 17 18#include <linux/kernel.h> 19#include <linux/module.h> 20#include <linux/gfp.h> 21#include <linux/pci.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <linux/interrupt.h> 25#include <linux/device.h> 26#include <scsi/scsi.h> 27#include <scsi/scsi_host.h> 28#include <scsi/scsi_cmnd.h> 29#include <linux/libata.h> 30#include "sata_promise.h" 31 32#define DRV_NAME "sata_promise" 33#define DRV_VERSION "2.12" 34 35enum { 36 PDC_MAX_PORTS = 4, 37 PDC_MMIO_BAR = 3, 38 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ 39 40 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */ 41 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 42 PDC_FLASH_CTL = 0x44, /* Flash control register */ 43 PDC_PCI_CTL = 0x48, /* PCI control/status reg */ 44 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 45 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 46 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 47 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 48 49 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */ 50 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 51 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 52 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 53 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 54 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 55 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 56 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 57 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 58 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 59 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 60 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 61 62 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */ 63 PDC_SATA_ERROR = 0x04, 64 PDC_PHYMODE4 = 0x14, 65 PDC_LINK_LAYER_ERRORS = 0x6C, 66 PDC_FPDMA_CTLSTAT = 0xD8, 67 PDC_INTERNAL_DEBUG_1 = 0xF8, /* also used for PATA */ 68 PDC_INTERNAL_DEBUG_2 = 0xFC, /* also used for PATA */ 69 70 /* PDC_FPDMA_CTLSTAT bit definitions */ 71 PDC_FPDMA_CTLSTAT_RESET = 1 << 3, 72 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10, 73 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11, 74 75 /* PDC_GLOBAL_CTL bit definitions */ 76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 84 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | 89 PDC2_ATA_DMA_CNT_ERR, 90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | 91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | 92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | 93 PDC1_ERR_MASK | PDC2_ERR_MASK, 94 95 board_2037x = 0, /* FastTrak S150 TX2plus */ 96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 97 board_20319 = 2, /* FastTrak S150 TX4 */ 98 board_20619 = 3, /* FastTrak TX4000 */ 99 board_2057x = 4, /* SATAII150 Tx2plus */ 100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 101 board_40518 = 6, /* SATAII150 Tx4 */ 102 103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 104 105 /* Sequence counter control registers bit definitions */ 106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 107 108 /* Feature register values */ 109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 111 112 /* Device/Head register values */ 113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 114 115 /* PDC_CTLSTAT bit definitions */ 116 PDC_DMA_ENABLE = (1 << 7), 117 PDC_IRQ_DISABLE = (1 << 10), 118 PDC_RESET = (1 << 11), /* HDMA reset */ 119 120 PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING, 121 122 /* ap->flags bits */ 123 PDC_FLAG_GEN_II = (1 << 24), 124 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 125 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 126}; 127 128struct pdc_port_priv { 129 u8 *pkt; 130 dma_addr_t pkt_dma; 131}; 132 133struct pdc_host_priv { 134 spinlock_t hard_reset_lock; 135}; 136 137static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 138static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 139static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 140static int pdc_common_port_start(struct ata_port *ap); 141static int pdc_sata_port_start(struct ata_port *ap); 142static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc); 143static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 144static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 145static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 146static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 147static void pdc_irq_clear(struct ata_port *ap); 148static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc); 149static void pdc_freeze(struct ata_port *ap); 150static void pdc_sata_freeze(struct ata_port *ap); 151static void pdc_thaw(struct ata_port *ap); 152static void pdc_sata_thaw(struct ata_port *ap); 153static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, 154 unsigned long deadline); 155static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, 156 unsigned long deadline); 157static void pdc_error_handler(struct ata_port *ap); 158static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 159static int pdc_pata_cable_detect(struct ata_port *ap); 160 161static const struct scsi_host_template pdc_ata_sht = { 162 ATA_BASE_SHT(DRV_NAME), 163 .sg_tablesize = PDC_MAX_PRD, 164 .dma_boundary = ATA_DMA_BOUNDARY, 165}; 166 167static const struct ata_port_operations pdc_common_ops = { 168 .inherits = &ata_sff_port_ops, 169 170 .sff_tf_load = pdc_tf_load_mmio, 171 .sff_exec_command = pdc_exec_command_mmio, 172 .check_atapi_dma = pdc_check_atapi_dma, 173 .qc_prep = pdc_qc_prep, 174 .qc_issue = pdc_qc_issue, 175 176 .sff_irq_clear = pdc_irq_clear, 177 .lost_interrupt = ATA_OP_NULL, 178 179 .post_internal_cmd = pdc_post_internal_cmd, 180 .error_handler = pdc_error_handler, 181}; 182 183static struct ata_port_operations pdc_sata_ops = { 184 .inherits = &pdc_common_ops, 185 .cable_detect = ata_cable_sata, 186 .freeze = pdc_sata_freeze, 187 .thaw = pdc_sata_thaw, 188 .scr_read = pdc_sata_scr_read, 189 .scr_write = pdc_sata_scr_write, 190 .port_start = pdc_sata_port_start, 191 .hardreset = pdc_sata_hardreset, 192}; 193 194/* First-generation chips need a more restrictive ->check_atapi_dma op, 195 and ->freeze/thaw that ignore the hotplug controls. */ 196static struct ata_port_operations pdc_old_sata_ops = { 197 .inherits = &pdc_sata_ops, 198 .freeze = pdc_freeze, 199 .thaw = pdc_thaw, 200 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 201}; 202 203static struct ata_port_operations pdc_pata_ops = { 204 .inherits = &pdc_common_ops, 205 .cable_detect = pdc_pata_cable_detect, 206 .freeze = pdc_freeze, 207 .thaw = pdc_thaw, 208 .port_start = pdc_common_port_start, 209 .softreset = pdc_pata_softreset, 210}; 211 212static const struct ata_port_info pdc_port_info[] = { 213 [board_2037x] = 214 { 215 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 216 PDC_FLAG_SATA_PATA, 217 .pio_mask = ATA_PIO4, 218 .mwdma_mask = ATA_MWDMA2, 219 .udma_mask = ATA_UDMA6, 220 .port_ops = &pdc_old_sata_ops, 221 }, 222 223 [board_2037x_pata] = 224 { 225 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 226 .pio_mask = ATA_PIO4, 227 .mwdma_mask = ATA_MWDMA2, 228 .udma_mask = ATA_UDMA6, 229 .port_ops = &pdc_pata_ops, 230 }, 231 232 [board_20319] = 233 { 234 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 235 PDC_FLAG_4_PORTS, 236 .pio_mask = ATA_PIO4, 237 .mwdma_mask = ATA_MWDMA2, 238 .udma_mask = ATA_UDMA6, 239 .port_ops = &pdc_old_sata_ops, 240 }, 241 242 [board_20619] = 243 { 244 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 245 PDC_FLAG_4_PORTS, 246 .pio_mask = ATA_PIO4, 247 .mwdma_mask = ATA_MWDMA2, 248 .udma_mask = ATA_UDMA6, 249 .port_ops = &pdc_pata_ops, 250 }, 251 252 [board_2057x] = 253 { 254 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 255 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 256 .pio_mask = ATA_PIO4, 257 .mwdma_mask = ATA_MWDMA2, 258 .udma_mask = ATA_UDMA6, 259 .port_ops = &pdc_sata_ops, 260 }, 261 262 [board_2057x_pata] = 263 { 264 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 265 PDC_FLAG_GEN_II, 266 .pio_mask = ATA_PIO4, 267 .mwdma_mask = ATA_MWDMA2, 268 .udma_mask = ATA_UDMA6, 269 .port_ops = &pdc_pata_ops, 270 }, 271 272 [board_40518] = 273 { 274 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 275 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 276 .pio_mask = ATA_PIO4, 277 .mwdma_mask = ATA_MWDMA2, 278 .udma_mask = ATA_UDMA6, 279 .port_ops = &pdc_sata_ops, 280 }, 281}; 282 283static const struct pci_device_id pdc_ata_pci_tbl[] = { 284 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 285 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 286 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 287 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 288 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 289 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 290 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 291 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 292 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 293 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 294 295 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 296 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 297 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, 298 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, 299 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 300 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 301 302 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 303 304 { } /* terminate list */ 305}; 306 307static struct pci_driver pdc_ata_pci_driver = { 308 .name = DRV_NAME, 309 .id_table = pdc_ata_pci_tbl, 310 .probe = pdc_ata_init_one, 311 .remove = ata_pci_remove_one, 312}; 313 314static int pdc_common_port_start(struct ata_port *ap) 315{ 316 struct device *dev = ap->host->dev; 317 struct pdc_port_priv *pp; 318 int rc; 319 320 /* we use the same prd table as bmdma, allocate it */ 321 rc = ata_bmdma_port_start(ap); 322 if (rc) 323 return rc; 324 325 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 326 if (!pp) 327 return -ENOMEM; 328 329 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 330 if (!pp->pkt) 331 return -ENOMEM; 332 333 ap->private_data = pp; 334 335 return 0; 336} 337 338static int pdc_sata_port_start(struct ata_port *ap) 339{ 340 int rc; 341 342 rc = pdc_common_port_start(ap); 343 if (rc) 344 return rc; 345 346 /* fix up PHYMODE4 align timing */ 347 if (ap->flags & PDC_FLAG_GEN_II) { 348 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 349 unsigned int tmp; 350 351 tmp = readl(sata_mmio + PDC_PHYMODE4); 352 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 353 writel(tmp, sata_mmio + PDC_PHYMODE4); 354 } 355 356 return 0; 357} 358 359static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap) 360{ 361 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 362 u32 tmp; 363 364 tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT); 365 tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG; 366 tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG; 367 368 /* It's not allowed to write to the entire FPDMA_CTLSTAT register 369 when NCQ is running. So do a byte-sized write to bits 10 and 11. */ 370 writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1); 371 readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */ 372} 373 374static void pdc_fpdma_reset(struct ata_port *ap) 375{ 376 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 377 u8 tmp; 378 379 tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT); 380 tmp &= 0x7F; 381 tmp |= PDC_FPDMA_CTLSTAT_RESET; 382 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); 383 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ 384 udelay(100); 385 tmp &= ~PDC_FPDMA_CTLSTAT_RESET; 386 writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT); 387 readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */ 388 389 pdc_fpdma_clear_interrupt_flag(ap); 390} 391 392static void pdc_not_at_command_packet_phase(struct ata_port *ap) 393{ 394 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 395 unsigned int i; 396 u32 tmp; 397 398 /* check not at ASIC packet command phase */ 399 for (i = 0; i < 100; ++i) { 400 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1); 401 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2); 402 if ((tmp & 0xF) != 1) 403 break; 404 udelay(100); 405 } 406} 407 408static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap) 409{ 410 void __iomem *sata_mmio = ap->ioaddr.scr_addr; 411 412 writel(0xffffffff, sata_mmio + PDC_SATA_ERROR); 413 writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS); 414} 415 416static void pdc_reset_port(struct ata_port *ap) 417{ 418 void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 419 unsigned int i; 420 u32 tmp; 421 422 if (ap->flags & PDC_FLAG_GEN_II) 423 pdc_not_at_command_packet_phase(ap); 424 425 tmp = readl(ata_ctlstat_mmio); 426 tmp |= PDC_RESET; 427 writel(tmp, ata_ctlstat_mmio); 428 429 for (i = 11; i > 0; i--) { 430 tmp = readl(ata_ctlstat_mmio); 431 if (tmp & PDC_RESET) 432 break; 433 434 udelay(100); 435 436 tmp |= PDC_RESET; 437 writel(tmp, ata_ctlstat_mmio); 438 } 439 440 tmp &= ~PDC_RESET; 441 writel(tmp, ata_ctlstat_mmio); 442 readl(ata_ctlstat_mmio); /* flush */ 443 444 if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) { 445 pdc_fpdma_reset(ap); 446 pdc_clear_internal_debug_record_error_register(ap); 447 } 448} 449 450static int pdc_pata_cable_detect(struct ata_port *ap) 451{ 452 u8 tmp; 453 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 454 455 tmp = readb(ata_mmio + PDC_CTLSTAT + 3); 456 if (tmp & 0x01) 457 return ATA_CBL_PATA40; 458 return ATA_CBL_PATA80; 459} 460 461static int pdc_sata_scr_read(struct ata_link *link, 462 unsigned int sc_reg, u32 *val) 463{ 464 if (sc_reg > SCR_CONTROL) 465 return -EINVAL; 466 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); 467 return 0; 468} 469 470static int pdc_sata_scr_write(struct ata_link *link, 471 unsigned int sc_reg, u32 val) 472{ 473 if (sc_reg > SCR_CONTROL) 474 return -EINVAL; 475 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); 476 return 0; 477} 478 479static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 480{ 481 struct ata_port *ap = qc->ap; 482 dma_addr_t sg_table = ap->bmdma_prd_dma; 483 unsigned int cdb_len = qc->dev->cdb_len; 484 u8 *cdb = qc->cdb; 485 struct pdc_port_priv *pp = ap->private_data; 486 u8 *buf = pp->pkt; 487 __le32 *buf32 = (__le32 *) buf; 488 unsigned int dev_sel, feature; 489 490 /* set control bits (byte 0), zero delay seq id (byte 3), 491 * and seq id (byte 2) 492 */ 493 switch (qc->tf.protocol) { 494 case ATAPI_PROT_DMA: 495 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 496 buf32[0] = cpu_to_le32(PDC_PKT_READ); 497 else 498 buf32[0] = 0; 499 break; 500 case ATAPI_PROT_NODATA: 501 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 502 break; 503 default: 504 BUG(); 505 break; 506 } 507 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 508 buf32[2] = 0; /* no next-packet */ 509 510 /* select drive */ 511 if (sata_scr_valid(&ap->link)) 512 dev_sel = PDC_DEVICE_SATA; 513 else 514 dev_sel = qc->tf.device; 515 516 buf[12] = (1 << 5) | ATA_REG_DEVICE; 517 buf[13] = dev_sel; 518 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 519 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 520 521 buf[16] = (1 << 5) | ATA_REG_NSECT; 522 buf[17] = qc->tf.nsect; 523 buf[18] = (1 << 5) | ATA_REG_LBAL; 524 buf[19] = qc->tf.lbal; 525 526 /* set feature and byte counter registers */ 527 if (qc->tf.protocol != ATAPI_PROT_DMA) 528 feature = PDC_FEATURE_ATAPI_PIO; 529 else 530 feature = PDC_FEATURE_ATAPI_DMA; 531 532 buf[20] = (1 << 5) | ATA_REG_FEATURE; 533 buf[21] = feature; 534 buf[22] = (1 << 5) | ATA_REG_BYTEL; 535 buf[23] = qc->tf.lbam; 536 buf[24] = (1 << 5) | ATA_REG_BYTEH; 537 buf[25] = qc->tf.lbah; 538 539 /* send ATAPI packet command 0xA0 */ 540 buf[26] = (1 << 5) | ATA_REG_CMD; 541 buf[27] = qc->tf.command; 542 543 /* select drive and check DRQ */ 544 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 545 buf[29] = dev_sel; 546 547 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 548 BUG_ON(cdb_len & ~0x1E); 549 550 /* append the CDB as the final part */ 551 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 552 memcpy(buf+31, cdb, cdb_len); 553} 554 555/** 556 * pdc_fill_sg - Fill PCI IDE PRD table 557 * @qc: Metadata associated with taskfile to be transferred 558 * 559 * Fill PCI IDE PRD (scatter-gather) table with segments 560 * associated with the current disk command. 561 * Make sure hardware does not choke on it. 562 * 563 * LOCKING: 564 * spin_lock_irqsave(host lock) 565 * 566 */ 567static void pdc_fill_sg(struct ata_queued_cmd *qc) 568{ 569 struct ata_port *ap = qc->ap; 570 struct ata_bmdma_prd *prd = ap->bmdma_prd; 571 struct scatterlist *sg; 572 const u32 SG_COUNT_ASIC_BUG = 41*4; 573 unsigned int si, idx; 574 u32 len; 575 576 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 577 return; 578 579 idx = 0; 580 for_each_sg(qc->sg, sg, qc->n_elem, si) { 581 u32 addr, offset; 582 u32 sg_len; 583 584 /* determine if physical DMA addr spans 64K boundary. 585 * Note h/w doesn't support 64-bit, so we unconditionally 586 * truncate dma_addr_t to u32. 587 */ 588 addr = (u32) sg_dma_address(sg); 589 sg_len = sg_dma_len(sg); 590 591 while (sg_len) { 592 offset = addr & 0xffff; 593 len = sg_len; 594 if ((offset + sg_len) > 0x10000) 595 len = 0x10000 - offset; 596 597 prd[idx].addr = cpu_to_le32(addr); 598 prd[idx].flags_len = cpu_to_le32(len & 0xffff); 599 ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n", 600 idx, addr, len); 601 602 idx++; 603 sg_len -= len; 604 addr += len; 605 } 606 } 607 608 len = le32_to_cpu(prd[idx - 1].flags_len); 609 610 if (len > SG_COUNT_ASIC_BUG) { 611 u32 addr; 612 613 addr = le32_to_cpu(prd[idx - 1].addr); 614 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); 615 ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n", 616 idx - 1, addr, SG_COUNT_ASIC_BUG); 617 618 addr = addr + len - SG_COUNT_ASIC_BUG; 619 len = SG_COUNT_ASIC_BUG; 620 prd[idx].addr = cpu_to_le32(addr); 621 prd[idx].flags_len = cpu_to_le32(len); 622 ata_port_dbg(ap, "PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 623 624 idx++; 625 } 626 627 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 628} 629 630static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc) 631{ 632 struct pdc_port_priv *pp = qc->ap->private_data; 633 unsigned int i; 634 635 switch (qc->tf.protocol) { 636 case ATA_PROT_DMA: 637 pdc_fill_sg(qc); 638 fallthrough; 639 case ATA_PROT_NODATA: 640 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma, 641 qc->dev->devno, pp->pkt); 642 if (qc->tf.flags & ATA_TFLAG_LBA48) 643 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 644 else 645 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 646 pdc_pkt_footer(&qc->tf, pp->pkt, i); 647 break; 648 case ATAPI_PROT_PIO: 649 pdc_fill_sg(qc); 650 break; 651 case ATAPI_PROT_DMA: 652 pdc_fill_sg(qc); 653 fallthrough; 654 case ATAPI_PROT_NODATA: 655 pdc_atapi_pkt(qc); 656 break; 657 default: 658 break; 659 } 660 661 return AC_ERR_OK; 662} 663 664static int pdc_is_sataii_tx4(unsigned long flags) 665{ 666 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 667 return (flags & mask) == mask; 668} 669 670static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, 671 int is_sataii_tx4) 672{ 673 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 674 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 675} 676 677static unsigned int pdc_sata_nr_ports(const struct ata_port *ap) 678{ 679 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2; 680} 681 682static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap) 683{ 684 const struct ata_host *host = ap->host; 685 unsigned int nr_ports = pdc_sata_nr_ports(ap); 686 unsigned int i; 687 688 for (i = 0; i < nr_ports && host->ports[i] != ap; ++i) 689 ; 690 BUG_ON(i >= nr_ports); 691 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags)); 692} 693 694static void pdc_freeze(struct ata_port *ap) 695{ 696 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 697 u32 tmp; 698 699 tmp = readl(ata_mmio + PDC_CTLSTAT); 700 tmp |= PDC_IRQ_DISABLE; 701 tmp &= ~PDC_DMA_ENABLE; 702 writel(tmp, ata_mmio + PDC_CTLSTAT); 703 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 704} 705 706static void pdc_sata_freeze(struct ata_port *ap) 707{ 708 struct ata_host *host = ap->host; 709 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 710 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR; 711 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 712 u32 hotplug_status; 713 714 /* Disable hotplug events on this port. 715 * 716 * Locking: 717 * 1) hotplug register accesses must be serialised via host->lock 718 * 2) ap->lock == &ap->host->lock 719 * 3) ->freeze() and ->thaw() are called with ap->lock held 720 */ 721 hotplug_status = readl(host_mmio + hotplug_offset); 722 hotplug_status |= 0x11 << (ata_no + 16); 723 writel(hotplug_status, host_mmio + hotplug_offset); 724 readl(host_mmio + hotplug_offset); /* flush */ 725 726 pdc_freeze(ap); 727} 728 729static void pdc_thaw(struct ata_port *ap) 730{ 731 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 732 u32 tmp; 733 734 /* clear IRQ */ 735 readl(ata_mmio + PDC_COMMAND); 736 737 /* turn IRQ back on */ 738 tmp = readl(ata_mmio + PDC_CTLSTAT); 739 tmp &= ~PDC_IRQ_DISABLE; 740 writel(tmp, ata_mmio + PDC_CTLSTAT); 741 readl(ata_mmio + PDC_CTLSTAT); /* flush */ 742} 743 744static void pdc_sata_thaw(struct ata_port *ap) 745{ 746 struct ata_host *host = ap->host; 747 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 748 unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR; 749 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap); 750 u32 hotplug_status; 751 752 pdc_thaw(ap); 753 754 /* Enable hotplug events on this port. 755 * Locking: see pdc_sata_freeze(). 756 */ 757 hotplug_status = readl(host_mmio + hotplug_offset); 758 hotplug_status |= 0x11 << ata_no; 759 hotplug_status &= ~(0x11 << (ata_no + 16)); 760 writel(hotplug_status, host_mmio + hotplug_offset); 761 readl(host_mmio + hotplug_offset); /* flush */ 762} 763 764static int pdc_pata_softreset(struct ata_link *link, unsigned int *class, 765 unsigned long deadline) 766{ 767 pdc_reset_port(link->ap); 768 return ata_sff_softreset(link, class, deadline); 769} 770 771static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap) 772{ 773 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 774 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 775 776 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */ 777 return (ata_mmio - host_mmio - 0x200) / 0x80; 778} 779 780static void pdc_hard_reset_port(struct ata_port *ap) 781{ 782 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 783 void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1; 784 unsigned int ata_no = pdc_ata_port_to_ata_no(ap); 785 struct pdc_host_priv *hpriv = ap->host->private_data; 786 u8 tmp; 787 788 spin_lock(&hpriv->hard_reset_lock); 789 790 tmp = readb(pcictl_b1_mmio); 791 tmp &= ~(0x10 << ata_no); 792 writeb(tmp, pcictl_b1_mmio); 793 readb(pcictl_b1_mmio); /* flush */ 794 udelay(100); 795 tmp |= (0x10 << ata_no); 796 writeb(tmp, pcictl_b1_mmio); 797 readb(pcictl_b1_mmio); /* flush */ 798 799 spin_unlock(&hpriv->hard_reset_lock); 800} 801 802static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class, 803 unsigned long deadline) 804{ 805 if (link->ap->flags & PDC_FLAG_GEN_II) 806 pdc_not_at_command_packet_phase(link->ap); 807 /* hotplug IRQs should have been masked by pdc_sata_freeze() */ 808 pdc_hard_reset_port(link->ap); 809 pdc_reset_port(link->ap); 810 811 /* sata_promise can't reliably acquire the first D2H Reg FIS 812 * after hardreset. Do non-waiting hardreset and request 813 * follow-up SRST. 814 */ 815 return sata_std_hardreset(link, class, deadline); 816} 817 818static void pdc_error_handler(struct ata_port *ap) 819{ 820 if (!ata_port_is_frozen(ap)) 821 pdc_reset_port(ap); 822 823 ata_sff_error_handler(ap); 824} 825 826static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 827{ 828 struct ata_port *ap = qc->ap; 829 830 /* make DMA engine forget about the failed command */ 831 if (qc->flags & ATA_QCFLAG_EH) 832 pdc_reset_port(ap); 833} 834 835static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 836 u32 port_status, u32 err_mask) 837{ 838 struct ata_eh_info *ehi = &ap->link.eh_info; 839 unsigned int ac_err_mask = 0; 840 841 ata_ehi_clear_desc(ehi); 842 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 843 port_status &= err_mask; 844 845 if (port_status & PDC_DRIVE_ERR) 846 ac_err_mask |= AC_ERR_DEV; 847 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 848 ac_err_mask |= AC_ERR_OTHER; 849 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 850 ac_err_mask |= AC_ERR_ATA_BUS; 851 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 852 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 853 ac_err_mask |= AC_ERR_HOST_BUS; 854 855 if (sata_scr_valid(&ap->link)) { 856 u32 serror; 857 858 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror); 859 ehi->serror |= serror; 860 } 861 862 qc->err_mask |= ac_err_mask; 863 864 pdc_reset_port(ap); 865 866 ata_port_abort(ap); 867} 868 869static unsigned int pdc_host_intr(struct ata_port *ap, 870 struct ata_queued_cmd *qc) 871{ 872 unsigned int handled = 0; 873 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 874 u32 port_status, err_mask; 875 876 err_mask = PDC_ERR_MASK; 877 if (ap->flags & PDC_FLAG_GEN_II) 878 err_mask &= ~PDC1_ERR_MASK; 879 else 880 err_mask &= ~PDC2_ERR_MASK; 881 port_status = readl(ata_mmio + PDC_GLOBAL_CTL); 882 if (unlikely(port_status & err_mask)) { 883 pdc_error_intr(ap, qc, port_status, err_mask); 884 return 1; 885 } 886 887 switch (qc->tf.protocol) { 888 case ATA_PROT_DMA: 889 case ATA_PROT_NODATA: 890 case ATAPI_PROT_DMA: 891 case ATAPI_PROT_NODATA: 892 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 893 ata_qc_complete(qc); 894 handled = 1; 895 break; 896 default: 897 ap->stats.idle_irq++; 898 break; 899 } 900 901 return handled; 902} 903 904static void pdc_irq_clear(struct ata_port *ap) 905{ 906 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 907 908 readl(ata_mmio + PDC_COMMAND); 909} 910 911static irqreturn_t pdc_interrupt(int irq, void *dev_instance) 912{ 913 struct ata_host *host = dev_instance; 914 struct ata_port *ap; 915 u32 mask = 0; 916 unsigned int i, tmp; 917 unsigned int handled = 0; 918 void __iomem *host_mmio; 919 unsigned int hotplug_offset, ata_no; 920 u32 hotplug_status; 921 int is_sataii_tx4; 922 923 if (!host || !host->iomap[PDC_MMIO_BAR]) 924 return IRQ_NONE; 925 926 host_mmio = host->iomap[PDC_MMIO_BAR]; 927 928 spin_lock(&host->lock); 929 930 /* read and clear hotplug flags for all ports */ 931 if (host->ports[0]->flags & PDC_FLAG_GEN_II) { 932 hotplug_offset = PDC2_SATA_PLUG_CSR; 933 hotplug_status = readl(host_mmio + hotplug_offset); 934 if (hotplug_status & 0xff) 935 writel(hotplug_status | 0xff, host_mmio + hotplug_offset); 936 hotplug_status &= 0xff; /* clear uninteresting bits */ 937 } else 938 hotplug_status = 0; 939 940 /* reading should also clear interrupts */ 941 mask = readl(host_mmio + PDC_INT_SEQMASK); 942 943 if (mask == 0xffffffff && hotplug_status == 0) 944 goto done_irq; 945 946 mask &= 0xffff; /* only 16 SEQIDs possible */ 947 if (mask == 0 && hotplug_status == 0) 948 goto done_irq; 949 950 writel(mask, host_mmio + PDC_INT_SEQMASK); 951 952 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 953 954 for (i = 0; i < host->n_ports; i++) { 955 ap = host->ports[i]; 956 957 /* check for a plug or unplug event */ 958 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 959 tmp = hotplug_status & (0x11 << ata_no); 960 if (tmp) { 961 struct ata_eh_info *ehi = &ap->link.eh_info; 962 ata_ehi_clear_desc(ehi); 963 ata_ehi_hotplugged(ehi); 964 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); 965 ata_port_freeze(ap); 966 ++handled; 967 continue; 968 } 969 970 /* check for a packet interrupt */ 971 tmp = mask & (1 << (i + 1)); 972 if (tmp) { 973 struct ata_queued_cmd *qc; 974 975 qc = ata_qc_from_tag(ap, ap->link.active_tag); 976 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 977 handled += pdc_host_intr(ap, qc); 978 } 979 } 980 981done_irq: 982 spin_unlock(&host->lock); 983 return IRQ_RETVAL(handled); 984} 985 986static void pdc_packet_start(struct ata_queued_cmd *qc) 987{ 988 struct ata_port *ap = qc->ap; 989 struct pdc_port_priv *pp = ap->private_data; 990 void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR]; 991 void __iomem *ata_mmio = ap->ioaddr.cmd_addr; 992 unsigned int port_no = ap->port_no; 993 u8 seq = (u8) (port_no + 1); 994 995 writel(0x00000001, host_mmio + (seq * 4)); 996 readl(host_mmio + (seq * 4)); /* flush */ 997 998 pp->pkt[2] = seq; 999 wmb(); /* flush PRD, pkt writes */ 1000 writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT); 1001 readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */ 1002} 1003 1004static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) 1005{ 1006 switch (qc->tf.protocol) { 1007 case ATAPI_PROT_NODATA: 1008 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 1009 break; 1010 fallthrough; 1011 case ATA_PROT_NODATA: 1012 if (qc->tf.flags & ATA_TFLAG_POLLING) 1013 break; 1014 fallthrough; 1015 case ATAPI_PROT_DMA: 1016 case ATA_PROT_DMA: 1017 pdc_packet_start(qc); 1018 return 0; 1019 default: 1020 break; 1021 } 1022 return ata_sff_qc_issue(qc); 1023} 1024 1025static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 1026{ 1027 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 1028 ata_sff_tf_load(ap, tf); 1029} 1030 1031static void pdc_exec_command_mmio(struct ata_port *ap, 1032 const struct ata_taskfile *tf) 1033{ 1034 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 1035 ata_sff_exec_command(ap, tf); 1036} 1037 1038static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 1039{ 1040 u8 *scsicmd = qc->scsicmd->cmnd; 1041 int pio = 1; /* atapi dma off by default */ 1042 1043 /* Whitelist commands that may use DMA. */ 1044 switch (scsicmd[0]) { 1045 case WRITE_12: 1046 case WRITE_10: 1047 case WRITE_6: 1048 case READ_12: 1049 case READ_10: 1050 case READ_6: 1051 case 0xad: /* READ_DVD_STRUCTURE */ 1052 case 0xbe: /* READ_CD */ 1053 pio = 0; 1054 } 1055 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 1056 if (scsicmd[0] == WRITE_10) { 1057 unsigned int lba = 1058 (scsicmd[2] << 24) | 1059 (scsicmd[3] << 16) | 1060 (scsicmd[4] << 8) | 1061 scsicmd[5]; 1062 if (lba >= 0xFFFF4FA2) 1063 pio = 1; 1064 } 1065 return pio; 1066} 1067 1068static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 1069{ 1070 /* First generation chips cannot use ATAPI DMA on SATA ports */ 1071 return 1; 1072} 1073 1074static void pdc_ata_setup_port(struct ata_port *ap, 1075 void __iomem *base, void __iomem *scr_addr) 1076{ 1077 ap->ioaddr.cmd_addr = base; 1078 ap->ioaddr.data_addr = base; 1079 ap->ioaddr.feature_addr = 1080 ap->ioaddr.error_addr = base + 0x4; 1081 ap->ioaddr.nsect_addr = base + 0x8; 1082 ap->ioaddr.lbal_addr = base + 0xc; 1083 ap->ioaddr.lbam_addr = base + 0x10; 1084 ap->ioaddr.lbah_addr = base + 0x14; 1085 ap->ioaddr.device_addr = base + 0x18; 1086 ap->ioaddr.command_addr = 1087 ap->ioaddr.status_addr = base + 0x1c; 1088 ap->ioaddr.altstatus_addr = 1089 ap->ioaddr.ctl_addr = base + 0x38; 1090 ap->ioaddr.scr_addr = scr_addr; 1091} 1092 1093static void pdc_host_init(struct ata_host *host) 1094{ 1095 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR]; 1096 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 1097 int hotplug_offset; 1098 u32 tmp; 1099 1100 if (is_gen2) 1101 hotplug_offset = PDC2_SATA_PLUG_CSR; 1102 else 1103 hotplug_offset = PDC_SATA_PLUG_CSR; 1104 1105 /* 1106 * Except for the hotplug stuff, this is voodoo from the 1107 * Promise driver. Label this entire section 1108 * "TODO: figure out why we do this" 1109 */ 1110 1111 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 1112 tmp = readl(host_mmio + PDC_FLASH_CTL); 1113 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 1114 if (!is_gen2) 1115 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 1116 writel(tmp, host_mmio + PDC_FLASH_CTL); 1117 1118 /* clear plug/unplug flags for all ports */ 1119 tmp = readl(host_mmio + hotplug_offset); 1120 writel(tmp | 0xff, host_mmio + hotplug_offset); 1121 1122 tmp = readl(host_mmio + hotplug_offset); 1123 if (is_gen2) /* unmask plug/unplug ints */ 1124 writel(tmp & ~0xff0000, host_mmio + hotplug_offset); 1125 else /* mask plug/unplug ints */ 1126 writel(tmp | 0xff0000, host_mmio + hotplug_offset); 1127 1128 /* don't initialise TBG or SLEW on 2nd generation chips */ 1129 if (is_gen2) 1130 return; 1131 1132 /* reduce TBG clock to 133 Mhz. */ 1133 tmp = readl(host_mmio + PDC_TBG_MODE); 1134 tmp &= ~0x30000; /* clear bit 17, 16*/ 1135 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 1136 writel(tmp, host_mmio + PDC_TBG_MODE); 1137 1138 readl(host_mmio + PDC_TBG_MODE); /* flush */ 1139 msleep(10); 1140 1141 /* adjust slew rate control register. */ 1142 tmp = readl(host_mmio + PDC_SLEW_CTL); 1143 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 1144 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 1145 writel(tmp, host_mmio + PDC_SLEW_CTL); 1146} 1147 1148static int pdc_ata_init_one(struct pci_dev *pdev, 1149 const struct pci_device_id *ent) 1150{ 1151 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 1152 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 1153 struct ata_host *host; 1154 struct pdc_host_priv *hpriv; 1155 void __iomem *host_mmio; 1156 int n_ports, i, rc; 1157 int is_sataii_tx4; 1158 1159 ata_print_version_once(&pdev->dev, DRV_VERSION); 1160 1161 /* enable and acquire resources */ 1162 rc = pcim_enable_device(pdev); 1163 if (rc) 1164 return rc; 1165 1166 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 1167 if (rc == -EBUSY) 1168 pcim_pin_device(pdev); 1169 if (rc) 1170 return rc; 1171 host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 1172 1173 /* determine port configuration and setup host */ 1174 n_ports = 2; 1175 if (pi->flags & PDC_FLAG_4_PORTS) 1176 n_ports = 4; 1177 for (i = 0; i < n_ports; i++) 1178 ppi[i] = pi; 1179 1180 if (pi->flags & PDC_FLAG_SATA_PATA) { 1181 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1); 1182 if (!(tmp & 0x80)) 1183 ppi[n_ports++] = pi + 1; 1184 } 1185 1186 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1187 if (!host) { 1188 dev_err(&pdev->dev, "failed to allocate host\n"); 1189 return -ENOMEM; 1190 } 1191 hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL); 1192 if (!hpriv) 1193 return -ENOMEM; 1194 spin_lock_init(&hpriv->hard_reset_lock); 1195 host->private_data = hpriv; 1196 host->iomap = pcim_iomap_table(pdev); 1197 1198 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 1199 for (i = 0; i < host->n_ports; i++) { 1200 struct ata_port *ap = host->ports[i]; 1201 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1202 unsigned int ata_offset = 0x200 + ata_no * 0x80; 1203 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1204 1205 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset); 1206 1207 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1208 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata"); 1209 } 1210 1211 /* initialize adapter */ 1212 pdc_host_init(host); 1213 1214 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); 1215 if (rc) 1216 return rc; 1217 1218 /* start host, request IRQ and attach */ 1219 pci_set_master(pdev); 1220 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1221 &pdc_ata_sht); 1222} 1223 1224module_pci_driver(pdc_ata_pci_driver); 1225 1226MODULE_AUTHOR("Jeff Garzik"); 1227MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1228MODULE_LICENSE("GPL"); 1229MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1230MODULE_VERSION(DRV_VERSION); 1231