1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/pci.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <linux/interrupt.h> 25#include <linux/dma-mapping.h> 26#include <linux/device.h> 27#include <linux/dmi.h> 28#include <linux/gfp.h> 29#include <scsi/scsi_host.h> 30#include <scsi/scsi_cmnd.h> 31#include <linux/libata.h> 32#include <linux/ahci-remap.h> 33#include <linux/io-64-nonatomic-lo-hi.h> 34#include "ahci.h" 35 36#define DRV_NAME "ahci" 37#define DRV_VERSION "3.0" 38 39enum { 40 AHCI_PCI_BAR_STA2X11 = 0, 41 AHCI_PCI_BAR_CAVIUM = 0, 42 AHCI_PCI_BAR_LOONGSON = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46}; 47 48enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_43bit_dma, 52 board_ahci_ign_iferr, 53 board_ahci_low_power, 54 board_ahci_no_debounce_delay, 55 board_ahci_nomsi, 56 board_ahci_noncq, 57 board_ahci_nosntf, 58 board_ahci_yes_fbs, 59 60 /* board IDs for specific chipsets in alphabetical order */ 61 board_ahci_al, 62 board_ahci_avn, 63 board_ahci_mcp65, 64 board_ahci_mcp77, 65 board_ahci_mcp89, 66 board_ahci_mv, 67 board_ahci_sb600, 68 board_ahci_sb700, /* for SB700 and SB800 */ 69 board_ahci_vt8251, 70 71 /* 72 * board IDs for Intel chipsets that support more than 6 ports 73 * *and* end up needing the PCS quirk. 74 */ 75 board_ahci_pcs7, 76 77 /* aliases */ 78 board_ahci_mcp_linux = board_ahci_mcp65, 79 board_ahci_mcp67 = board_ahci_mcp65, 80 board_ahci_mcp73 = board_ahci_mcp65, 81 board_ahci_mcp79 = board_ahci_mcp77, 82}; 83 84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 85static void ahci_remove_one(struct pci_dev *dev); 86static void ahci_shutdown_one(struct pci_dev *dev); 87static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv); 88static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 89 unsigned long deadline); 90static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 91 unsigned long deadline); 92static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 93static bool is_mcp89_apple(struct pci_dev *pdev); 94static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 95 unsigned long deadline); 96#ifdef CONFIG_PM 97static int ahci_pci_device_runtime_suspend(struct device *dev); 98static int ahci_pci_device_runtime_resume(struct device *dev); 99#ifdef CONFIG_PM_SLEEP 100static int ahci_pci_device_suspend(struct device *dev); 101static int ahci_pci_device_resume(struct device *dev); 102#endif 103#endif /* CONFIG_PM */ 104 105static const struct scsi_host_template ahci_sht = { 106 AHCI_SHT("ahci"), 107}; 108 109static struct ata_port_operations ahci_vt8251_ops = { 110 .inherits = &ahci_ops, 111 .hardreset = ahci_vt8251_hardreset, 112}; 113 114static struct ata_port_operations ahci_p5wdh_ops = { 115 .inherits = &ahci_ops, 116 .hardreset = ahci_p5wdh_hardreset, 117}; 118 119static struct ata_port_operations ahci_avn_ops = { 120 .inherits = &ahci_ops, 121 .hardreset = ahci_avn_hardreset, 122}; 123 124static const struct ata_port_info ahci_port_info[] = { 125 /* by features */ 126 [board_ahci] = { 127 .flags = AHCI_FLAG_COMMON, 128 .pio_mask = ATA_PIO4, 129 .udma_mask = ATA_UDMA6, 130 .port_ops = &ahci_ops, 131 }, 132 [board_ahci_43bit_dma] = { 133 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY), 134 .flags = AHCI_FLAG_COMMON, 135 .pio_mask = ATA_PIO4, 136 .udma_mask = ATA_UDMA6, 137 .port_ops = &ahci_ops, 138 }, 139 [board_ahci_ign_iferr] = { 140 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 141 .flags = AHCI_FLAG_COMMON, 142 .pio_mask = ATA_PIO4, 143 .udma_mask = ATA_UDMA6, 144 .port_ops = &ahci_ops, 145 }, 146 [board_ahci_low_power] = { 147 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY), 148 .flags = AHCI_FLAG_COMMON, 149 .pio_mask = ATA_PIO4, 150 .udma_mask = ATA_UDMA6, 151 .port_ops = &ahci_ops, 152 }, 153 [board_ahci_no_debounce_delay] = { 154 .flags = AHCI_FLAG_COMMON, 155 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, 156 .pio_mask = ATA_PIO4, 157 .udma_mask = ATA_UDMA6, 158 .port_ops = &ahci_ops, 159 }, 160 [board_ahci_nomsi] = { 161 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 162 .flags = AHCI_FLAG_COMMON, 163 .pio_mask = ATA_PIO4, 164 .udma_mask = ATA_UDMA6, 165 .port_ops = &ahci_ops, 166 }, 167 [board_ahci_noncq] = { 168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 169 .flags = AHCI_FLAG_COMMON, 170 .pio_mask = ATA_PIO4, 171 .udma_mask = ATA_UDMA6, 172 .port_ops = &ahci_ops, 173 }, 174 [board_ahci_nosntf] = { 175 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 176 .flags = AHCI_FLAG_COMMON, 177 .pio_mask = ATA_PIO4, 178 .udma_mask = ATA_UDMA6, 179 .port_ops = &ahci_ops, 180 }, 181 [board_ahci_yes_fbs] = { 182 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 183 .flags = AHCI_FLAG_COMMON, 184 .pio_mask = ATA_PIO4, 185 .udma_mask = ATA_UDMA6, 186 .port_ops = &ahci_ops, 187 }, 188 /* by chipsets */ 189 [board_ahci_al] = { 190 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 191 .flags = AHCI_FLAG_COMMON, 192 .pio_mask = ATA_PIO4, 193 .udma_mask = ATA_UDMA6, 194 .port_ops = &ahci_ops, 195 }, 196 [board_ahci_avn] = { 197 .flags = AHCI_FLAG_COMMON, 198 .pio_mask = ATA_PIO4, 199 .udma_mask = ATA_UDMA6, 200 .port_ops = &ahci_avn_ops, 201 }, 202 [board_ahci_mcp65] = { 203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 204 AHCI_HFLAG_YES_NCQ), 205 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 206 .pio_mask = ATA_PIO4, 207 .udma_mask = ATA_UDMA6, 208 .port_ops = &ahci_ops, 209 }, 210 [board_ahci_mcp77] = { 211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 212 .flags = AHCI_FLAG_COMMON, 213 .pio_mask = ATA_PIO4, 214 .udma_mask = ATA_UDMA6, 215 .port_ops = &ahci_ops, 216 }, 217 [board_ahci_mcp89] = { 218 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 219 .flags = AHCI_FLAG_COMMON, 220 .pio_mask = ATA_PIO4, 221 .udma_mask = ATA_UDMA6, 222 .port_ops = &ahci_ops, 223 }, 224 [board_ahci_mv] = { 225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 226 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 227 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 228 .pio_mask = ATA_PIO4, 229 .udma_mask = ATA_UDMA6, 230 .port_ops = &ahci_ops, 231 }, 232 [board_ahci_sb600] = { 233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 234 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 235 AHCI_HFLAG_32BIT_ONLY), 236 .flags = AHCI_FLAG_COMMON, 237 .pio_mask = ATA_PIO4, 238 .udma_mask = ATA_UDMA6, 239 .port_ops = &ahci_pmp_retry_srst_ops, 240 }, 241 [board_ahci_sb700] = { /* for SB700 and SB800 */ 242 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 243 .flags = AHCI_FLAG_COMMON, 244 .pio_mask = ATA_PIO4, 245 .udma_mask = ATA_UDMA6, 246 .port_ops = &ahci_pmp_retry_srst_ops, 247 }, 248 [board_ahci_vt8251] = { 249 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 250 .flags = AHCI_FLAG_COMMON, 251 .pio_mask = ATA_PIO4, 252 .udma_mask = ATA_UDMA6, 253 .port_ops = &ahci_vt8251_ops, 254 }, 255 [board_ahci_pcs7] = { 256 .flags = AHCI_FLAG_COMMON, 257 .pio_mask = ATA_PIO4, 258 .udma_mask = ATA_UDMA6, 259 .port_ops = &ahci_ops, 260 }, 261}; 262 263static const struct pci_device_id ahci_pci_tbl[] = { 264 /* Intel */ 265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */ 266 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 267 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 268 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 269 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 270 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 271 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 272 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 273 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 274 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 276 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 277 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/ 278 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 279 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 280 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 281 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 282 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 283 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 284 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 285 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 286 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ 287 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ 288 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ 289 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ 290 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ 291 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 292 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ 293 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 294 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 295 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 296 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 297 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 298 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 299 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 300 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 301 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 302 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ 303 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 304 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ 305 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 308 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 309 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 310 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 311 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 312 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 313 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 314 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 315 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 316 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 317 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 318 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 319 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 320 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 321 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 322 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 323 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 324 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 325 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 326 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 327 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ 328 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 329 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ 330 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 331 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 332 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 333 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 334 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 335 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 336 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 337 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ 338 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 339 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 340 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 341 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ 342 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 343 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 344 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ 345 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 346 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ 347 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 348 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ 349 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 350 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ 351 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ 352 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ 353 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ 354 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ 355 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ 356 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ 357 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ 358 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ 359 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ 360 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 361 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 362 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 363 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 364 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 365 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 366 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 367 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 368 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 369 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 370 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 371 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 372 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 373 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 374 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 375 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/ 377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */ 378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */ 379 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */ 380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */ 381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */ 382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */ 383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */ 384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ 394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ 395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ 396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ 397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ 399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ 401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ 403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ 405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ 406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ 407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ 408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ 410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ 413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 414 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 415 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 416 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 417 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 418 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 419 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 420 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 421 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 422 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 423 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ 424 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ 425 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ 426 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ 427 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ 428 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ 429 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ 430 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ 431 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ 432 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ 433 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */ 434 435 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 436 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 437 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 438 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 439 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 440 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 441 /* May need to update quirk_jmicron_async_suspend() for additions */ 442 443 /* ATI */ 444 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 445 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 446 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 447 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 448 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 449 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 450 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 451 452 /* Amazon's Annapurna Labs support */ 453 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 454 .class = PCI_CLASS_STORAGE_SATA_AHCI, 455 .class_mask = 0xffffff, 456 board_ahci_al }, 457 /* AMD */ 458 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 459 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ 460 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 461 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */ 462 /* AMD is using RAID class only for ahci controllers */ 463 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 464 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 465 466 /* Dell S140/S150 */ 467 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID, 468 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 469 470 /* VIA */ 471 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 472 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 473 474 /* NVIDIA */ 475 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 476 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 477 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 478 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 479 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 480 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 481 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 482 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 483 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 484 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 485 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 486 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 487 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 488 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 489 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 490 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 491 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 492 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 493 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 494 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 495 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 496 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 497 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 498 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 499 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 500 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 501 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 502 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 503 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 504 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 505 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 506 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 507 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 508 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 509 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 510 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 511 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 512 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 513 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 514 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 515 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 516 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 517 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 518 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 519 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 520 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 521 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 522 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 523 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 524 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 525 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 526 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 527 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 528 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 529 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 530 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 531 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 532 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 533 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 534 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 535 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 536 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 537 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 538 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 539 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 540 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 541 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 542 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 543 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 544 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 545 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 546 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 547 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 548 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 549 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 550 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 551 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 552 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 553 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 554 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 555 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 556 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 557 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 558 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 559 560 /* SiS */ 561 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 562 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 563 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 564 565 /* ST Microelectronics */ 566 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 567 568 /* Marvell */ 569 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 570 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 572 .class = PCI_CLASS_STORAGE_SATA_AHCI, 573 .class_mask = 0xffffff, 574 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 576 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 577 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 578 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 579 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 581 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 583 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 585 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 587 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 589 .driver_data = board_ahci_yes_fbs }, 590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 591 .driver_data = board_ahci_yes_fbs }, 592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 593 .driver_data = board_ahci_yes_fbs }, 594 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 595 .driver_data = board_ahci_yes_fbs }, 596 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235), 597 .driver_data = board_ahci_no_debounce_delay }, 598 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 599 .driver_data = board_ahci_yes_fbs }, 600 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 601 .driver_data = board_ahci_yes_fbs }, 602 603 /* Promise */ 604 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 605 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 606 607 /* ASMedia */ 608 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */ 609 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */ 610 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */ 611 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */ 612 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */ 613 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */ 614 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */ 615 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */ 616 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */ 617 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */ 618 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */ 619 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */ 620 621 /* 622 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 623 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 624 */ 625 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 626 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 627 628 /* Enmotus */ 629 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 630 631 /* Loongson */ 632 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci }, 633 634 /* Generic, PCI class code for AHCI */ 635 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 636 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 637 638 { } /* terminate list */ 639}; 640 641static const struct dev_pm_ops ahci_pci_pm_ops = { 642 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 643 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 644 ahci_pci_device_runtime_resume, NULL) 645}; 646 647static struct pci_driver ahci_pci_driver = { 648 .name = DRV_NAME, 649 .id_table = ahci_pci_tbl, 650 .probe = ahci_init_one, 651 .remove = ahci_remove_one, 652 .shutdown = ahci_shutdown_one, 653 .driver = { 654 .pm = &ahci_pci_pm_ops, 655 }, 656}; 657 658#if IS_ENABLED(CONFIG_PATA_MARVELL) 659static int marvell_enable; 660#else 661static int marvell_enable = 1; 662#endif 663module_param(marvell_enable, int, 0644); 664MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 665 666static int mobile_lpm_policy = -1; 667module_param(mobile_lpm_policy, int, 0644); 668MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 669 670static void ahci_pci_save_initial_config(struct pci_dev *pdev, 671 struct ahci_host_priv *hpriv) 672{ 673 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && pdev->device == 0x1166) { 674 dev_info(&pdev->dev, "ASM1166 has only six ports\n"); 675 hpriv->saved_port_map = 0x3f; 676 } 677 678 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 679 dev_info(&pdev->dev, "JMB361 has only one port\n"); 680 hpriv->saved_port_map = 1; 681 } 682 683 /* 684 * Temporary Marvell 6145 hack: PATA port presence 685 * is asserted through the standard AHCI port 686 * presence register, as bit 4 (counting from 0) 687 */ 688 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 689 if (pdev->device == 0x6121) 690 hpriv->mask_port_map = 0x3; 691 else 692 hpriv->mask_port_map = 0xf; 693 dev_info(&pdev->dev, 694 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 695 } 696 697 ahci_save_initial_config(&pdev->dev, hpriv); 698} 699 700static int ahci_pci_reset_controller(struct ata_host *host) 701{ 702 struct pci_dev *pdev = to_pci_dev(host->dev); 703 struct ahci_host_priv *hpriv = host->private_data; 704 int rc; 705 706 rc = ahci_reset_controller(host); 707 if (rc) 708 return rc; 709 710 /* 711 * If platform firmware failed to enable ports, try to enable 712 * them here. 713 */ 714 ahci_intel_pcs_quirk(pdev, hpriv); 715 716 return 0; 717} 718 719static void ahci_pci_init_controller(struct ata_host *host) 720{ 721 struct ahci_host_priv *hpriv = host->private_data; 722 struct pci_dev *pdev = to_pci_dev(host->dev); 723 void __iomem *port_mmio; 724 u32 tmp; 725 int mv; 726 727 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 728 if (pdev->device == 0x6121) 729 mv = 2; 730 else 731 mv = 4; 732 port_mmio = __ahci_port_base(hpriv, mv); 733 734 writel(0, port_mmio + PORT_IRQ_MASK); 735 736 /* clear port IRQ */ 737 tmp = readl(port_mmio + PORT_IRQ_STAT); 738 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 739 if (tmp) 740 writel(tmp, port_mmio + PORT_IRQ_STAT); 741 } 742 743 ahci_init_controller(host); 744} 745 746static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 747 unsigned long deadline) 748{ 749 struct ata_port *ap = link->ap; 750 struct ahci_host_priv *hpriv = ap->host->private_data; 751 bool online; 752 int rc; 753 754 hpriv->stop_engine(ap); 755 756 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 757 deadline, &online, NULL); 758 759 hpriv->start_engine(ap); 760 761 /* vt8251 doesn't clear BSY on signature FIS reception, 762 * request follow-up softreset. 763 */ 764 return online ? -EAGAIN : rc; 765} 766 767static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 768 unsigned long deadline) 769{ 770 struct ata_port *ap = link->ap; 771 struct ahci_port_priv *pp = ap->private_data; 772 struct ahci_host_priv *hpriv = ap->host->private_data; 773 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 774 struct ata_taskfile tf; 775 bool online; 776 int rc; 777 778 hpriv->stop_engine(ap); 779 780 /* clear D2H reception area to properly wait for D2H FIS */ 781 ata_tf_init(link->device, &tf); 782 tf.status = ATA_BUSY; 783 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 784 785 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 786 deadline, &online, NULL); 787 788 hpriv->start_engine(ap); 789 790 /* The pseudo configuration device on SIMG4726 attached to 791 * ASUS P5W-DH Deluxe doesn't send signature FIS after 792 * hardreset if no device is attached to the first downstream 793 * port && the pseudo device locks up on SRST w/ PMP==0. To 794 * work around this, wait for !BSY only briefly. If BSY isn't 795 * cleared, perform CLO and proceed to IDENTIFY (achieved by 796 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 797 * 798 * Wait for two seconds. Devices attached to downstream port 799 * which can't process the following IDENTIFY after this will 800 * have to be reset again. For most cases, this should 801 * suffice while making probing snappish enough. 802 */ 803 if (online) { 804 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 805 ahci_check_ready); 806 if (rc) 807 ahci_kick_engine(ap); 808 } 809 return rc; 810} 811 812/* 813 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 814 * 815 * It has been observed with some SSDs that the timing of events in the 816 * link synchronization phase can leave the port in a state that can not 817 * be recovered by a SATA-hard-reset alone. The failing signature is 818 * SStatus.DET stuck at 1 ("Device presence detected but Phy 819 * communication not established"). It was found that unloading and 820 * reloading the driver when this problem occurs allows the drive 821 * connection to be recovered (DET advanced to 0x3). The critical 822 * component of reloading the driver is that the port state machines are 823 * reset by bouncing "port enable" in the AHCI PCS configuration 824 * register. So, reproduce that effect by bouncing a port whenever we 825 * see DET==1 after a reset. 826 */ 827static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 828 unsigned long deadline) 829{ 830 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context); 831 struct ata_port *ap = link->ap; 832 struct ahci_port_priv *pp = ap->private_data; 833 struct ahci_host_priv *hpriv = ap->host->private_data; 834 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 835 unsigned long tmo = deadline - jiffies; 836 struct ata_taskfile tf; 837 bool online; 838 int rc, i; 839 840 hpriv->stop_engine(ap); 841 842 for (i = 0; i < 2; i++) { 843 u16 val; 844 u32 sstatus; 845 int port = ap->port_no; 846 struct ata_host *host = ap->host; 847 struct pci_dev *pdev = to_pci_dev(host->dev); 848 849 /* clear D2H reception area to properly wait for D2H FIS */ 850 ata_tf_init(link->device, &tf); 851 tf.status = ATA_BUSY; 852 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 853 854 rc = sata_link_hardreset(link, timing, deadline, &online, 855 ahci_check_ready); 856 857 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 858 (sstatus & 0xf) != 1) 859 break; 860 861 ata_link_info(link, "avn bounce port%d\n", port); 862 863 pci_read_config_word(pdev, 0x92, &val); 864 val &= ~(1 << port); 865 pci_write_config_word(pdev, 0x92, val); 866 ata_msleep(ap, 1000); 867 val |= 1 << port; 868 pci_write_config_word(pdev, 0x92, val); 869 deadline += tmo; 870 } 871 872 hpriv->start_engine(ap); 873 874 if (online) 875 *class = ahci_dev_classify(ap); 876 877 return rc; 878} 879 880 881#ifdef CONFIG_PM 882static void ahci_pci_disable_interrupts(struct ata_host *host) 883{ 884 struct ahci_host_priv *hpriv = host->private_data; 885 void __iomem *mmio = hpriv->mmio; 886 u32 ctl; 887 888 /* AHCI spec rev1.1 section 8.3.3: 889 * Software must disable interrupts prior to requesting a 890 * transition of the HBA to D3 state. 891 */ 892 ctl = readl(mmio + HOST_CTL); 893 ctl &= ~HOST_IRQ_EN; 894 writel(ctl, mmio + HOST_CTL); 895 readl(mmio + HOST_CTL); /* flush */ 896} 897 898static int ahci_pci_device_runtime_suspend(struct device *dev) 899{ 900 struct pci_dev *pdev = to_pci_dev(dev); 901 struct ata_host *host = pci_get_drvdata(pdev); 902 903 ahci_pci_disable_interrupts(host); 904 return 0; 905} 906 907static int ahci_pci_device_runtime_resume(struct device *dev) 908{ 909 struct pci_dev *pdev = to_pci_dev(dev); 910 struct ata_host *host = pci_get_drvdata(pdev); 911 int rc; 912 913 rc = ahci_pci_reset_controller(host); 914 if (rc) 915 return rc; 916 ahci_pci_init_controller(host); 917 return 0; 918} 919 920#ifdef CONFIG_PM_SLEEP 921static int ahci_pci_device_suspend(struct device *dev) 922{ 923 struct pci_dev *pdev = to_pci_dev(dev); 924 struct ata_host *host = pci_get_drvdata(pdev); 925 struct ahci_host_priv *hpriv = host->private_data; 926 927 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 928 dev_err(&pdev->dev, 929 "BIOS update required for suspend/resume\n"); 930 return -EIO; 931 } 932 933 ahci_pci_disable_interrupts(host); 934 ata_host_suspend(host, PMSG_SUSPEND); 935 return 0; 936} 937 938static int ahci_pci_device_resume(struct device *dev) 939{ 940 struct pci_dev *pdev = to_pci_dev(dev); 941 struct ata_host *host = pci_get_drvdata(pdev); 942 int rc; 943 944 /* Apple BIOS helpfully mangles the registers on resume */ 945 if (is_mcp89_apple(pdev)) 946 ahci_mcp89_apple_enable(pdev); 947 948 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 949 rc = ahci_pci_reset_controller(host); 950 if (rc) 951 return rc; 952 953 ahci_pci_init_controller(host); 954 } 955 956 ata_host_resume(host); 957 958 return 0; 959} 960#endif 961 962#endif /* CONFIG_PM */ 963 964static int ahci_configure_dma_masks(struct pci_dev *pdev, 965 struct ahci_host_priv *hpriv) 966{ 967 int dma_bits; 968 int rc; 969 970 if (hpriv->cap & HOST_CAP_64) { 971 dma_bits = 64; 972 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY) 973 dma_bits = 43; 974 } else { 975 dma_bits = 32; 976 } 977 978 /* 979 * If the device fixup already set the dma_mask to some non-standard 980 * value, don't extend it here. This happens on STA2X11, for example. 981 * 982 * XXX: manipulating the DMA mask from platform code is completely 983 * bogus, platform code should use dev->bus_dma_limit instead.. 984 */ 985 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 986 return 0; 987 988 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 989 if (rc) 990 dev_err(&pdev->dev, "DMA enable failed\n"); 991 return rc; 992} 993 994static void ahci_pci_print_info(struct ata_host *host) 995{ 996 struct pci_dev *pdev = to_pci_dev(host->dev); 997 u16 cc; 998 const char *scc_s; 999 1000 pci_read_config_word(pdev, 0x0a, &cc); 1001 if (cc == PCI_CLASS_STORAGE_IDE) 1002 scc_s = "IDE"; 1003 else if (cc == PCI_CLASS_STORAGE_SATA) 1004 scc_s = "SATA"; 1005 else if (cc == PCI_CLASS_STORAGE_RAID) 1006 scc_s = "RAID"; 1007 else 1008 scc_s = "unknown"; 1009 1010 ahci_print_info(host, scc_s); 1011} 1012 1013/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 1014 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 1015 * support PMP and the 4726 either directly exports the device 1016 * attached to the first downstream port or acts as a hardware storage 1017 * controller and emulate a single ATA device (can be RAID 0/1 or some 1018 * other configuration). 1019 * 1020 * When there's no device attached to the first downstream port of the 1021 * 4726, "Config Disk" appears, which is a pseudo ATA device to 1022 * configure the 4726. However, ATA emulation of the device is very 1023 * lame. It doesn't send signature D2H Reg FIS after the initial 1024 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 1025 * 1026 * The following function works around the problem by always using 1027 * hardreset on the port and not depending on receiving signature FIS 1028 * afterward. If signature FIS isn't received soon, ATA class is 1029 * assumed without follow-up softreset. 1030 */ 1031static void ahci_p5wdh_workaround(struct ata_host *host) 1032{ 1033 static const struct dmi_system_id sysids[] = { 1034 { 1035 .ident = "P5W DH Deluxe", 1036 .matches = { 1037 DMI_MATCH(DMI_SYS_VENDOR, 1038 "ASUSTEK COMPUTER INC"), 1039 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 1040 }, 1041 }, 1042 { } 1043 }; 1044 struct pci_dev *pdev = to_pci_dev(host->dev); 1045 1046 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 1047 dmi_check_system(sysids)) { 1048 struct ata_port *ap = host->ports[1]; 1049 1050 dev_info(&pdev->dev, 1051 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 1052 1053 ap->ops = &ahci_p5wdh_ops; 1054 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 1055 } 1056} 1057 1058/* 1059 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 1060 * booting in BIOS compatibility mode. We restore the registers but not ID. 1061 */ 1062static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 1063{ 1064 u32 val; 1065 1066 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 1067 1068 pci_read_config_dword(pdev, 0xf8, &val); 1069 val |= 1 << 0x1b; 1070 /* the following changes the device ID, but appears not to affect function */ 1071 /* val = (val & ~0xf0000000) | 0x80000000; */ 1072 pci_write_config_dword(pdev, 0xf8, val); 1073 1074 pci_read_config_dword(pdev, 0x54c, &val); 1075 val |= 1 << 0xc; 1076 pci_write_config_dword(pdev, 0x54c, val); 1077 1078 pci_read_config_dword(pdev, 0x4a4, &val); 1079 val &= 0xff; 1080 val |= 0x01060100; 1081 pci_write_config_dword(pdev, 0x4a4, val); 1082 1083 pci_read_config_dword(pdev, 0x54c, &val); 1084 val &= ~(1 << 0xc); 1085 pci_write_config_dword(pdev, 0x54c, val); 1086 1087 pci_read_config_dword(pdev, 0xf8, &val); 1088 val &= ~(1 << 0x1b); 1089 pci_write_config_dword(pdev, 0xf8, val); 1090} 1091 1092static bool is_mcp89_apple(struct pci_dev *pdev) 1093{ 1094 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1095 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1096 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1097 pdev->subsystem_device == 0xcb89; 1098} 1099 1100/* only some SB600 ahci controllers can do 64bit DMA */ 1101static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1102{ 1103 static const struct dmi_system_id sysids[] = { 1104 /* 1105 * The oldest version known to be broken is 0901 and 1106 * working is 1501 which was released on 2007-10-26. 1107 * Enable 64bit DMA on 1501 and anything newer. 1108 * 1109 * Please read bko#9412 for more info. 1110 */ 1111 { 1112 .ident = "ASUS M2A-VM", 1113 .matches = { 1114 DMI_MATCH(DMI_BOARD_VENDOR, 1115 "ASUSTeK Computer INC."), 1116 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1117 }, 1118 .driver_data = "20071026", /* yyyymmdd */ 1119 }, 1120 /* 1121 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1122 * support 64bit DMA. 1123 * 1124 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1125 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1126 * This spelling mistake was fixed in BIOS version 1.5, so 1127 * 1.5 and later have the Manufacturer as 1128 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1129 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1130 * 1131 * BIOS versions earlier than 1.9 had a Board Product Name 1132 * DMI field of "MS-7376". This was changed to be 1133 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1134 * match on DMI_BOARD_NAME of "MS-7376". 1135 */ 1136 { 1137 .ident = "MSI K9A2 Platinum", 1138 .matches = { 1139 DMI_MATCH(DMI_BOARD_VENDOR, 1140 "MICRO-STAR INTER"), 1141 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1142 }, 1143 }, 1144 /* 1145 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1146 * 64bit DMA. 1147 * 1148 * This board also had the typo mentioned above in the 1149 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1150 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1151 */ 1152 { 1153 .ident = "MSI K9AGM2", 1154 .matches = { 1155 DMI_MATCH(DMI_BOARD_VENDOR, 1156 "MICRO-STAR INTER"), 1157 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1158 }, 1159 }, 1160 /* 1161 * All BIOS versions for the Asus M3A support 64bit DMA. 1162 * (all release versions from 0301 to 1206 were tested) 1163 */ 1164 { 1165 .ident = "ASUS M3A", 1166 .matches = { 1167 DMI_MATCH(DMI_BOARD_VENDOR, 1168 "ASUSTeK Computer INC."), 1169 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1170 }, 1171 }, 1172 { } 1173 }; 1174 const struct dmi_system_id *match; 1175 int year, month, date; 1176 char buf[9]; 1177 1178 match = dmi_first_match(sysids); 1179 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1180 !match) 1181 return false; 1182 1183 if (!match->driver_data) 1184 goto enable_64bit; 1185 1186 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1187 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1188 1189 if (strcmp(buf, match->driver_data) >= 0) 1190 goto enable_64bit; 1191 else { 1192 dev_warn(&pdev->dev, 1193 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1194 match->ident); 1195 return false; 1196 } 1197 1198enable_64bit: 1199 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1200 return true; 1201} 1202 1203static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1204{ 1205 static const struct dmi_system_id broken_systems[] = { 1206 { 1207 .ident = "HP Compaq nx6310", 1208 .matches = { 1209 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1210 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1211 }, 1212 /* PCI slot number of the controller */ 1213 .driver_data = (void *)0x1FUL, 1214 }, 1215 { 1216 .ident = "HP Compaq 6720s", 1217 .matches = { 1218 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1219 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1220 }, 1221 /* PCI slot number of the controller */ 1222 .driver_data = (void *)0x1FUL, 1223 }, 1224 1225 { } /* terminate list */ 1226 }; 1227 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1228 1229 if (dmi) { 1230 unsigned long slot = (unsigned long)dmi->driver_data; 1231 /* apply the quirk only to on-board controllers */ 1232 return slot == PCI_SLOT(pdev->devfn); 1233 } 1234 1235 return false; 1236} 1237 1238static bool ahci_broken_suspend(struct pci_dev *pdev) 1239{ 1240 static const struct dmi_system_id sysids[] = { 1241 /* 1242 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1243 * to the harddisk doesn't become online after 1244 * resuming from STR. Warn and fail suspend. 1245 * 1246 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1247 * 1248 * Use dates instead of versions to match as HP is 1249 * apparently recycling both product and version 1250 * strings. 1251 * 1252 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1253 */ 1254 { 1255 .ident = "dv4", 1256 .matches = { 1257 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1258 DMI_MATCH(DMI_PRODUCT_NAME, 1259 "HP Pavilion dv4 Notebook PC"), 1260 }, 1261 .driver_data = "20090105", /* F.30 */ 1262 }, 1263 { 1264 .ident = "dv5", 1265 .matches = { 1266 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1267 DMI_MATCH(DMI_PRODUCT_NAME, 1268 "HP Pavilion dv5 Notebook PC"), 1269 }, 1270 .driver_data = "20090506", /* F.16 */ 1271 }, 1272 { 1273 .ident = "dv6", 1274 .matches = { 1275 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1276 DMI_MATCH(DMI_PRODUCT_NAME, 1277 "HP Pavilion dv6 Notebook PC"), 1278 }, 1279 .driver_data = "20090423", /* F.21 */ 1280 }, 1281 { 1282 .ident = "HDX18", 1283 .matches = { 1284 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1285 DMI_MATCH(DMI_PRODUCT_NAME, 1286 "HP HDX18 Notebook PC"), 1287 }, 1288 .driver_data = "20090430", /* F.23 */ 1289 }, 1290 /* 1291 * Acer eMachines G725 has the same problem. BIOS 1292 * V1.03 is known to be broken. V3.04 is known to 1293 * work. Between, there are V1.06, V2.06 and V3.03 1294 * that we don't have much idea about. For now, 1295 * blacklist anything older than V3.04. 1296 * 1297 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1298 */ 1299 { 1300 .ident = "G725", 1301 .matches = { 1302 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1303 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1304 }, 1305 .driver_data = "20091216", /* V3.04 */ 1306 }, 1307 { } /* terminate list */ 1308 }; 1309 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1310 int year, month, date; 1311 char buf[9]; 1312 1313 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1314 return false; 1315 1316 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1317 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1318 1319 return strcmp(buf, dmi->driver_data) < 0; 1320} 1321 1322static bool ahci_broken_lpm(struct pci_dev *pdev) 1323{ 1324 static const struct dmi_system_id sysids[] = { 1325 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1326 { 1327 .matches = { 1328 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1329 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1330 }, 1331 .driver_data = "20180406", /* 1.31 */ 1332 }, 1333 { 1334 .matches = { 1335 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1336 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1337 }, 1338 .driver_data = "20180420", /* 1.28 */ 1339 }, 1340 { 1341 .matches = { 1342 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1343 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1344 }, 1345 .driver_data = "20180315", /* 1.33 */ 1346 }, 1347 { 1348 .matches = { 1349 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1350 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1351 }, 1352 /* 1353 * Note date based on release notes, 2.35 has been 1354 * reported to be good, but I've been unable to get 1355 * a hold of the reporter to get the DMI BIOS date. 1356 * TODO: fix this. 1357 */ 1358 .driver_data = "20180310", /* 2.35 */ 1359 }, 1360 { } /* terminate list */ 1361 }; 1362 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1363 int year, month, date; 1364 char buf[9]; 1365 1366 if (!dmi) 1367 return false; 1368 1369 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1370 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1371 1372 return strcmp(buf, dmi->driver_data) < 0; 1373} 1374 1375static bool ahci_broken_online(struct pci_dev *pdev) 1376{ 1377#define ENCODE_BUSDEVFN(bus, slot, func) \ 1378 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1379 static const struct dmi_system_id sysids[] = { 1380 /* 1381 * There are several gigabyte boards which use 1382 * SIMG5723s configured as hardware RAID. Certain 1383 * 5723 firmware revisions shipped there keep the link 1384 * online but fail to answer properly to SRST or 1385 * IDENTIFY when no device is attached downstream 1386 * causing libata to retry quite a few times leading 1387 * to excessive detection delay. 1388 * 1389 * As these firmwares respond to the second reset try 1390 * with invalid device signature, considering unknown 1391 * sig as offline works around the problem acceptably. 1392 */ 1393 { 1394 .ident = "EP45-DQ6", 1395 .matches = { 1396 DMI_MATCH(DMI_BOARD_VENDOR, 1397 "Gigabyte Technology Co., Ltd."), 1398 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1399 }, 1400 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1401 }, 1402 { 1403 .ident = "EP45-DS5", 1404 .matches = { 1405 DMI_MATCH(DMI_BOARD_VENDOR, 1406 "Gigabyte Technology Co., Ltd."), 1407 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1408 }, 1409 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1410 }, 1411 { } /* terminate list */ 1412 }; 1413#undef ENCODE_BUSDEVFN 1414 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1415 unsigned int val; 1416 1417 if (!dmi) 1418 return false; 1419 1420 val = (unsigned long)dmi->driver_data; 1421 1422 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1423} 1424 1425static bool ahci_broken_devslp(struct pci_dev *pdev) 1426{ 1427 /* device with broken DEVSLP but still showing SDS capability */ 1428 static const struct pci_device_id ids[] = { 1429 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1430 {} 1431 }; 1432 1433 return pci_match_id(ids, pdev); 1434} 1435 1436#ifdef CONFIG_ATA_ACPI 1437static void ahci_gtf_filter_workaround(struct ata_host *host) 1438{ 1439 static const struct dmi_system_id sysids[] = { 1440 /* 1441 * Aspire 3810T issues a bunch of SATA enable commands 1442 * via _GTF including an invalid one and one which is 1443 * rejected by the device. Among the successful ones 1444 * is FPDMA non-zero offset enable which when enabled 1445 * only on the drive side leads to NCQ command 1446 * failures. Filter it out. 1447 */ 1448 { 1449 .ident = "Aspire 3810T", 1450 .matches = { 1451 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1452 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1453 }, 1454 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1455 }, 1456 { } 1457 }; 1458 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1459 unsigned int filter; 1460 int i; 1461 1462 if (!dmi) 1463 return; 1464 1465 filter = (unsigned long)dmi->driver_data; 1466 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1467 filter, dmi->ident); 1468 1469 for (i = 0; i < host->n_ports; i++) { 1470 struct ata_port *ap = host->ports[i]; 1471 struct ata_link *link; 1472 struct ata_device *dev; 1473 1474 ata_for_each_link(link, ap, EDGE) 1475 ata_for_each_dev(dev, link, ALL) 1476 dev->gtf_filter |= filter; 1477 } 1478} 1479#else 1480static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1481{} 1482#endif 1483 1484/* 1485 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1486 * as DUMMY, or detected but eventually get a "link down" and never get up 1487 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1488 * port_map may hold a value of 0x00. 1489 * 1490 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1491 * and can significantly reduce the occurrence of the problem. 1492 * 1493 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1494 */ 1495static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1496 struct pci_dev *pdev) 1497{ 1498 static const struct dmi_system_id sysids[] = { 1499 { 1500 .ident = "Acer Switch Alpha 12", 1501 .matches = { 1502 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1503 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1504 }, 1505 }, 1506 { } 1507 }; 1508 1509 if (dmi_check_system(sysids)) { 1510 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1511 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1512 hpriv->port_map = 0x7; 1513 hpriv->cap = 0xC734FF02; 1514 } 1515 } 1516} 1517 1518#ifdef CONFIG_ARM64 1519/* 1520 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1521 * Workaround is to make sure all pending IRQs are served before leaving 1522 * handler. 1523 */ 1524static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1525{ 1526 struct ata_host *host = dev_instance; 1527 struct ahci_host_priv *hpriv; 1528 unsigned int rc = 0; 1529 void __iomem *mmio; 1530 u32 irq_stat, irq_masked; 1531 unsigned int handled = 1; 1532 1533 hpriv = host->private_data; 1534 mmio = hpriv->mmio; 1535 irq_stat = readl(mmio + HOST_IRQ_STAT); 1536 if (!irq_stat) 1537 return IRQ_NONE; 1538 1539 do { 1540 irq_masked = irq_stat & hpriv->port_map; 1541 spin_lock(&host->lock); 1542 rc = ahci_handle_port_intr(host, irq_masked); 1543 if (!rc) 1544 handled = 0; 1545 writel(irq_stat, mmio + HOST_IRQ_STAT); 1546 irq_stat = readl(mmio + HOST_IRQ_STAT); 1547 spin_unlock(&host->lock); 1548 } while (irq_stat); 1549 1550 return IRQ_RETVAL(handled); 1551} 1552#endif 1553 1554static void ahci_remap_check(struct pci_dev *pdev, int bar, 1555 struct ahci_host_priv *hpriv) 1556{ 1557 int i; 1558 u32 cap; 1559 1560 /* 1561 * Check if this device might have remapped nvme devices. 1562 */ 1563 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1564 pci_resource_len(pdev, bar) < SZ_512K || 1565 bar != AHCI_PCI_BAR_STANDARD || 1566 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1567 return; 1568 1569 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1570 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1571 if ((cap & (1 << i)) == 0) 1572 continue; 1573 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1574 != PCI_CLASS_STORAGE_EXPRESS) 1575 continue; 1576 1577 /* We've found a remapped device */ 1578 hpriv->remapped_nvme++; 1579 } 1580 1581 if (!hpriv->remapped_nvme) 1582 return; 1583 1584 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n", 1585 hpriv->remapped_nvme); 1586 dev_warn(&pdev->dev, 1587 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1588 1589 /* 1590 * Don't rely on the msi-x capability in the remap case, 1591 * share the legacy interrupt across ahci and remapped devices. 1592 */ 1593 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1594} 1595 1596static int ahci_get_irq_vector(struct ata_host *host, int port) 1597{ 1598 return pci_irq_vector(to_pci_dev(host->dev), port); 1599} 1600 1601static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1602 struct ahci_host_priv *hpriv) 1603{ 1604 int nvec; 1605 1606 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1607 return -ENODEV; 1608 1609 /* 1610 * If number of MSIs is less than number of ports then Sharing Last 1611 * Message mode could be enforced. In this case assume that advantage 1612 * of multipe MSIs is negated and use single MSI mode instead. 1613 */ 1614 if (n_ports > 1) { 1615 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1616 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1617 if (nvec > 0) { 1618 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1619 hpriv->get_irq_vector = ahci_get_irq_vector; 1620 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1621 return nvec; 1622 } 1623 1624 /* 1625 * Fallback to single MSI mode if the controller 1626 * enforced MRSM mode. 1627 */ 1628 printk(KERN_INFO 1629 "ahci: MRSM is on, fallback to single MSI\n"); 1630 pci_free_irq_vectors(pdev); 1631 } 1632 } 1633 1634 /* 1635 * If the host is not capable of supporting per-port vectors, fall 1636 * back to single MSI before finally attempting single MSI-X. 1637 */ 1638 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1639 if (nvec == 1) 1640 return nvec; 1641 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1642} 1643 1644static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1645 struct ahci_host_priv *hpriv) 1646{ 1647 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1648 1649 1650 /* Ignore processing for chipsets that don't use policy */ 1651 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY)) 1652 return; 1653 1654 /* user modified policy via module param */ 1655 if (mobile_lpm_policy != -1) { 1656 policy = mobile_lpm_policy; 1657 goto update_policy; 1658 } 1659 1660 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) { 1661 if (hpriv->cap & HOST_CAP_PART) 1662 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1663 else if (hpriv->cap & HOST_CAP_SSC) 1664 policy = ATA_LPM_MIN_POWER; 1665 } 1666 1667update_policy: 1668 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1669 ap->target_lpm_policy = policy; 1670} 1671 1672static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1673{ 1674 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1675 u16 tmp16; 1676 1677 /* 1678 * Only apply the 6-port PCS quirk for known legacy platforms. 1679 */ 1680 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1681 return; 1682 1683 /* Skip applying the quirk on Denverton and beyond */ 1684 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1685 return; 1686 1687 /* 1688 * port_map is determined from PORTS_IMPL PCI register which is 1689 * implemented as write or write-once register. If the register 1690 * isn't programmed, ahci automatically generates it from number 1691 * of ports, which is good enough for PCS programming. It is 1692 * otherwise expected that platform firmware enables the ports 1693 * before the OS boots. 1694 */ 1695 pci_read_config_word(pdev, PCS_6, &tmp16); 1696 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1697 tmp16 |= hpriv->port_map; 1698 pci_write_config_word(pdev, PCS_6, tmp16); 1699 } 1700} 1701 1702static ssize_t remapped_nvme_show(struct device *dev, 1703 struct device_attribute *attr, 1704 char *buf) 1705{ 1706 struct ata_host *host = dev_get_drvdata(dev); 1707 struct ahci_host_priv *hpriv = host->private_data; 1708 1709 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme); 1710} 1711 1712static DEVICE_ATTR_RO(remapped_nvme); 1713 1714static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1715{ 1716 unsigned int board_id = ent->driver_data; 1717 struct ata_port_info pi = ahci_port_info[board_id]; 1718 const struct ata_port_info *ppi[] = { &pi, NULL }; 1719 struct device *dev = &pdev->dev; 1720 struct ahci_host_priv *hpriv; 1721 struct ata_host *host; 1722 int n_ports, i, rc; 1723 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1724 1725 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1726 1727 ata_print_version_once(&pdev->dev, DRV_VERSION); 1728 1729 /* The AHCI driver can only drive the SATA ports, the PATA driver 1730 can drive them all so if both drivers are selected make sure 1731 AHCI stays out of the way */ 1732 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1733 return -ENODEV; 1734 1735 /* Apple BIOS on MCP89 prevents us using AHCI */ 1736 if (is_mcp89_apple(pdev)) 1737 ahci_mcp89_apple_enable(pdev); 1738 1739 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1740 * At the moment, we can only use the AHCI mode. Let the users know 1741 * that for SAS drives they're out of luck. 1742 */ 1743 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1744 dev_info(&pdev->dev, 1745 "PDC42819 can only drive SATA devices with this driver\n"); 1746 1747 /* Some devices use non-standard BARs */ 1748 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1749 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1750 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1751 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1752 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1753 if (pdev->device == 0xa01c) 1754 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1755 if (pdev->device == 0xa084) 1756 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1757 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) { 1758 if (pdev->device == 0x7a08) 1759 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON; 1760 } 1761 1762 /* acquire resources */ 1763 rc = pcim_enable_device(pdev); 1764 if (rc) 1765 return rc; 1766 1767 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1768 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1769 u8 map; 1770 1771 /* ICH6s share the same PCI ID for both piix and ahci 1772 * modes. Enabling ahci mode while MAP indicates 1773 * combined mode is a bad idea. Yield to ata_piix. 1774 */ 1775 pci_read_config_byte(pdev, ICH_MAP, &map); 1776 if (map & 0x3) { 1777 dev_info(&pdev->dev, 1778 "controller is in combined mode, can't enable AHCI mode\n"); 1779 return -ENODEV; 1780 } 1781 } 1782 1783 /* AHCI controllers often implement SFF compatible interface. 1784 * Grab all PCI BARs just in case. 1785 */ 1786 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1787 if (rc == -EBUSY) 1788 pcim_pin_device(pdev); 1789 if (rc) 1790 return rc; 1791 1792 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1793 if (!hpriv) 1794 return -ENOMEM; 1795 hpriv->flags |= (unsigned long)pi.private_data; 1796 1797 /* MCP65 revision A1 and A2 can't do MSI */ 1798 if (board_id == board_ahci_mcp65 && 1799 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1800 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1801 1802 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1803 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1804 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1805 1806 /* only some SB600s can do 64bit DMA */ 1807 if (ahci_sb600_enable_64bit(pdev)) 1808 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1809 1810 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1811 1812 /* detect remapped nvme devices */ 1813 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1814 1815 sysfs_add_file_to_group(&pdev->dev.kobj, 1816 &dev_attr_remapped_nvme.attr, 1817 NULL); 1818 1819 /* must set flag prior to save config in order to take effect */ 1820 if (ahci_broken_devslp(pdev)) 1821 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1822 1823#ifdef CONFIG_ARM64 1824 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI && 1825 pdev->device == 0xa235 && 1826 pdev->revision < 0x30) 1827 hpriv->flags |= AHCI_HFLAG_NO_SXS; 1828 1829 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1830 hpriv->irq_handler = ahci_thunderx_irq_handler; 1831#endif 1832 1833 /* save initial config */ 1834 ahci_pci_save_initial_config(pdev, hpriv); 1835 1836 /* prepare host */ 1837 if (hpriv->cap & HOST_CAP_NCQ) { 1838 pi.flags |= ATA_FLAG_NCQ; 1839 /* 1840 * Auto-activate optimization is supposed to be 1841 * supported on all AHCI controllers indicating NCQ 1842 * capability, but it seems to be broken on some 1843 * chipsets including NVIDIAs. 1844 */ 1845 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1846 pi.flags |= ATA_FLAG_FPDMA_AA; 1847 1848 /* 1849 * All AHCI controllers should be forward-compatible 1850 * with the new auxiliary field. This code should be 1851 * conditionalized if any buggy AHCI controllers are 1852 * encountered. 1853 */ 1854 pi.flags |= ATA_FLAG_FPDMA_AUX; 1855 } 1856 1857 if (hpriv->cap & HOST_CAP_PMP) 1858 pi.flags |= ATA_FLAG_PMP; 1859 1860 ahci_set_em_messages(hpriv, &pi); 1861 1862 if (ahci_broken_system_poweroff(pdev)) { 1863 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1864 dev_info(&pdev->dev, 1865 "quirky BIOS, skipping spindown on poweroff\n"); 1866 } 1867 1868 if (ahci_broken_lpm(pdev)) { 1869 pi.flags |= ATA_FLAG_NO_LPM; 1870 dev_warn(&pdev->dev, 1871 "BIOS update required for Link Power Management support\n"); 1872 } 1873 1874 if (ahci_broken_suspend(pdev)) { 1875 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1876 dev_warn(&pdev->dev, 1877 "BIOS update required for suspend/resume\n"); 1878 } 1879 1880 if (ahci_broken_online(pdev)) { 1881 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1882 dev_info(&pdev->dev, 1883 "online status unreliable, applying workaround\n"); 1884 } 1885 1886 1887 /* Acer SA5-271 workaround modifies private_data */ 1888 acer_sa5_271_workaround(hpriv, pdev); 1889 1890 /* CAP.NP sometimes indicate the index of the last enabled 1891 * port, at other times, that of the last possible port, so 1892 * determining the maximum port number requires looking at 1893 * both CAP.NP and port_map. 1894 */ 1895 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1896 1897 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1898 if (!host) 1899 return -ENOMEM; 1900 host->private_data = hpriv; 1901 1902 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1903 /* legacy intx interrupts */ 1904 pci_intx(pdev, 1); 1905 } 1906 hpriv->irq = pci_irq_vector(pdev, 0); 1907 1908 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1909 host->flags |= ATA_HOST_PARALLEL_SCAN; 1910 else 1911 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1912 1913 if (!(hpriv->cap & HOST_CAP_PART)) 1914 host->flags |= ATA_HOST_NO_PART; 1915 1916 if (!(hpriv->cap & HOST_CAP_SSC)) 1917 host->flags |= ATA_HOST_NO_SSC; 1918 1919 if (!(hpriv->cap2 & HOST_CAP2_SDS)) 1920 host->flags |= ATA_HOST_NO_DEVSLP; 1921 1922 if (pi.flags & ATA_FLAG_EM) 1923 ahci_reset_em(host); 1924 1925 for (i = 0; i < host->n_ports; i++) { 1926 struct ata_port *ap = host->ports[i]; 1927 1928 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1929 ata_port_pbar_desc(ap, ahci_pci_bar, 1930 0x100 + ap->port_no * 0x80, "port"); 1931 1932 /* set enclosure management message type */ 1933 if (ap->flags & ATA_FLAG_EM) 1934 ap->em_message_type = hpriv->em_msg_type; 1935 1936 ahci_update_initial_lpm_policy(ap, hpriv); 1937 1938 /* disabled/not-implemented port */ 1939 if (!(hpriv->port_map & (1 << i))) 1940 ap->ops = &ata_dummy_port_ops; 1941 } 1942 1943 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1944 ahci_p5wdh_workaround(host); 1945 1946 /* apply gtf filter quirk */ 1947 ahci_gtf_filter_workaround(host); 1948 1949 /* initialize adapter */ 1950 rc = ahci_configure_dma_masks(pdev, hpriv); 1951 if (rc) 1952 return rc; 1953 1954 rc = ahci_pci_reset_controller(host); 1955 if (rc) 1956 return rc; 1957 1958 ahci_pci_init_controller(host); 1959 ahci_pci_print_info(host); 1960 1961 pci_set_master(pdev); 1962 1963 rc = ahci_host_activate(host, &ahci_sht); 1964 if (rc) 1965 return rc; 1966 1967 pm_runtime_put_noidle(&pdev->dev); 1968 return 0; 1969} 1970 1971static void ahci_shutdown_one(struct pci_dev *pdev) 1972{ 1973 ata_pci_shutdown_one(pdev); 1974} 1975 1976static void ahci_remove_one(struct pci_dev *pdev) 1977{ 1978 sysfs_remove_file_from_group(&pdev->dev.kobj, 1979 &dev_attr_remapped_nvme.attr, 1980 NULL); 1981 pm_runtime_get_noresume(&pdev->dev); 1982 ata_pci_remove_one(pdev); 1983} 1984 1985module_pci_driver(ahci_pci_driver); 1986 1987MODULE_AUTHOR("Jeff Garzik"); 1988MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1989MODULE_LICENSE("GPL"); 1990MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1991MODULE_VERSION(DRV_VERSION); 1992