1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/clkdev.h> 12#include <linux/clk-provider.h> 13#include <linux/dmi.h> 14#include <linux/err.h> 15#include <linux/io.h> 16#include <linux/mutex.h> 17#include <linux/pci.h> 18#include <linux/platform_device.h> 19#include <linux/platform_data/x86/clk-lpss.h> 20#include <linux/platform_data/x86/pmc_atom.h> 21#include <linux/pm_domain.h> 22#include <linux/pm_runtime.h> 23#include <linux/pwm.h> 24#include <linux/pxa2xx_ssp.h> 25#include <linux/suspend.h> 26#include <linux/delay.h> 27 28#include "internal.h" 29 30#ifdef CONFIG_X86_INTEL_LPSS 31 32#include <asm/cpu_device_id.h> 33#include <asm/intel-family.h> 34#include <asm/iosf_mbi.h> 35 36#define LPSS_ADDR(desc) ((unsigned long)&desc) 37 38#define LPSS_CLK_SIZE 0x04 39#define LPSS_LTR_SIZE 0x18 40 41/* Offsets relative to LPSS_PRIVATE_OFFSET */ 42#define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 43#define LPSS_RESETS 0x04 44#define LPSS_RESETS_RESET_FUNC BIT(0) 45#define LPSS_RESETS_RESET_APB BIT(1) 46#define LPSS_GENERAL 0x08 47#define LPSS_GENERAL_LTR_MODE_SW BIT(2) 48#define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 49#define LPSS_SW_LTR 0x10 50#define LPSS_AUTO_LTR 0x14 51#define LPSS_LTR_SNOOP_REQ BIT(15) 52#define LPSS_LTR_SNOOP_MASK 0x0000FFFF 53#define LPSS_LTR_SNOOP_LAT_1US 0x800 54#define LPSS_LTR_SNOOP_LAT_32US 0xC00 55#define LPSS_LTR_SNOOP_LAT_SHIFT 5 56#define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 57#define LPSS_LTR_MAX_VAL 0x3FF 58#define LPSS_TX_INT 0x20 59#define LPSS_TX_INT_MASK BIT(1) 60 61#define LPSS_PRV_REG_COUNT 9 62 63/* LPSS Flags */ 64#define LPSS_CLK BIT(0) 65#define LPSS_CLK_GATE BIT(1) 66#define LPSS_CLK_DIVIDER BIT(2) 67#define LPSS_LTR BIT(3) 68#define LPSS_SAVE_CTX BIT(4) 69/* 70 * For some devices the DSDT AML code for another device turns off the device 71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) 72 * as ctx register values. 73 * Luckily these devices always use the same ctx register values, so we can 74 * work around this by saving the ctx registers once on activation. 75 */ 76#define LPSS_SAVE_CTX_ONCE BIT(5) 77#define LPSS_NO_D3_DELAY BIT(6) 78 79struct lpss_private_data; 80 81struct lpss_device_desc { 82 unsigned int flags; 83 const char *clk_con_id; 84 unsigned int prv_offset; 85 size_t prv_size_override; 86 const struct property_entry *properties; 87 void (*setup)(struct lpss_private_data *pdata); 88 bool resume_from_noirq; 89}; 90 91static const struct lpss_device_desc lpss_dma_desc = { 92 .flags = LPSS_CLK, 93}; 94 95struct lpss_private_data { 96 struct acpi_device *adev; 97 void __iomem *mmio_base; 98 resource_size_t mmio_size; 99 unsigned int fixed_clk_rate; 100 struct clk *clk; 101 const struct lpss_device_desc *dev_desc; 102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 103}; 104 105/* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 106static u32 pmc_atom_d3_mask = 0xfe000ffe; 107 108/* LPSS run time quirks */ 109static unsigned int lpss_quirks; 110 111/* 112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 113 * 114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 115 * it can be powered off automatically whenever the last LPSS device goes down. 116 * In case of no power any access to the DMA controller will hang the system. 117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 118 * well as on ASuS T100TA transformer. 119 * 120 * This quirk overrides power state of entire LPSS island to keep DMA powered 121 * on whenever we have at least one other device in use. 122 */ 123#define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 124 125/* UART Component Parameter Register */ 126#define LPSS_UART_CPR 0xF4 127#define LPSS_UART_CPR_AFCE BIT(4) 128 129static void lpss_uart_setup(struct lpss_private_data *pdata) 130{ 131 unsigned int offset; 132 u32 val; 133 134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 135 val = readl(pdata->mmio_base + offset); 136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 137 138 val = readl(pdata->mmio_base + LPSS_UART_CPR); 139 if (!(val & LPSS_UART_CPR_AFCE)) { 140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 141 val = readl(pdata->mmio_base + offset); 142 val |= LPSS_GENERAL_UART_RTS_OVRD; 143 writel(val, pdata->mmio_base + offset); 144 } 145} 146 147static void lpss_deassert_reset(struct lpss_private_data *pdata) 148{ 149 unsigned int offset; 150 u32 val; 151 152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 153 val = readl(pdata->mmio_base + offset); 154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 155 writel(val, pdata->mmio_base + offset); 156} 157 158/* 159 * BYT PWM used for backlight control by the i915 driver on systems without 160 * the Crystal Cove PMIC. 161 */ 162static struct pwm_lookup byt_pwm_lookup[] = { 163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 165 "pwm-lpss-platform"), 166}; 167 168static void byt_pwm_setup(struct lpss_private_data *pdata) 169{ 170 u64 uid; 171 172 /* Only call pwm_add_table for the first PWM controller */ 173 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1) 174 return; 175 176 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 177} 178 179#define LPSS_I2C_ENABLE 0x6c 180 181static void byt_i2c_setup(struct lpss_private_data *pdata) 182{ 183 acpi_handle handle = pdata->adev->handle; 184 unsigned long long shared_host = 0; 185 acpi_status status; 186 u64 uid; 187 188 /* Expected to always be successfull, but better safe then sorry */ 189 if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) { 190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 192 if (ACPI_SUCCESS(status) && shared_host) 193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 194 } 195 196 lpss_deassert_reset(pdata); 197 198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 199 pdata->fixed_clk_rate = 133000000; 200 201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 202} 203 204/* 205 * BSW PWM1 is used for backlight control by the i915 driver 206 * BSW PWM2 is used for backlight control for fixed (etched into the glass) 207 * touch controls on some models. These touch-controls have specialized 208 * drivers which know they need the "pwm_soc_lpss_2" con-id. 209 */ 210static struct pwm_lookup bsw_pwm_lookup[] = { 211 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 212 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 213 "pwm-lpss-platform"), 214 PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL, 215 "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL, 216 "pwm-lpss-platform"), 217}; 218 219static void bsw_pwm_setup(struct lpss_private_data *pdata) 220{ 221 u64 uid; 222 223 /* Only call pwm_add_table for the first PWM controller */ 224 if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1) 225 return; 226 227 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 228} 229 230static const struct property_entry lpt_spi_properties[] = { 231 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP), 232 { } 233}; 234 235static const struct lpss_device_desc lpt_spi_dev_desc = { 236 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 237 | LPSS_SAVE_CTX, 238 .prv_offset = 0x800, 239 .properties = lpt_spi_properties, 240}; 241 242static const struct lpss_device_desc lpt_i2c_dev_desc = { 243 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 244 .prv_offset = 0x800, 245}; 246 247static struct property_entry uart_properties[] = { 248 PROPERTY_ENTRY_U32("reg-io-width", 4), 249 PROPERTY_ENTRY_U32("reg-shift", 2), 250 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 251 { }, 252}; 253 254static const struct lpss_device_desc lpt_uart_dev_desc = { 255 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 256 | LPSS_SAVE_CTX, 257 .clk_con_id = "baudclk", 258 .prv_offset = 0x800, 259 .setup = lpss_uart_setup, 260 .properties = uart_properties, 261}; 262 263static const struct lpss_device_desc lpt_sdio_dev_desc = { 264 .flags = LPSS_LTR, 265 .prv_offset = 0x1000, 266 .prv_size_override = 0x1018, 267}; 268 269static const struct lpss_device_desc byt_pwm_dev_desc = { 270 .flags = LPSS_SAVE_CTX, 271 .prv_offset = 0x800, 272 .setup = byt_pwm_setup, 273}; 274 275static const struct lpss_device_desc bsw_pwm_dev_desc = { 276 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 277 .prv_offset = 0x800, 278 .setup = bsw_pwm_setup, 279 .resume_from_noirq = true, 280}; 281 282static const struct lpss_device_desc bsw_pwm2_dev_desc = { 283 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 284 .prv_offset = 0x800, 285 .resume_from_noirq = true, 286}; 287 288static const struct lpss_device_desc byt_uart_dev_desc = { 289 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 290 .clk_con_id = "baudclk", 291 .prv_offset = 0x800, 292 .setup = lpss_uart_setup, 293 .properties = uart_properties, 294}; 295 296static const struct lpss_device_desc bsw_uart_dev_desc = { 297 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 298 | LPSS_NO_D3_DELAY, 299 .clk_con_id = "baudclk", 300 .prv_offset = 0x800, 301 .setup = lpss_uart_setup, 302 .properties = uart_properties, 303}; 304 305static const struct property_entry byt_spi_properties[] = { 306 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP), 307 { } 308}; 309 310static const struct lpss_device_desc byt_spi_dev_desc = { 311 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 312 .prv_offset = 0x400, 313 .properties = byt_spi_properties, 314}; 315 316static const struct lpss_device_desc byt_sdio_dev_desc = { 317 .flags = LPSS_CLK, 318}; 319 320static const struct lpss_device_desc byt_i2c_dev_desc = { 321 .flags = LPSS_CLK | LPSS_SAVE_CTX, 322 .prv_offset = 0x800, 323 .setup = byt_i2c_setup, 324 .resume_from_noirq = true, 325}; 326 327static const struct lpss_device_desc bsw_i2c_dev_desc = { 328 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 329 .prv_offset = 0x800, 330 .setup = byt_i2c_setup, 331 .resume_from_noirq = true, 332}; 333 334static const struct property_entry bsw_spi_properties[] = { 335 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP), 336 { } 337}; 338 339static const struct lpss_device_desc bsw_spi_dev_desc = { 340 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 341 | LPSS_NO_D3_DELAY, 342 .prv_offset = 0x400, 343 .setup = lpss_deassert_reset, 344 .properties = bsw_spi_properties, 345}; 346 347static const struct x86_cpu_id lpss_cpu_ids[] = { 348 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), 349 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), 350 {} 351}; 352 353#else 354 355#define LPSS_ADDR(desc) (0UL) 356 357#endif /* CONFIG_X86_INTEL_LPSS */ 358 359static const struct acpi_device_id acpi_lpss_device_ids[] = { 360 /* Generic LPSS devices */ 361 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 362 363 /* Lynxpoint LPSS devices */ 364 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) }, 365 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) }, 366 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 367 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 368 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 369 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 370 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 371 { "INT33C7", }, 372 373 /* BayTrail LPSS devices */ 374 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 375 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 376 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 377 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 378 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 379 { "INT33B2", }, 380 { "INT33FC", }, 381 382 /* Braswell LPSS devices */ 383 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 384 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 385 { "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) }, 386 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 387 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 388 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 389 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 390 391 /* Broadwell LPSS devices */ 392 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) }, 393 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) }, 394 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 395 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 396 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 397 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 398 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 399 { "INT3437", }, 400 401 /* Wildcat Point LPSS devices */ 402 { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) }, 403 404 { } 405}; 406 407#ifdef CONFIG_X86_INTEL_LPSS 408 409/* LPSS main clock device. */ 410static struct platform_device *lpss_clk_dev; 411 412static inline void lpt_register_clock_device(void) 413{ 414 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", 415 PLATFORM_DEVID_NONE, 416 NULL, 0); 417} 418 419static int register_device_clock(struct acpi_device *adev, 420 struct lpss_private_data *pdata) 421{ 422 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 423 const char *devname = dev_name(&adev->dev); 424 struct clk *clk; 425 struct lpss_clk_data *clk_data; 426 const char *parent, *clk_name; 427 void __iomem *prv_base; 428 429 if (!lpss_clk_dev) 430 lpt_register_clock_device(); 431 432 if (IS_ERR(lpss_clk_dev)) 433 return PTR_ERR(lpss_clk_dev); 434 435 clk_data = platform_get_drvdata(lpss_clk_dev); 436 if (!clk_data) 437 return -ENODEV; 438 clk = clk_data->clk; 439 440 if (!pdata->mmio_base 441 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 442 return -ENODATA; 443 444 parent = clk_data->name; 445 prv_base = pdata->mmio_base + dev_desc->prv_offset; 446 447 if (pdata->fixed_clk_rate) { 448 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 449 pdata->fixed_clk_rate); 450 goto out; 451 } 452 453 if (dev_desc->flags & LPSS_CLK_GATE) { 454 clk = clk_register_gate(NULL, devname, parent, 0, 455 prv_base, 0, 0, NULL); 456 parent = devname; 457 } 458 459 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 460 /* Prevent division by zero */ 461 if (!readl(prv_base)) 462 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 463 464 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 465 if (!clk_name) 466 return -ENOMEM; 467 clk = clk_register_fractional_divider(NULL, clk_name, parent, 468 0, prv_base, 1, 15, 16, 15, 469 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, 470 NULL); 471 parent = clk_name; 472 473 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 474 if (!clk_name) { 475 kfree(parent); 476 return -ENOMEM; 477 } 478 clk = clk_register_gate(NULL, clk_name, parent, 479 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 480 prv_base, 31, 0, NULL); 481 kfree(parent); 482 kfree(clk_name); 483 } 484out: 485 if (IS_ERR(clk)) 486 return PTR_ERR(clk); 487 488 pdata->clk = clk; 489 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 490 return 0; 491} 492 493struct lpss_device_links { 494 const char *supplier_hid; 495 const char *supplier_uid; 496 const char *consumer_hid; 497 const char *consumer_uid; 498 u32 flags; 499 const struct dmi_system_id *dep_missing_ids; 500}; 501 502/* Please keep this list sorted alphabetically by vendor and model */ 503static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { 504 { 505 .matches = { 506 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 507 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), 508 }, 509 }, 510 {} 511}; 512 513/* 514 * The _DEP method is used to identify dependencies but instead of creating 515 * device links for every handle in _DEP, only links in the following list are 516 * created. That is necessary because, in the general case, _DEP can refer to 517 * devices that might not have drivers, or that are on different buses, or where 518 * the supplier is not enumerated until after the consumer is probed. 519 */ 520static const struct lpss_device_links lpss_device_links[] = { 521 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ 522 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 523 /* CHT iGPU depends on PMIC I2C controller */ 524 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 525 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ 526 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, 527 i2c1_dep_missing_dmi_ids}, 528 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ 529 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 530 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ 531 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 532}; 533 534static bool acpi_lpss_is_supplier(struct acpi_device *adev, 535 const struct lpss_device_links *link) 536{ 537 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 538} 539 540static bool acpi_lpss_is_consumer(struct acpi_device *adev, 541 const struct lpss_device_links *link) 542{ 543 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 544} 545 546struct hid_uid { 547 const char *hid; 548 const char *uid; 549}; 550 551static int match_hid_uid(struct device *dev, const void *data) 552{ 553 struct acpi_device *adev = ACPI_COMPANION(dev); 554 const struct hid_uid *id = data; 555 556 if (!adev) 557 return 0; 558 559 return acpi_dev_hid_uid_match(adev, id->hid, id->uid); 560} 561 562static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 563{ 564 struct device *dev; 565 566 struct hid_uid data = { 567 .hid = hid, 568 .uid = uid, 569 }; 570 571 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 572 if (dev) 573 return dev; 574 575 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 576} 577 578static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 579{ 580 struct acpi_handle_list dep_devices; 581 acpi_status status; 582 int i; 583 584 if (!acpi_has_method(adev->handle, "_DEP")) 585 return false; 586 587 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 588 &dep_devices); 589 if (ACPI_FAILURE(status)) { 590 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 591 return false; 592 } 593 594 for (i = 0; i < dep_devices.count; i++) { 595 if (dep_devices.handles[i] == handle) 596 return true; 597 } 598 599 return false; 600} 601 602static void acpi_lpss_link_consumer(struct device *dev1, 603 const struct lpss_device_links *link) 604{ 605 struct device *dev2; 606 607 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 608 if (!dev2) 609 return; 610 611 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 612 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 613 device_link_add(dev2, dev1, link->flags); 614 615 put_device(dev2); 616} 617 618static void acpi_lpss_link_supplier(struct device *dev1, 619 const struct lpss_device_links *link) 620{ 621 struct device *dev2; 622 623 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 624 if (!dev2) 625 return; 626 627 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 628 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 629 device_link_add(dev1, dev2, link->flags); 630 631 put_device(dev2); 632} 633 634static void acpi_lpss_create_device_links(struct acpi_device *adev, 635 struct platform_device *pdev) 636{ 637 int i; 638 639 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 640 const struct lpss_device_links *link = &lpss_device_links[i]; 641 642 if (acpi_lpss_is_supplier(adev, link)) 643 acpi_lpss_link_consumer(&pdev->dev, link); 644 645 if (acpi_lpss_is_consumer(adev, link)) 646 acpi_lpss_link_supplier(&pdev->dev, link); 647 } 648} 649 650static int acpi_lpss_create_device(struct acpi_device *adev, 651 const struct acpi_device_id *id) 652{ 653 const struct lpss_device_desc *dev_desc; 654 struct lpss_private_data *pdata; 655 struct resource_entry *rentry; 656 struct list_head resource_list; 657 struct platform_device *pdev; 658 int ret; 659 660 dev_desc = (const struct lpss_device_desc *)id->driver_data; 661 if (!dev_desc) { 662 pdev = acpi_create_platform_device(adev, NULL); 663 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 664 } 665 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 666 if (!pdata) 667 return -ENOMEM; 668 669 INIT_LIST_HEAD(&resource_list); 670 ret = acpi_dev_get_memory_resources(adev, &resource_list); 671 if (ret < 0) 672 goto err_out; 673 674 rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node); 675 if (rentry) { 676 if (dev_desc->prv_size_override) 677 pdata->mmio_size = dev_desc->prv_size_override; 678 else 679 pdata->mmio_size = resource_size(rentry->res); 680 pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size); 681 } 682 683 acpi_dev_free_resource_list(&resource_list); 684 685 if (!pdata->mmio_base) { 686 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 687 adev->pnp.type.platform_id = 0; 688 goto out_free; 689 } 690 691 pdata->adev = adev; 692 pdata->dev_desc = dev_desc; 693 694 if (dev_desc->setup) 695 dev_desc->setup(pdata); 696 697 if (dev_desc->flags & LPSS_CLK) { 698 ret = register_device_clock(adev, pdata); 699 if (ret) 700 goto out_free; 701 } 702 703 /* 704 * This works around a known issue in ACPI tables where LPSS devices 705 * have _PS0 and _PS3 without _PSC (and no power resources), so 706 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 707 */ 708 acpi_device_fix_up_power(adev); 709 710 adev->driver_data = pdata; 711 pdev = acpi_create_platform_device(adev, dev_desc->properties); 712 if (IS_ERR_OR_NULL(pdev)) { 713 adev->driver_data = NULL; 714 ret = PTR_ERR(pdev); 715 goto err_out; 716 } 717 718 acpi_lpss_create_device_links(adev, pdev); 719 return 1; 720 721out_free: 722 /* Skip the device, but continue the namespace scan */ 723 ret = 0; 724err_out: 725 kfree(pdata); 726 return ret; 727} 728 729static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 730{ 731 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 732} 733 734static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 735 unsigned int reg) 736{ 737 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 738} 739 740static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 741{ 742 struct acpi_device *adev = ACPI_COMPANION(dev); 743 struct lpss_private_data *pdata; 744 unsigned long flags; 745 int ret; 746 747 if (WARN_ON(!adev)) 748 return -ENODEV; 749 750 spin_lock_irqsave(&dev->power.lock, flags); 751 if (pm_runtime_suspended(dev)) { 752 ret = -EAGAIN; 753 goto out; 754 } 755 pdata = acpi_driver_data(adev); 756 if (WARN_ON(!pdata || !pdata->mmio_base)) { 757 ret = -ENODEV; 758 goto out; 759 } 760 *val = __lpss_reg_read(pdata, reg); 761 ret = 0; 762 763 out: 764 spin_unlock_irqrestore(&dev->power.lock, flags); 765 return ret; 766} 767 768static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 769 char *buf) 770{ 771 u32 ltr_value = 0; 772 unsigned int reg; 773 int ret; 774 775 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 776 ret = lpss_reg_read(dev, reg, <r_value); 777 if (ret) 778 return ret; 779 780 return sysfs_emit(buf, "%08x\n", ltr_value); 781} 782 783static ssize_t lpss_ltr_mode_show(struct device *dev, 784 struct device_attribute *attr, char *buf) 785{ 786 u32 ltr_mode = 0; 787 char *outstr; 788 int ret; 789 790 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 791 if (ret) 792 return ret; 793 794 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 795 return sprintf(buf, "%s\n", outstr); 796} 797 798static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 799static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 800static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 801 802static struct attribute *lpss_attrs[] = { 803 &dev_attr_auto_ltr.attr, 804 &dev_attr_sw_ltr.attr, 805 &dev_attr_ltr_mode.attr, 806 NULL, 807}; 808 809static const struct attribute_group lpss_attr_group = { 810 .attrs = lpss_attrs, 811 .name = "lpss_ltr", 812}; 813 814static void acpi_lpss_set_ltr(struct device *dev, s32 val) 815{ 816 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 817 u32 ltr_mode, ltr_val; 818 819 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 820 if (val < 0) { 821 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 822 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 823 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 824 } 825 return; 826 } 827 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 828 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 829 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 830 val = LPSS_LTR_MAX_VAL; 831 } else if (val > LPSS_LTR_MAX_VAL) { 832 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 833 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 834 } else { 835 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 836 } 837 ltr_val |= val; 838 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 839 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 840 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 841 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 842 } 843} 844 845#ifdef CONFIG_PM 846/** 847 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 848 * @dev: LPSS device 849 * @pdata: pointer to the private data of the LPSS device 850 * 851 * Most LPSS devices have private registers which may loose their context when 852 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 853 * prv_reg_ctx array. 854 */ 855static void acpi_lpss_save_ctx(struct device *dev, 856 struct lpss_private_data *pdata) 857{ 858 unsigned int i; 859 860 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 861 unsigned long offset = i * sizeof(u32); 862 863 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 864 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 865 pdata->prv_reg_ctx[i], offset); 866 } 867} 868 869/** 870 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 871 * @dev: LPSS device 872 * @pdata: pointer to the private data of the LPSS device 873 * 874 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 875 */ 876static void acpi_lpss_restore_ctx(struct device *dev, 877 struct lpss_private_data *pdata) 878{ 879 unsigned int i; 880 881 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 882 unsigned long offset = i * sizeof(u32); 883 884 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 885 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 886 pdata->prv_reg_ctx[i], offset); 887 } 888} 889 890static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 891{ 892 /* 893 * The following delay is needed or the subsequent write operations may 894 * fail. The LPSS devices are actually PCI devices and the PCI spec 895 * expects 10ms delay before the device can be accessed after D3 to D0 896 * transition. However some platforms like BSW does not need this delay. 897 */ 898 unsigned int delay = 10; /* default 10ms delay */ 899 900 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 901 delay = 0; 902 903 msleep(delay); 904} 905 906static int acpi_lpss_activate(struct device *dev) 907{ 908 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 909 int ret; 910 911 ret = acpi_dev_resume(dev); 912 if (ret) 913 return ret; 914 915 acpi_lpss_d3_to_d0_delay(pdata); 916 917 /* 918 * This is called only on ->probe() stage where a device is either in 919 * known state defined by BIOS or most likely powered off. Due to this 920 * we have to deassert reset line to be sure that ->probe() will 921 * recognize the device. 922 */ 923 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 924 lpss_deassert_reset(pdata); 925 926#ifdef CONFIG_PM 927 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) 928 acpi_lpss_save_ctx(dev, pdata); 929#endif 930 931 return 0; 932} 933 934static void acpi_lpss_dismiss(struct device *dev) 935{ 936 acpi_dev_suspend(dev, false); 937} 938 939/* IOSF SB for LPSS island */ 940#define LPSS_IOSF_UNIT_LPIOEP 0xA0 941#define LPSS_IOSF_UNIT_LPIO1 0xAB 942#define LPSS_IOSF_UNIT_LPIO2 0xAC 943 944#define LPSS_IOSF_PMCSR 0x84 945#define LPSS_PMCSR_D0 0 946#define LPSS_PMCSR_D3hot 3 947#define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 948 949#define LPSS_IOSF_GPIODEF0 0x154 950#define LPSS_GPIODEF0_DMA1_D3 BIT(2) 951#define LPSS_GPIODEF0_DMA2_D3 BIT(3) 952#define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 953#define LPSS_GPIODEF0_DMA_LLP BIT(13) 954 955static DEFINE_MUTEX(lpss_iosf_mutex); 956static bool lpss_iosf_d3_entered = true; 957 958static void lpss_iosf_enter_d3_state(void) 959{ 960 u32 value1 = 0; 961 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 962 u32 value2 = LPSS_PMCSR_D3hot; 963 u32 mask2 = LPSS_PMCSR_Dx_MASK; 964 /* 965 * PMC provides an information about actual status of the LPSS devices. 966 * Here we read the values related to LPSS power island, i.e. LPSS 967 * devices, excluding both LPSS DMA controllers, along with SCC domain. 968 */ 969 u32 func_dis, d3_sts_0, pmc_status; 970 int ret; 971 972 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 973 if (ret) 974 return; 975 976 mutex_lock(&lpss_iosf_mutex); 977 978 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 979 if (ret) 980 goto exit; 981 982 /* 983 * Get the status of entire LPSS power island per device basis. 984 * Shutdown both LPSS DMA controllers if and only if all other devices 985 * are already in D3hot. 986 */ 987 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 988 if (pmc_status) 989 goto exit; 990 991 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 992 LPSS_IOSF_PMCSR, value2, mask2); 993 994 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 995 LPSS_IOSF_PMCSR, value2, mask2); 996 997 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 998 LPSS_IOSF_GPIODEF0, value1, mask1); 999 1000 lpss_iosf_d3_entered = true; 1001 1002exit: 1003 mutex_unlock(&lpss_iosf_mutex); 1004} 1005 1006static void lpss_iosf_exit_d3_state(void) 1007{ 1008 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 1009 LPSS_GPIODEF0_DMA_LLP; 1010 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 1011 u32 value2 = LPSS_PMCSR_D0; 1012 u32 mask2 = LPSS_PMCSR_Dx_MASK; 1013 1014 mutex_lock(&lpss_iosf_mutex); 1015 1016 if (!lpss_iosf_d3_entered) 1017 goto exit; 1018 1019 lpss_iosf_d3_entered = false; 1020 1021 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 1022 LPSS_IOSF_GPIODEF0, value1, mask1); 1023 1024 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 1025 LPSS_IOSF_PMCSR, value2, mask2); 1026 1027 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 1028 LPSS_IOSF_PMCSR, value2, mask2); 1029 1030exit: 1031 mutex_unlock(&lpss_iosf_mutex); 1032} 1033 1034static int acpi_lpss_suspend(struct device *dev, bool wakeup) 1035{ 1036 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1037 int ret; 1038 1039 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1040 acpi_lpss_save_ctx(dev, pdata); 1041 1042 ret = acpi_dev_suspend(dev, wakeup); 1043 1044 /* 1045 * This call must be last in the sequence, otherwise PMC will return 1046 * wrong status for devices being about to be powered off. See 1047 * lpss_iosf_enter_d3_state() for further information. 1048 */ 1049 if (acpi_target_system_state() == ACPI_STATE_S0 && 1050 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1051 lpss_iosf_enter_d3_state(); 1052 1053 return ret; 1054} 1055 1056static int acpi_lpss_resume(struct device *dev) 1057{ 1058 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1059 int ret; 1060 1061 /* 1062 * This call is kept first to be in symmetry with 1063 * acpi_lpss_runtime_suspend() one. 1064 */ 1065 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1066 lpss_iosf_exit_d3_state(); 1067 1068 ret = acpi_dev_resume(dev); 1069 if (ret) 1070 return ret; 1071 1072 acpi_lpss_d3_to_d0_delay(pdata); 1073 1074 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 1075 acpi_lpss_restore_ctx(dev, pdata); 1076 1077 return 0; 1078} 1079 1080#ifdef CONFIG_PM_SLEEP 1081static int acpi_lpss_do_suspend_late(struct device *dev) 1082{ 1083 int ret; 1084 1085 if (dev_pm_skip_suspend(dev)) 1086 return 0; 1087 1088 ret = pm_generic_suspend_late(dev); 1089 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1090} 1091 1092static int acpi_lpss_suspend_late(struct device *dev) 1093{ 1094 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1095 1096 if (pdata->dev_desc->resume_from_noirq) 1097 return 0; 1098 1099 return acpi_lpss_do_suspend_late(dev); 1100} 1101 1102static int acpi_lpss_suspend_noirq(struct device *dev) 1103{ 1104 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1105 int ret; 1106 1107 if (pdata->dev_desc->resume_from_noirq) { 1108 /* 1109 * The driver's ->suspend_late callback will be invoked by 1110 * acpi_lpss_do_suspend_late(), with the assumption that the 1111 * driver really wanted to run that code in ->suspend_noirq, but 1112 * it could not run after acpi_dev_suspend() and the driver 1113 * expected the latter to be called in the "late" phase. 1114 */ 1115 ret = acpi_lpss_do_suspend_late(dev); 1116 if (ret) 1117 return ret; 1118 } 1119 1120 return acpi_subsys_suspend_noirq(dev); 1121} 1122 1123static int acpi_lpss_do_resume_early(struct device *dev) 1124{ 1125 int ret = acpi_lpss_resume(dev); 1126 1127 return ret ? ret : pm_generic_resume_early(dev); 1128} 1129 1130static int acpi_lpss_resume_early(struct device *dev) 1131{ 1132 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1133 1134 if (pdata->dev_desc->resume_from_noirq) 1135 return 0; 1136 1137 if (dev_pm_skip_resume(dev)) 1138 return 0; 1139 1140 return acpi_lpss_do_resume_early(dev); 1141} 1142 1143static int acpi_lpss_resume_noirq(struct device *dev) 1144{ 1145 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1146 int ret; 1147 1148 /* Follow acpi_subsys_resume_noirq(). */ 1149 if (dev_pm_skip_resume(dev)) 1150 return 0; 1151 1152 ret = pm_generic_resume_noirq(dev); 1153 if (ret) 1154 return ret; 1155 1156 if (!pdata->dev_desc->resume_from_noirq) 1157 return 0; 1158 1159 /* 1160 * The driver's ->resume_early callback will be invoked by 1161 * acpi_lpss_do_resume_early(), with the assumption that the driver 1162 * really wanted to run that code in ->resume_noirq, but it could not 1163 * run before acpi_dev_resume() and the driver expected the latter to be 1164 * called in the "early" phase. 1165 */ 1166 return acpi_lpss_do_resume_early(dev); 1167} 1168 1169static int acpi_lpss_do_restore_early(struct device *dev) 1170{ 1171 int ret = acpi_lpss_resume(dev); 1172 1173 return ret ? ret : pm_generic_restore_early(dev); 1174} 1175 1176static int acpi_lpss_restore_early(struct device *dev) 1177{ 1178 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1179 1180 if (pdata->dev_desc->resume_from_noirq) 1181 return 0; 1182 1183 return acpi_lpss_do_restore_early(dev); 1184} 1185 1186static int acpi_lpss_restore_noirq(struct device *dev) 1187{ 1188 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1189 int ret; 1190 1191 ret = pm_generic_restore_noirq(dev); 1192 if (ret) 1193 return ret; 1194 1195 if (!pdata->dev_desc->resume_from_noirq) 1196 return 0; 1197 1198 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1199 return acpi_lpss_do_restore_early(dev); 1200} 1201 1202static int acpi_lpss_do_poweroff_late(struct device *dev) 1203{ 1204 int ret = pm_generic_poweroff_late(dev); 1205 1206 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1207} 1208 1209static int acpi_lpss_poweroff_late(struct device *dev) 1210{ 1211 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1212 1213 if (dev_pm_skip_suspend(dev)) 1214 return 0; 1215 1216 if (pdata->dev_desc->resume_from_noirq) 1217 return 0; 1218 1219 return acpi_lpss_do_poweroff_late(dev); 1220} 1221 1222static int acpi_lpss_poweroff_noirq(struct device *dev) 1223{ 1224 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1225 1226 if (dev_pm_skip_suspend(dev)) 1227 return 0; 1228 1229 if (pdata->dev_desc->resume_from_noirq) { 1230 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1231 int ret = acpi_lpss_do_poweroff_late(dev); 1232 1233 if (ret) 1234 return ret; 1235 } 1236 1237 return pm_generic_poweroff_noirq(dev); 1238} 1239#endif /* CONFIG_PM_SLEEP */ 1240 1241static int acpi_lpss_runtime_suspend(struct device *dev) 1242{ 1243 int ret = pm_generic_runtime_suspend(dev); 1244 1245 return ret ? ret : acpi_lpss_suspend(dev, true); 1246} 1247 1248static int acpi_lpss_runtime_resume(struct device *dev) 1249{ 1250 int ret = acpi_lpss_resume(dev); 1251 1252 return ret ? ret : pm_generic_runtime_resume(dev); 1253} 1254#endif /* CONFIG_PM */ 1255 1256static struct dev_pm_domain acpi_lpss_pm_domain = { 1257#ifdef CONFIG_PM 1258 .activate = acpi_lpss_activate, 1259 .dismiss = acpi_lpss_dismiss, 1260#endif 1261 .ops = { 1262#ifdef CONFIG_PM 1263#ifdef CONFIG_PM_SLEEP 1264 .prepare = acpi_subsys_prepare, 1265 .complete = acpi_subsys_complete, 1266 .suspend = acpi_subsys_suspend, 1267 .suspend_late = acpi_lpss_suspend_late, 1268 .suspend_noirq = acpi_lpss_suspend_noirq, 1269 .resume_noirq = acpi_lpss_resume_noirq, 1270 .resume_early = acpi_lpss_resume_early, 1271 .freeze = acpi_subsys_freeze, 1272 .poweroff = acpi_subsys_poweroff, 1273 .poweroff_late = acpi_lpss_poweroff_late, 1274 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1275 .restore_noirq = acpi_lpss_restore_noirq, 1276 .restore_early = acpi_lpss_restore_early, 1277#endif 1278 .runtime_suspend = acpi_lpss_runtime_suspend, 1279 .runtime_resume = acpi_lpss_runtime_resume, 1280#endif 1281 }, 1282}; 1283 1284static int acpi_lpss_platform_notify(struct notifier_block *nb, 1285 unsigned long action, void *data) 1286{ 1287 struct platform_device *pdev = to_platform_device(data); 1288 struct lpss_private_data *pdata; 1289 struct acpi_device *adev; 1290 const struct acpi_device_id *id; 1291 1292 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1293 if (!id || !id->driver_data) 1294 return 0; 1295 1296 adev = ACPI_COMPANION(&pdev->dev); 1297 if (!adev) 1298 return 0; 1299 1300 pdata = acpi_driver_data(adev); 1301 if (!pdata) 1302 return 0; 1303 1304 if (pdata->mmio_base && 1305 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1306 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1307 return 0; 1308 } 1309 1310 switch (action) { 1311 case BUS_NOTIFY_BIND_DRIVER: 1312 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1313 break; 1314 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1315 case BUS_NOTIFY_UNBOUND_DRIVER: 1316 dev_pm_domain_set(&pdev->dev, NULL); 1317 break; 1318 case BUS_NOTIFY_ADD_DEVICE: 1319 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1320 if (pdata->dev_desc->flags & LPSS_LTR) 1321 return sysfs_create_group(&pdev->dev.kobj, 1322 &lpss_attr_group); 1323 break; 1324 case BUS_NOTIFY_DEL_DEVICE: 1325 if (pdata->dev_desc->flags & LPSS_LTR) 1326 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1327 dev_pm_domain_set(&pdev->dev, NULL); 1328 break; 1329 default: 1330 break; 1331 } 1332 1333 return 0; 1334} 1335 1336static struct notifier_block acpi_lpss_nb = { 1337 .notifier_call = acpi_lpss_platform_notify, 1338}; 1339 1340static void acpi_lpss_bind(struct device *dev) 1341{ 1342 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1343 1344 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1345 return; 1346 1347 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1348 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1349 else 1350 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1351} 1352 1353static void acpi_lpss_unbind(struct device *dev) 1354{ 1355 dev->power.set_latency_tolerance = NULL; 1356} 1357 1358static struct acpi_scan_handler lpss_handler = { 1359 .ids = acpi_lpss_device_ids, 1360 .attach = acpi_lpss_create_device, 1361 .bind = acpi_lpss_bind, 1362 .unbind = acpi_lpss_unbind, 1363}; 1364 1365void __init acpi_lpss_init(void) 1366{ 1367 const struct x86_cpu_id *id; 1368 int ret; 1369 1370 ret = lpss_atom_clk_init(); 1371 if (ret) 1372 return; 1373 1374 id = x86_match_cpu(lpss_cpu_ids); 1375 if (id) 1376 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1377 1378 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1379 acpi_scan_add_handler(&lpss_handler); 1380} 1381 1382#else 1383 1384static struct acpi_scan_handler lpss_handler = { 1385 .ids = acpi_lpss_device_ids, 1386}; 1387 1388void __init acpi_lpss_init(void) 1389{ 1390 acpi_scan_add_handler(&lpss_handler); 1391} 1392 1393#endif /* CONFIG_X86_INTEL_LPSS */ 1394