1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6#include <linux/genalloc.h> 7#include <linux/highmem.h> 8#include <linux/kthread.h> 9#include <linux/wait.h> 10 11#include "ivpu_drv.h" 12#include "ivpu_gem.h" 13#include "ivpu_hw.h" 14#include "ivpu_hw_reg_io.h" 15#include "ivpu_ipc.h" 16#include "ivpu_jsm_msg.h" 17#include "ivpu_pm.h" 18 19#define IPC_MAX_RX_MSG 128 20#define IS_KTHREAD() (get_current()->flags & PF_KTHREAD) 21 22struct ivpu_ipc_tx_buf { 23 struct ivpu_ipc_hdr ipc; 24 struct vpu_jsm_msg jsm; 25}; 26 27struct ivpu_ipc_rx_msg { 28 struct list_head link; 29 struct ivpu_ipc_hdr *ipc_hdr; 30 struct vpu_jsm_msg *jsm_msg; 31}; 32 33static void ivpu_ipc_msg_dump(struct ivpu_device *vdev, char *c, 34 struct ivpu_ipc_hdr *ipc_hdr, u32 vpu_addr) 35{ 36 ivpu_dbg(vdev, IPC, 37 "%s: vpu:0x%x (data_addr:0x%08x, data_size:0x%x, channel:0x%x, src_node:0x%x, dst_node:0x%x, status:0x%x)", 38 c, vpu_addr, ipc_hdr->data_addr, ipc_hdr->data_size, ipc_hdr->channel, 39 ipc_hdr->src_node, ipc_hdr->dst_node, ipc_hdr->status); 40} 41 42static void ivpu_jsm_msg_dump(struct ivpu_device *vdev, char *c, 43 struct vpu_jsm_msg *jsm_msg, u32 vpu_addr) 44{ 45 u32 *payload = (u32 *)&jsm_msg->payload; 46 47 ivpu_dbg(vdev, JSM, 48 "%s: vpu:0x%08x (type:0x%x, status:0x%x, id: 0x%x, result: 0x%x, payload:0x%x 0x%x 0x%x 0x%x 0x%x)\n", 49 c, vpu_addr, jsm_msg->type, jsm_msg->status, jsm_msg->request_id, jsm_msg->result, 50 payload[0], payload[1], payload[2], payload[3], payload[4]); 51} 52 53static void 54ivpu_ipc_rx_mark_free(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr, 55 struct vpu_jsm_msg *jsm_msg) 56{ 57 ipc_hdr->status = IVPU_IPC_HDR_FREE; 58 if (jsm_msg) 59 jsm_msg->status = VPU_JSM_MSG_FREE; 60 wmb(); /* Flush WC buffers for message statuses */ 61} 62 63static void ivpu_ipc_mem_fini(struct ivpu_device *vdev) 64{ 65 struct ivpu_ipc_info *ipc = vdev->ipc; 66 67 ivpu_bo_free_internal(ipc->mem_rx); 68 ivpu_bo_free_internal(ipc->mem_tx); 69} 70 71static int 72ivpu_ipc_tx_prepare(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 73 struct vpu_jsm_msg *req) 74{ 75 struct ivpu_ipc_info *ipc = vdev->ipc; 76 struct ivpu_ipc_tx_buf *tx_buf; 77 u32 tx_buf_vpu_addr; 78 u32 jsm_vpu_addr; 79 80 tx_buf_vpu_addr = gen_pool_alloc(ipc->mm_tx, sizeof(*tx_buf)); 81 if (!tx_buf_vpu_addr) { 82 ivpu_err(vdev, "Failed to reserve IPC buffer, size %ld\n", 83 sizeof(*tx_buf)); 84 return -ENOMEM; 85 } 86 87 tx_buf = ivpu_to_cpu_addr(ipc->mem_tx, tx_buf_vpu_addr); 88 if (drm_WARN_ON(&vdev->drm, !tx_buf)) { 89 gen_pool_free(ipc->mm_tx, tx_buf_vpu_addr, sizeof(*tx_buf)); 90 return -EIO; 91 } 92 93 jsm_vpu_addr = tx_buf_vpu_addr + offsetof(struct ivpu_ipc_tx_buf, jsm); 94 95 if (tx_buf->ipc.status != IVPU_IPC_HDR_FREE) 96 ivpu_warn(vdev, "IPC message vpu:0x%x not released by firmware\n", 97 tx_buf_vpu_addr); 98 99 if (tx_buf->jsm.status != VPU_JSM_MSG_FREE) 100 ivpu_warn(vdev, "JSM message vpu:0x%x not released by firmware\n", 101 jsm_vpu_addr); 102 103 memset(tx_buf, 0, sizeof(*tx_buf)); 104 tx_buf->ipc.data_addr = jsm_vpu_addr; 105 /* TODO: Set data_size to actual JSM message size, not union of all messages */ 106 tx_buf->ipc.data_size = sizeof(*req); 107 tx_buf->ipc.channel = cons->channel; 108 tx_buf->ipc.src_node = 0; 109 tx_buf->ipc.dst_node = 1; 110 tx_buf->ipc.status = IVPU_IPC_HDR_ALLOCATED; 111 tx_buf->jsm.type = req->type; 112 tx_buf->jsm.status = VPU_JSM_MSG_ALLOCATED; 113 tx_buf->jsm.payload = req->payload; 114 115 req->request_id = atomic_inc_return(&ipc->request_id); 116 tx_buf->jsm.request_id = req->request_id; 117 cons->request_id = req->request_id; 118 wmb(); /* Flush WC buffers for IPC, JSM msgs */ 119 120 cons->tx_vpu_addr = tx_buf_vpu_addr; 121 122 ivpu_jsm_msg_dump(vdev, "TX", &tx_buf->jsm, jsm_vpu_addr); 123 ivpu_ipc_msg_dump(vdev, "TX", &tx_buf->ipc, tx_buf_vpu_addr); 124 125 return 0; 126} 127 128static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr) 129{ 130 struct ivpu_ipc_info *ipc = vdev->ipc; 131 132 if (vpu_addr) 133 gen_pool_free(ipc->mm_tx, vpu_addr, sizeof(struct ivpu_ipc_tx_buf)); 134} 135 136static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr) 137{ 138 ivpu_hw_reg_ipc_tx_set(vdev, vpu_addr); 139} 140 141void 142ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, u32 channel) 143{ 144 struct ivpu_ipc_info *ipc = vdev->ipc; 145 146 INIT_LIST_HEAD(&cons->link); 147 cons->channel = channel; 148 cons->tx_vpu_addr = 0; 149 cons->request_id = 0; 150 spin_lock_init(&cons->rx_msg_lock); 151 INIT_LIST_HEAD(&cons->rx_msg_list); 152 init_waitqueue_head(&cons->rx_msg_wq); 153 154 spin_lock_irq(&ipc->cons_list_lock); 155 list_add_tail(&cons->link, &ipc->cons_list); 156 spin_unlock_irq(&ipc->cons_list_lock); 157} 158 159void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons) 160{ 161 struct ivpu_ipc_info *ipc = vdev->ipc; 162 struct ivpu_ipc_rx_msg *rx_msg, *r; 163 164 spin_lock_irq(&ipc->cons_list_lock); 165 list_del(&cons->link); 166 spin_unlock_irq(&ipc->cons_list_lock); 167 168 spin_lock_irq(&cons->rx_msg_lock); 169 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link) { 170 list_del(&rx_msg->link); 171 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 172 atomic_dec(&ipc->rx_msg_count); 173 kfree(rx_msg); 174 } 175 spin_unlock_irq(&cons->rx_msg_lock); 176 177 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr); 178} 179 180static int 181ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req) 182{ 183 struct ivpu_ipc_info *ipc = vdev->ipc; 184 int ret; 185 186 mutex_lock(&ipc->lock); 187 188 if (!ipc->on) { 189 ret = -EAGAIN; 190 goto unlock; 191 } 192 193 ret = ivpu_ipc_tx_prepare(vdev, cons, req); 194 if (ret) 195 goto unlock; 196 197 ivpu_ipc_tx(vdev, cons->tx_vpu_addr); 198 199unlock: 200 mutex_unlock(&ipc->lock); 201 return ret; 202} 203 204int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 205 struct ivpu_ipc_hdr *ipc_buf, 206 struct vpu_jsm_msg *ipc_payload, unsigned long timeout_ms) 207{ 208 struct ivpu_ipc_info *ipc = vdev->ipc; 209 struct ivpu_ipc_rx_msg *rx_msg; 210 int wait_ret, ret = 0; 211 212 wait_ret = wait_event_timeout(cons->rx_msg_wq, 213 (IS_KTHREAD() && kthread_should_stop()) || 214 !list_empty(&cons->rx_msg_list), 215 msecs_to_jiffies(timeout_ms)); 216 217 if (IS_KTHREAD() && kthread_should_stop()) 218 return -EINTR; 219 220 if (wait_ret == 0) 221 return -ETIMEDOUT; 222 223 spin_lock_irq(&cons->rx_msg_lock); 224 rx_msg = list_first_entry_or_null(&cons->rx_msg_list, struct ivpu_ipc_rx_msg, link); 225 if (!rx_msg) { 226 spin_unlock_irq(&cons->rx_msg_lock); 227 return -EAGAIN; 228 } 229 list_del(&rx_msg->link); 230 spin_unlock_irq(&cons->rx_msg_lock); 231 232 if (ipc_buf) 233 memcpy(ipc_buf, rx_msg->ipc_hdr, sizeof(*ipc_buf)); 234 if (rx_msg->jsm_msg) { 235 u32 size = min_t(int, rx_msg->ipc_hdr->data_size, sizeof(*ipc_payload)); 236 237 if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) { 238 ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result); 239 ret = -EBADMSG; 240 } 241 242 if (ipc_payload) 243 memcpy(ipc_payload, rx_msg->jsm_msg, size); 244 } 245 246 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 247 atomic_dec(&ipc->rx_msg_count); 248 kfree(rx_msg); 249 250 return ret; 251} 252 253static int 254ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 255 enum vpu_ipc_msg_type expected_resp_type, 256 struct vpu_jsm_msg *resp, u32 channel, 257 unsigned long timeout_ms) 258{ 259 struct ivpu_ipc_consumer cons; 260 int ret; 261 262 ivpu_ipc_consumer_add(vdev, &cons, channel); 263 264 ret = ivpu_ipc_send(vdev, &cons, req); 265 if (ret) { 266 ivpu_warn(vdev, "IPC send failed: %d\n", ret); 267 goto consumer_del; 268 } 269 270 ret = ivpu_ipc_receive(vdev, &cons, NULL, resp, timeout_ms); 271 if (ret) { 272 ivpu_warn(vdev, "IPC receive failed: type 0x%x, ret %d\n", req->type, ret); 273 goto consumer_del; 274 } 275 276 if (resp->type != expected_resp_type) { 277 ivpu_warn(vdev, "Invalid JSM response type: 0x%x\n", resp->type); 278 ret = -EBADE; 279 } 280 281consumer_del: 282 ivpu_ipc_consumer_del(vdev, &cons); 283 return ret; 284} 285 286int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 287 enum vpu_ipc_msg_type expected_resp_type, 288 struct vpu_jsm_msg *resp, u32 channel, 289 unsigned long timeout_ms) 290{ 291 struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB }; 292 struct vpu_jsm_msg hb_resp; 293 int ret, hb_ret; 294 295 ret = ivpu_rpm_get(vdev); 296 if (ret < 0) 297 return ret; 298 299 ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp_type, resp, 300 channel, timeout_ms); 301 if (ret != -ETIMEDOUT) 302 goto rpm_put; 303 304 hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, 305 &hb_resp, VPU_IPC_CHAN_ASYNC_CMD, 306 vdev->timeout.jsm); 307 if (hb_ret == -ETIMEDOUT) { 308 ivpu_hw_diagnose_failure(vdev); 309 ivpu_pm_schedule_recovery(vdev); 310 } 311 312rpm_put: 313 ivpu_rpm_put(vdev); 314 return ret; 315} 316 317static bool 318ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 319 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 320{ 321 if (cons->channel != ipc_hdr->channel) 322 return false; 323 324 if (!jsm_msg || jsm_msg->request_id == cons->request_id) 325 return true; 326 327 return false; 328} 329 330static void 331ivpu_ipc_dispatch(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 332 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 333{ 334 struct ivpu_ipc_info *ipc = vdev->ipc; 335 struct ivpu_ipc_rx_msg *rx_msg; 336 unsigned long flags; 337 338 lockdep_assert_held(&ipc->cons_list_lock); 339 340 rx_msg = kzalloc(sizeof(*rx_msg), GFP_ATOMIC); 341 if (!rx_msg) { 342 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 343 return; 344 } 345 346 atomic_inc(&ipc->rx_msg_count); 347 348 rx_msg->ipc_hdr = ipc_hdr; 349 rx_msg->jsm_msg = jsm_msg; 350 351 spin_lock_irqsave(&cons->rx_msg_lock, flags); 352 list_add_tail(&rx_msg->link, &cons->rx_msg_list); 353 spin_unlock_irqrestore(&cons->rx_msg_lock, flags); 354 355 wake_up(&cons->rx_msg_wq); 356} 357 358int ivpu_ipc_irq_handler(struct ivpu_device *vdev) 359{ 360 struct ivpu_ipc_info *ipc = vdev->ipc; 361 struct ivpu_ipc_consumer *cons; 362 struct ivpu_ipc_hdr *ipc_hdr; 363 struct vpu_jsm_msg *jsm_msg; 364 unsigned long flags; 365 bool dispatched; 366 u32 vpu_addr; 367 368 /* 369 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt. 370 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated. 371 */ 372 while (ivpu_hw_reg_ipc_rx_count_get(vdev)) { 373 vpu_addr = ivpu_hw_reg_ipc_rx_addr_get(vdev); 374 if (vpu_addr == REG_IO_ERROR) { 375 ivpu_err(vdev, "Failed to read IPC rx addr register\n"); 376 return -EIO; 377 } 378 379 ipc_hdr = ivpu_to_cpu_addr(ipc->mem_rx, vpu_addr); 380 if (!ipc_hdr) { 381 ivpu_warn(vdev, "IPC msg 0x%x out of range\n", vpu_addr); 382 continue; 383 } 384 ivpu_ipc_msg_dump(vdev, "RX", ipc_hdr, vpu_addr); 385 386 jsm_msg = NULL; 387 if (ipc_hdr->channel != IVPU_IPC_CHAN_BOOT_MSG) { 388 jsm_msg = ivpu_to_cpu_addr(ipc->mem_rx, ipc_hdr->data_addr); 389 if (!jsm_msg) { 390 ivpu_warn(vdev, "JSM msg 0x%x out of range\n", ipc_hdr->data_addr); 391 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, NULL); 392 continue; 393 } 394 ivpu_jsm_msg_dump(vdev, "RX", jsm_msg, ipc_hdr->data_addr); 395 } 396 397 if (atomic_read(&ipc->rx_msg_count) > IPC_MAX_RX_MSG) { 398 ivpu_warn(vdev, "IPC RX msg dropped, msg count %d\n", IPC_MAX_RX_MSG); 399 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 400 continue; 401 } 402 403 dispatched = false; 404 spin_lock_irqsave(&ipc->cons_list_lock, flags); 405 list_for_each_entry(cons, &ipc->cons_list, link) { 406 if (ivpu_ipc_match_consumer(vdev, cons, ipc_hdr, jsm_msg)) { 407 ivpu_ipc_dispatch(vdev, cons, ipc_hdr, jsm_msg); 408 dispatched = true; 409 break; 410 } 411 } 412 spin_unlock_irqrestore(&ipc->cons_list_lock, flags); 413 414 if (!dispatched) { 415 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); 416 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 417 } 418 } 419 420 return 0; 421} 422 423int ivpu_ipc_init(struct ivpu_device *vdev) 424{ 425 struct ivpu_ipc_info *ipc = vdev->ipc; 426 int ret = -ENOMEM; 427 428 ipc->mem_tx = ivpu_bo_alloc_internal(vdev, 0, SZ_16K, DRM_IVPU_BO_WC); 429 if (!ipc->mem_tx) 430 return ret; 431 432 ipc->mem_rx = ivpu_bo_alloc_internal(vdev, 0, SZ_16K, DRM_IVPU_BO_WC); 433 if (!ipc->mem_rx) 434 goto err_free_tx; 435 436 ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT), 437 -1, "TX_IPC_JSM"); 438 if (IS_ERR(ipc->mm_tx)) { 439 ret = PTR_ERR(ipc->mm_tx); 440 ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx); 441 goto err_free_rx; 442 } 443 444 ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ipc->mem_tx->base.size, -1); 445 if (ret) { 446 ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret); 447 goto err_free_rx; 448 } 449 450 INIT_LIST_HEAD(&ipc->cons_list); 451 spin_lock_init(&ipc->cons_list_lock); 452 drmm_mutex_init(&vdev->drm, &ipc->lock); 453 454 ivpu_ipc_reset(vdev); 455 return 0; 456 457err_free_rx: 458 ivpu_bo_free_internal(ipc->mem_rx); 459err_free_tx: 460 ivpu_bo_free_internal(ipc->mem_tx); 461 return ret; 462} 463 464void ivpu_ipc_fini(struct ivpu_device *vdev) 465{ 466 ivpu_ipc_mem_fini(vdev); 467} 468 469void ivpu_ipc_enable(struct ivpu_device *vdev) 470{ 471 struct ivpu_ipc_info *ipc = vdev->ipc; 472 473 mutex_lock(&ipc->lock); 474 ipc->on = true; 475 mutex_unlock(&ipc->lock); 476} 477 478void ivpu_ipc_disable(struct ivpu_device *vdev) 479{ 480 struct ivpu_ipc_info *ipc = vdev->ipc; 481 struct ivpu_ipc_consumer *cons, *c; 482 unsigned long flags; 483 484 mutex_lock(&ipc->lock); 485 ipc->on = false; 486 mutex_unlock(&ipc->lock); 487 488 spin_lock_irqsave(&ipc->cons_list_lock, flags); 489 list_for_each_entry_safe(cons, c, &ipc->cons_list, link) 490 wake_up(&cons->rx_msg_wq); 491 spin_unlock_irqrestore(&ipc->cons_list_lock, flags); 492} 493 494void ivpu_ipc_reset(struct ivpu_device *vdev) 495{ 496 struct ivpu_ipc_info *ipc = vdev->ipc; 497 498 mutex_lock(&ipc->lock); 499 500 memset(ipc->mem_tx->kvaddr, 0, ipc->mem_tx->base.size); 501 memset(ipc->mem_rx->kvaddr, 0, ipc->mem_rx->base.size); 502 wmb(); /* Flush WC buffers for TX and RX rings */ 503 504 mutex_unlock(&ipc->lock); 505} 506