1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#ifndef __IVPU_DRV_H__
7#define __IVPU_DRV_H__
8
9#include <drm/drm_device.h>
10#include <drm/drm_drv.h>
11#include <drm/drm_managed.h>
12#include <drm/drm_mm.h>
13#include <drm/drm_print.h>
14
15#include <linux/pci.h>
16#include <linux/xarray.h>
17#include <uapi/drm/ivpu_accel.h>
18
19#include "ivpu_mmu_context.h"
20
21#define DRIVER_NAME "intel_vpu"
22#define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
23#define DRIVER_DATE "20230117"
24
25#define PCI_DEVICE_ID_MTL   0x7d1d
26#define PCI_DEVICE_ID_ARL   0xad1d
27#define PCI_DEVICE_ID_LNL   0x643e
28
29#define IVPU_HW_37XX	37
30#define IVPU_HW_40XX	40
31
32#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
33/* SSID 1 is used by the VPU to represent invalid context */
34#define IVPU_USER_CONTEXT_MIN_SSID   2
35#define IVPU_USER_CONTEXT_MAX_SSID   (IVPU_USER_CONTEXT_MIN_SSID + 63)
36
37#define IVPU_NUM_ENGINES	     2
38
39#define IVPU_PLATFORM_SILICON 0
40#define IVPU_PLATFORM_SIMICS  2
41#define IVPU_PLATFORM_FPGA    3
42#define IVPU_PLATFORM_INVALID 8
43
44#define IVPU_DBG_REG	 BIT(0)
45#define IVPU_DBG_IRQ	 BIT(1)
46#define IVPU_DBG_MMU	 BIT(2)
47#define IVPU_DBG_FILE	 BIT(3)
48#define IVPU_DBG_MISC	 BIT(4)
49#define IVPU_DBG_FW_BOOT BIT(5)
50#define IVPU_DBG_PM	 BIT(6)
51#define IVPU_DBG_IPC	 BIT(7)
52#define IVPU_DBG_BO	 BIT(8)
53#define IVPU_DBG_JOB	 BIT(9)
54#define IVPU_DBG_JSM	 BIT(10)
55#define IVPU_DBG_KREF	 BIT(11)
56#define IVPU_DBG_RPM	 BIT(12)
57
58#define ivpu_err(vdev, fmt, ...) \
59	drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
60
61#define ivpu_err_ratelimited(vdev, fmt, ...) \
62	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
63
64#define ivpu_warn(vdev, fmt, ...) \
65	drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
66
67#define ivpu_warn_ratelimited(vdev, fmt, ...) \
68	drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
69
70#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
71
72#define ivpu_dbg(vdev, type, fmt, args...) do {                                \
73	if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask))                         \
74		dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args);          \
75} while (0)
76
77#define IVPU_WA(wa_name) (vdev->wa.wa_name)
78
79#define IVPU_PRINT_WA(wa_name) do {					\
80	if (IVPU_WA(wa_name))						\
81		ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n");	\
82} while (0)
83
84struct ivpu_wa_table {
85	bool punit_disabled;
86	bool clear_runtime_mem;
87	bool d3hot_after_power_off;
88	bool interrupt_clear_with_0;
89	bool disable_clock_relinquish;
90};
91
92struct ivpu_hw_info;
93struct ivpu_mmu_info;
94struct ivpu_fw_info;
95struct ivpu_ipc_info;
96struct ivpu_pm_info;
97
98struct ivpu_device {
99	struct drm_device drm;
100	void __iomem *regb;
101	void __iomem *regv;
102	u32 platform;
103	u32 irq;
104
105	struct ivpu_wa_table wa;
106	struct ivpu_hw_info *hw;
107	struct ivpu_mmu_info *mmu;
108	struct ivpu_fw_info *fw;
109	struct ivpu_ipc_info *ipc;
110	struct ivpu_pm_info *pm;
111
112	struct ivpu_mmu_context gctx;
113	struct xarray context_xa;
114	struct xa_limit context_xa_limit;
115
116	struct xarray submitted_jobs_xa;
117	struct task_struct *job_done_thread;
118
119	atomic64_t unique_id_counter;
120
121	struct {
122		int boot;
123		int jsm;
124		int tdr;
125		int reschedule_suspend;
126	} timeout;
127};
128
129/*
130 * file_priv has its own refcount (ref) that allows user space to close the fd
131 * without blocking even if VPU is still processing some jobs.
132 */
133struct ivpu_file_priv {
134	struct kref ref;
135	struct ivpu_device *vdev;
136	struct mutex lock; /* Protects cmdq */
137	struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
138	struct ivpu_mmu_context ctx;
139	u32 priority;
140	bool has_mmu_faults;
141};
142
143extern int ivpu_dbg_mask;
144extern u8 ivpu_pll_min_ratio;
145extern u8 ivpu_pll_max_ratio;
146extern bool ivpu_disable_mmu_cont_pages;
147
148#define IVPU_TEST_MODE_DISABLED  0
149#define IVPU_TEST_MODE_FW_TEST   1
150#define IVPU_TEST_MODE_NULL_HW   2
151extern int ivpu_test_mode;
152
153struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
154struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
155void ivpu_file_priv_put(struct ivpu_file_priv **link);
156
157int ivpu_boot(struct ivpu_device *vdev);
158int ivpu_shutdown(struct ivpu_device *vdev);
159void ivpu_prepare_for_reset(struct ivpu_device *vdev);
160
161static inline u8 ivpu_revision(struct ivpu_device *vdev)
162{
163	return to_pci_dev(vdev->drm.dev)->revision;
164}
165
166static inline u16 ivpu_device_id(struct ivpu_device *vdev)
167{
168	return to_pci_dev(vdev->drm.dev)->device;
169}
170
171static inline int ivpu_hw_gen(struct ivpu_device *vdev)
172{
173	switch (ivpu_device_id(vdev)) {
174	case PCI_DEVICE_ID_MTL:
175	case PCI_DEVICE_ID_ARL:
176		return IVPU_HW_37XX;
177	case PCI_DEVICE_ID_LNL:
178		return IVPU_HW_40XX;
179	default:
180		ivpu_err(vdev, "Unknown VPU device\n");
181		return 0;
182	}
183}
184
185static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
186{
187	return container_of(dev, struct ivpu_device, drm);
188}
189
190static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
191{
192	struct xa_limit ctx_limit = vdev->context_xa_limit;
193
194	return (ctx_limit.max - ctx_limit.min + 1);
195}
196
197static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
198{
199	WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
200	return vdev->platform;
201}
202
203static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
204{
205	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
206}
207
208static inline bool ivpu_is_simics(struct ivpu_device *vdev)
209{
210	return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
211}
212
213static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
214{
215	return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
216}
217
218#endif /* __IVPU_DRV_H__ */
219