1// SPDX-License-Identifier: GPL-2.0 2 3/* 4 * Copyright 2016-2022 HabanaLabs, Ltd. 5 * All Rights Reserved. 6 */ 7 8#include "habanalabs.h" 9 10#include <linux/slab.h> 11 12/** 13 * struct hl_eqe_work - This structure is used to schedule work of EQ 14 * entry and cpucp_reset event 15 * 16 * @eq_work: workqueue object to run when EQ entry is received 17 * @hdev: pointer to device structure 18 * @eq_entry: copy of the EQ entry 19 */ 20struct hl_eqe_work { 21 struct work_struct eq_work; 22 struct hl_device *hdev; 23 struct hl_eq_entry eq_entry; 24}; 25 26/** 27 * hl_cq_inc_ptr - increment ci or pi of cq 28 * 29 * @ptr: the current ci or pi value of the completion queue 30 * 31 * Increment ptr by 1. If it reaches the number of completion queue 32 * entries, set it to 0 33 */ 34inline u32 hl_cq_inc_ptr(u32 ptr) 35{ 36 ptr++; 37 if (unlikely(ptr == HL_CQ_LENGTH)) 38 ptr = 0; 39 return ptr; 40} 41 42/** 43 * hl_eq_inc_ptr - increment ci of eq 44 * 45 * @ptr: the current ci value of the event queue 46 * 47 * Increment ptr by 1. If it reaches the number of event queue 48 * entries, set it to 0 49 */ 50static inline u32 hl_eq_inc_ptr(u32 ptr) 51{ 52 ptr++; 53 if (unlikely(ptr == HL_EQ_LENGTH)) 54 ptr = 0; 55 return ptr; 56} 57 58static void irq_handle_eqe(struct work_struct *work) 59{ 60 struct hl_eqe_work *eqe_work = container_of(work, struct hl_eqe_work, 61 eq_work); 62 struct hl_device *hdev = eqe_work->hdev; 63 64 hdev->asic_funcs->handle_eqe(hdev, &eqe_work->eq_entry); 65 66 kfree(eqe_work); 67} 68 69/** 70 * job_finish - queue job finish work 71 * 72 * @hdev: pointer to device structure 73 * @cs_seq: command submission sequence 74 * @cq: completion queue 75 * @timestamp: interrupt timestamp 76 * 77 */ 78static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq, ktime_t timestamp) 79{ 80 struct hl_hw_queue *queue; 81 struct hl_cs_job *job; 82 83 queue = &hdev->kernel_queues[cq->hw_queue_id]; 84 job = queue->shadow_queue[hl_pi_2_offset(cs_seq)]; 85 job->timestamp = timestamp; 86 queue_work(hdev->cq_wq[cq->cq_idx], &job->finish_work); 87 88 atomic_inc(&queue->ci); 89} 90 91/** 92 * cs_finish - queue all cs jobs finish work 93 * 94 * @hdev: pointer to device structure 95 * @cs_seq: command submission sequence 96 * @timestamp: interrupt timestamp 97 * 98 */ 99static void cs_finish(struct hl_device *hdev, u16 cs_seq, ktime_t timestamp) 100{ 101 struct asic_fixed_properties *prop = &hdev->asic_prop; 102 struct hl_hw_queue *queue; 103 struct hl_cs *cs; 104 struct hl_cs_job *job; 105 106 cs = hdev->shadow_cs_queue[cs_seq & (prop->max_pending_cs - 1)]; 107 if (!cs) { 108 dev_warn(hdev->dev, 109 "No pointer to CS in shadow array at index %d\n", 110 cs_seq); 111 return; 112 } 113 114 list_for_each_entry(job, &cs->job_list, cs_node) { 115 queue = &hdev->kernel_queues[job->hw_queue_id]; 116 atomic_inc(&queue->ci); 117 } 118 119 cs->completion_timestamp = timestamp; 120 queue_work(hdev->cs_cmplt_wq, &cs->finish_work); 121} 122 123/** 124 * hl_irq_handler_cq - irq handler for completion queue 125 * 126 * @irq: irq number 127 * @arg: pointer to completion queue structure 128 * 129 */ 130irqreturn_t hl_irq_handler_cq(int irq, void *arg) 131{ 132 struct hl_cq *cq = arg; 133 struct hl_device *hdev = cq->hdev; 134 bool shadow_index_valid, entry_ready; 135 u16 shadow_index; 136 struct hl_cq_entry *cq_entry, *cq_base; 137 ktime_t timestamp = ktime_get(); 138 139 if (hdev->disabled) { 140 dev_dbg(hdev->dev, 141 "Device disabled but received IRQ %d for CQ %d\n", 142 irq, cq->hw_queue_id); 143 return IRQ_HANDLED; 144 } 145 146 cq_base = cq->kernel_address; 147 148 while (1) { 149 cq_entry = (struct hl_cq_entry *) &cq_base[cq->ci]; 150 151 entry_ready = !!FIELD_GET(CQ_ENTRY_READY_MASK, 152 le32_to_cpu(cq_entry->data)); 153 if (!entry_ready) 154 break; 155 156 /* Make sure we read CQ entry contents after we've 157 * checked the ownership bit. 158 */ 159 dma_rmb(); 160 161 shadow_index_valid = 162 !!FIELD_GET(CQ_ENTRY_SHADOW_INDEX_VALID_MASK, 163 le32_to_cpu(cq_entry->data)); 164 165 shadow_index = FIELD_GET(CQ_ENTRY_SHADOW_INDEX_MASK, 166 le32_to_cpu(cq_entry->data)); 167 168 /* 169 * CQ interrupt handler has 2 modes of operation: 170 * 1. Interrupt per CS completion: (Single CQ for all queues) 171 * CQ entry represents a completed CS 172 * 173 * 2. Interrupt per CS job completion in queue: (CQ per queue) 174 * CQ entry represents a completed job in a certain queue 175 */ 176 if (shadow_index_valid && !hdev->disabled) { 177 if (hdev->asic_prop.completion_mode == 178 HL_COMPLETION_MODE_CS) 179 cs_finish(hdev, shadow_index, timestamp); 180 else 181 job_finish(hdev, shadow_index, cq, timestamp); 182 } 183 184 /* Clear CQ entry ready bit */ 185 cq_entry->data = cpu_to_le32(le32_to_cpu(cq_entry->data) & 186 ~CQ_ENTRY_READY_MASK); 187 188 cq->ci = hl_cq_inc_ptr(cq->ci); 189 190 /* Increment free slots */ 191 atomic_inc(&cq->free_slots_cnt); 192 } 193 194 return IRQ_HANDLED; 195} 196 197/* 198 * hl_ts_free_objects - handler of the free objects workqueue. 199 * This function should put refcount to objects that the registration node 200 * took refcount to them. 201 * @work: workqueue object pointer 202 */ 203static void hl_ts_free_objects(struct work_struct *work) 204{ 205 struct timestamp_reg_work_obj *job = 206 container_of(work, struct timestamp_reg_work_obj, free_obj); 207 struct timestamp_reg_free_node *free_obj, *temp_free_obj; 208 struct list_head *free_list_head = job->free_obj_head; 209 struct hl_device *hdev = job->hdev; 210 211 list_for_each_entry_safe(free_obj, temp_free_obj, free_list_head, free_objects_node) { 212 dev_dbg(hdev->dev, "About to put refcount to buf (%p) cq_cb(%p)\n", 213 free_obj->buf, 214 free_obj->cq_cb); 215 216 hl_mmap_mem_buf_put(free_obj->buf); 217 hl_cb_put(free_obj->cq_cb); 218 kfree(free_obj); 219 } 220 221 kfree(free_list_head); 222 kfree(job); 223} 224 225/* 226 * This function called with spin_lock of wait_list_lock taken 227 * This function will set timestamp and delete the registration node from the 228 * wait_list_lock. 229 * and since we're protected with spin_lock here, so we cannot just put the refcount 230 * for the objects here, since the release function may be called and it's also a long 231 * logic (which might sleep also) that cannot be handled in irq context. 232 * so here we'll be filling a list with nodes of "put" jobs and then will send this 233 * list to a dedicated workqueue to do the actual put. 234 */ 235static int handle_registration_node(struct hl_device *hdev, struct hl_user_pending_interrupt *pend, 236 struct list_head **free_list, ktime_t now) 237{ 238 struct timestamp_reg_free_node *free_node; 239 u64 timestamp; 240 241 if (!(*free_list)) { 242 /* Alloc/Init the timestamp registration free objects list */ 243 *free_list = kmalloc(sizeof(struct list_head), GFP_ATOMIC); 244 if (!(*free_list)) 245 return -ENOMEM; 246 247 INIT_LIST_HEAD(*free_list); 248 } 249 250 free_node = kmalloc(sizeof(*free_node), GFP_ATOMIC); 251 if (!free_node) 252 return -ENOMEM; 253 254 timestamp = ktime_to_ns(now); 255 256 *pend->ts_reg_info.timestamp_kernel_addr = timestamp; 257 258 dev_dbg(hdev->dev, "Timestamp is set to ts cb address (%p), ts: 0x%llx\n", 259 pend->ts_reg_info.timestamp_kernel_addr, 260 *(u64 *)pend->ts_reg_info.timestamp_kernel_addr); 261 262 list_del(&pend->wait_list_node); 263 264 /* Mark kernel CB node as free */ 265 pend->ts_reg_info.in_use = 0; 266 267 /* Putting the refcount for ts_buff and cq_cb objects will be handled 268 * in workqueue context, just add job to free_list. 269 */ 270 free_node->buf = pend->ts_reg_info.buf; 271 free_node->cq_cb = pend->ts_reg_info.cq_cb; 272 list_add(&free_node->free_objects_node, *free_list); 273 274 return 0; 275} 276 277static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interrupt *intr) 278{ 279 struct hl_user_pending_interrupt *pend, *temp_pend; 280 struct list_head *ts_reg_free_list_head = NULL; 281 struct timestamp_reg_work_obj *job; 282 bool reg_node_handle_fail = false; 283 int rc; 284 285 /* For registration nodes: 286 * As part of handling the registration nodes, we should put refcount to 287 * some objects. the problem is that we cannot do that under spinlock 288 * or in irq handler context at all (since release functions are long and 289 * might sleep), so we will need to handle that part in workqueue context. 290 * To avoid handling kmalloc failure which compels us rolling back actions 291 * and move nodes hanged on the free list back to the interrupt wait list 292 * we always alloc the job of the WQ at the beginning. 293 */ 294 job = kmalloc(sizeof(*job), GFP_ATOMIC); 295 if (!job) 296 return; 297 298 spin_lock(&intr->wait_list_lock); 299 list_for_each_entry_safe(pend, temp_pend, &intr->wait_list_head, wait_list_node) { 300 if ((pend->cq_kernel_addr && *(pend->cq_kernel_addr) >= pend->cq_target_value) || 301 !pend->cq_kernel_addr) { 302 if (pend->ts_reg_info.buf) { 303 if (!reg_node_handle_fail) { 304 rc = handle_registration_node(hdev, pend, 305 &ts_reg_free_list_head, intr->timestamp); 306 if (rc) 307 reg_node_handle_fail = true; 308 } 309 } else { 310 /* Handle wait target value node */ 311 pend->fence.timestamp = intr->timestamp; 312 complete_all(&pend->fence.completion); 313 } 314 } 315 } 316 spin_unlock(&intr->wait_list_lock); 317 318 if (ts_reg_free_list_head) { 319 INIT_WORK(&job->free_obj, hl_ts_free_objects); 320 job->free_obj_head = ts_reg_free_list_head; 321 job->hdev = hdev; 322 queue_work(hdev->ts_free_obj_wq, &job->free_obj); 323 } else { 324 kfree(job); 325 } 326} 327 328static void handle_tpc_interrupt(struct hl_device *hdev) 329{ 330 u64 event_mask; 331 u32 flags; 332 333 event_mask = HL_NOTIFIER_EVENT_TPC_ASSERT | 334 HL_NOTIFIER_EVENT_USER_ENGINE_ERR | 335 HL_NOTIFIER_EVENT_DEVICE_RESET; 336 337 flags = HL_DRV_RESET_DELAY; 338 339 dev_err_ratelimited(hdev->dev, "Received TPC assert\n"); 340 hl_device_cond_reset(hdev, flags, event_mask); 341} 342 343static void handle_unexpected_user_interrupt(struct hl_device *hdev) 344{ 345 dev_err_ratelimited(hdev->dev, "Received unexpected user error interrupt\n"); 346} 347 348/** 349 * hl_irq_handler_user_interrupt - irq handler for user interrupts 350 * 351 * @irq: irq number 352 * @arg: pointer to user interrupt structure 353 * 354 */ 355irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg) 356{ 357 struct hl_user_interrupt *user_int = arg; 358 359 user_int->timestamp = ktime_get(); 360 361 return IRQ_WAKE_THREAD; 362} 363 364/** 365 * hl_irq_user_interrupt_thread_handler - irq thread handler for user interrupts. 366 * This function is invoked by threaded irq mechanism 367 * 368 * @irq: irq number 369 * @arg: pointer to user interrupt structure 370 * 371 */ 372irqreturn_t hl_irq_user_interrupt_thread_handler(int irq, void *arg) 373{ 374 struct hl_user_interrupt *user_int = arg; 375 struct hl_device *hdev = user_int->hdev; 376 377 switch (user_int->type) { 378 case HL_USR_INTERRUPT_CQ: 379 handle_user_interrupt(hdev, &hdev->common_user_cq_interrupt); 380 381 /* Handle user cq interrupt registered on this specific irq */ 382 handle_user_interrupt(hdev, user_int); 383 break; 384 case HL_USR_INTERRUPT_DECODER: 385 handle_user_interrupt(hdev, &hdev->common_decoder_interrupt); 386 387 /* Handle decoder interrupt registered on this specific irq */ 388 handle_user_interrupt(hdev, user_int); 389 break; 390 case HL_USR_INTERRUPT_TPC: 391 handle_tpc_interrupt(hdev); 392 break; 393 case HL_USR_INTERRUPT_UNEXPECTED: 394 handle_unexpected_user_interrupt(hdev); 395 break; 396 default: 397 break; 398 } 399 400 return IRQ_HANDLED; 401} 402 403/** 404 * hl_irq_handler_eq - irq handler for event queue 405 * 406 * @irq: irq number 407 * @arg: pointer to event queue structure 408 * 409 */ 410irqreturn_t hl_irq_handler_eq(int irq, void *arg) 411{ 412 struct hl_eq *eq = arg; 413 struct hl_device *hdev = eq->hdev; 414 struct hl_eq_entry *eq_entry; 415 struct hl_eq_entry *eq_base; 416 struct hl_eqe_work *handle_eqe_work; 417 bool entry_ready; 418 u32 cur_eqe, ctl; 419 u16 cur_eqe_index, event_type; 420 421 eq_base = eq->kernel_address; 422 423 while (1) { 424 cur_eqe = le32_to_cpu(eq_base[eq->ci].hdr.ctl); 425 entry_ready = !!FIELD_GET(EQ_CTL_READY_MASK, cur_eqe); 426 427 if (!entry_ready) 428 break; 429 430 cur_eqe_index = FIELD_GET(EQ_CTL_INDEX_MASK, cur_eqe); 431 if ((hdev->event_queue.check_eqe_index) && 432 (((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK) != cur_eqe_index)) { 433 dev_err(hdev->dev, 434 "EQE %#x in queue is ready but index does not match %d!=%d", 435 cur_eqe, 436 ((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK), 437 cur_eqe_index); 438 break; 439 } 440 441 eq->prev_eqe_index++; 442 443 eq_entry = &eq_base[eq->ci]; 444 445 /* 446 * Make sure we read EQ entry contents after we've 447 * checked the ownership bit. 448 */ 449 dma_rmb(); 450 451 if (hdev->disabled && !hdev->reset_info.in_compute_reset) { 452 ctl = le32_to_cpu(eq_entry->hdr.ctl); 453 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) >> EQ_CTL_EVENT_TYPE_SHIFT); 454 dev_warn(hdev->dev, 455 "Device disabled but received an EQ event (%u)\n", event_type); 456 goto skip_irq; 457 } 458 459 handle_eqe_work = kmalloc(sizeof(*handle_eqe_work), GFP_ATOMIC); 460 if (handle_eqe_work) { 461 INIT_WORK(&handle_eqe_work->eq_work, irq_handle_eqe); 462 handle_eqe_work->hdev = hdev; 463 464 memcpy(&handle_eqe_work->eq_entry, eq_entry, 465 sizeof(*eq_entry)); 466 467 queue_work(hdev->eq_wq, &handle_eqe_work->eq_work); 468 } 469skip_irq: 470 /* Clear EQ entry ready bit */ 471 eq_entry->hdr.ctl = 472 cpu_to_le32(le32_to_cpu(eq_entry->hdr.ctl) & 473 ~EQ_CTL_READY_MASK); 474 475 eq->ci = hl_eq_inc_ptr(eq->ci); 476 477 hdev->asic_funcs->update_eq_ci(hdev, eq->ci); 478 } 479 480 return IRQ_HANDLED; 481} 482 483/** 484 * hl_irq_handler_dec_abnrm - Decoder error interrupt handler 485 * @irq: IRQ number 486 * @arg: pointer to decoder structure. 487 */ 488irqreturn_t hl_irq_handler_dec_abnrm(int irq, void *arg) 489{ 490 struct hl_dec *dec = arg; 491 492 schedule_work(&dec->abnrm_intr_work); 493 494 return IRQ_HANDLED; 495} 496 497/** 498 * hl_cq_init - main initialization function for an cq object 499 * 500 * @hdev: pointer to device structure 501 * @q: pointer to cq structure 502 * @hw_queue_id: The H/W queue ID this completion queue belongs to 503 * HL_INVALID_QUEUE if cq is not attached to any specific queue 504 * 505 * Allocate dma-able memory for the completion queue and initialize fields 506 * Returns 0 on success 507 */ 508int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id) 509{ 510 void *p; 511 512 p = hl_asic_dma_alloc_coherent(hdev, HL_CQ_SIZE_IN_BYTES, &q->bus_address, 513 GFP_KERNEL | __GFP_ZERO); 514 if (!p) 515 return -ENOMEM; 516 517 q->hdev = hdev; 518 q->kernel_address = p; 519 q->hw_queue_id = hw_queue_id; 520 q->ci = 0; 521 q->pi = 0; 522 523 atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH); 524 525 return 0; 526} 527 528/** 529 * hl_cq_fini - destroy completion queue 530 * 531 * @hdev: pointer to device structure 532 * @q: pointer to cq structure 533 * 534 * Free the completion queue memory 535 */ 536void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q) 537{ 538 hl_asic_dma_free_coherent(hdev, HL_CQ_SIZE_IN_BYTES, q->kernel_address, q->bus_address); 539} 540 541void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q) 542{ 543 q->ci = 0; 544 q->pi = 0; 545 546 atomic_set(&q->free_slots_cnt, HL_CQ_LENGTH); 547 548 /* 549 * It's not enough to just reset the PI/CI because the H/W may have 550 * written valid completion entries before it was halted and therefore 551 * we need to clean the actual queues so we won't process old entries 552 * when the device is operational again 553 */ 554 555 memset(q->kernel_address, 0, HL_CQ_SIZE_IN_BYTES); 556} 557 558/** 559 * hl_eq_init - main initialization function for an event queue object 560 * 561 * @hdev: pointer to device structure 562 * @q: pointer to eq structure 563 * 564 * Allocate dma-able memory for the event queue and initialize fields 565 * Returns 0 on success 566 */ 567int hl_eq_init(struct hl_device *hdev, struct hl_eq *q) 568{ 569 void *p; 570 571 p = hl_cpu_accessible_dma_pool_alloc(hdev, HL_EQ_SIZE_IN_BYTES, &q->bus_address); 572 if (!p) 573 return -ENOMEM; 574 575 q->hdev = hdev; 576 q->kernel_address = p; 577 q->ci = 0; 578 q->prev_eqe_index = 0; 579 580 return 0; 581} 582 583/** 584 * hl_eq_fini - destroy event queue 585 * 586 * @hdev: pointer to device structure 587 * @q: pointer to eq structure 588 * 589 * Free the event queue memory 590 */ 591void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q) 592{ 593 flush_workqueue(hdev->eq_wq); 594 595 hl_cpu_accessible_dma_pool_free(hdev, HL_EQ_SIZE_IN_BYTES, q->kernel_address); 596} 597 598void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q) 599{ 600 q->ci = 0; 601 q->prev_eqe_index = 0; 602 603 /* 604 * It's not enough to just reset the PI/CI because the H/W may have 605 * written valid completion entries before it was halted and therefore 606 * we need to clean the actual queues so we won't process old entries 607 * when the device is operational again 608 */ 609 610 memset(q->kernel_address, 0, HL_EQ_SIZE_IN_BYTES); 611} 612