162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * This header file describes this specific Xtensa processor's TIE extensions 362306a36Sopenharmony_ci * that extend basic Xtensa core functionality. It is customized to this 462306a36Sopenharmony_ci * Xtensa processor configuration. 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 762306a36Sopenharmony_ci * License. See the file "COPYING" in the main directory of this archive 862306a36Sopenharmony_ci * for more details. 962306a36Sopenharmony_ci * 1062306a36Sopenharmony_ci * Copyright (C) 1999-2007 Tensilica Inc. 1162306a36Sopenharmony_ci */ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#ifndef _XTENSA_CORE_TIE_H 1462306a36Sopenharmony_ci#define _XTENSA_CORE_TIE_H 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci#define XCHAL_CP_NUM 0 /* number of coprocessors */ 1762306a36Sopenharmony_ci#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ 1862306a36Sopenharmony_ci#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 1962306a36Sopenharmony_ci#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci/* Filler info for unassigned coprocessors, to simplify arrays etc: */ 2262306a36Sopenharmony_ci#define XCHAL_NCP_SA_SIZE 0 2362306a36Sopenharmony_ci#define XCHAL_NCP_SA_ALIGN 1 2462306a36Sopenharmony_ci#define XCHAL_CP0_SA_SIZE 0 2562306a36Sopenharmony_ci#define XCHAL_CP0_SA_ALIGN 1 2662306a36Sopenharmony_ci#define XCHAL_CP1_SA_SIZE 0 2762306a36Sopenharmony_ci#define XCHAL_CP1_SA_ALIGN 1 2862306a36Sopenharmony_ci#define XCHAL_CP2_SA_SIZE 0 2962306a36Sopenharmony_ci#define XCHAL_CP2_SA_ALIGN 1 3062306a36Sopenharmony_ci#define XCHAL_CP3_SA_SIZE 0 3162306a36Sopenharmony_ci#define XCHAL_CP3_SA_ALIGN 1 3262306a36Sopenharmony_ci#define XCHAL_CP4_SA_SIZE 0 3362306a36Sopenharmony_ci#define XCHAL_CP4_SA_ALIGN 1 3462306a36Sopenharmony_ci#define XCHAL_CP5_SA_SIZE 0 3562306a36Sopenharmony_ci#define XCHAL_CP5_SA_ALIGN 1 3662306a36Sopenharmony_ci#define XCHAL_CP6_SA_SIZE 0 3762306a36Sopenharmony_ci#define XCHAL_CP6_SA_ALIGN 1 3862306a36Sopenharmony_ci#define XCHAL_CP7_SA_SIZE 0 3962306a36Sopenharmony_ci#define XCHAL_CP7_SA_ALIGN 1 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci/* Save area for non-coprocessor optional and custom (TIE) state: */ 4262306a36Sopenharmony_ci#define XCHAL_NCP_SA_SIZE 0 4362306a36Sopenharmony_ci#define XCHAL_NCP_SA_ALIGN 1 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci/* Total save area for optional and custom state (NCP + CPn): */ 4662306a36Sopenharmony_ci#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */ 4762306a36Sopenharmony_ci#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */ 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_ci#define XCHAL_NCP_SA_NUM 0 5062306a36Sopenharmony_ci#define XCHAL_NCP_SA_LIST(s) 5162306a36Sopenharmony_ci#define XCHAL_CP0_SA_NUM 0 5262306a36Sopenharmony_ci#define XCHAL_CP0_SA_LIST(s) 5362306a36Sopenharmony_ci#define XCHAL_CP1_SA_NUM 0 5462306a36Sopenharmony_ci#define XCHAL_CP1_SA_LIST(s) 5562306a36Sopenharmony_ci#define XCHAL_CP2_SA_NUM 0 5662306a36Sopenharmony_ci#define XCHAL_CP2_SA_LIST(s) 5762306a36Sopenharmony_ci#define XCHAL_CP3_SA_NUM 0 5862306a36Sopenharmony_ci#define XCHAL_CP3_SA_LIST(s) 5962306a36Sopenharmony_ci#define XCHAL_CP4_SA_NUM 0 6062306a36Sopenharmony_ci#define XCHAL_CP4_SA_LIST(s) 6162306a36Sopenharmony_ci#define XCHAL_CP5_SA_NUM 0 6262306a36Sopenharmony_ci#define XCHAL_CP5_SA_LIST(s) 6362306a36Sopenharmony_ci#define XCHAL_CP6_SA_NUM 0 6462306a36Sopenharmony_ci#define XCHAL_CP6_SA_LIST(s) 6562306a36Sopenharmony_ci#define XCHAL_CP7_SA_NUM 0 6662306a36Sopenharmony_ci#define XCHAL_CP7_SA_LIST(s) 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ci/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 6962306a36Sopenharmony_ci#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ci#endif /*_XTENSA_CORE_TIE_H*/ 7262306a36Sopenharmony_ci 73