162306a36Sopenharmony_ci/*
262306a36Sopenharmony_ci * include/asm-xtensa/pci-bridge.h
362306a36Sopenharmony_ci *
462306a36Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General
562306a36Sopenharmony_ci * Public License.  See the file "COPYING" in the main directory of
662306a36Sopenharmony_ci * this archive for more details.
762306a36Sopenharmony_ci *
862306a36Sopenharmony_ci * Copyright (C) 2005 Tensilica Inc.
962306a36Sopenharmony_ci */
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#ifndef _XTENSA_PCI_BRIDGE_H
1262306a36Sopenharmony_ci#define _XTENSA_PCI_BRIDGE_H
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_cistruct device_node;
1562306a36Sopenharmony_cistruct pci_controller;
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ci/*
1862306a36Sopenharmony_ci * pciauto_bus_scan() enumerates the pci space.
1962306a36Sopenharmony_ci */
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ciextern int pciauto_bus_scan(struct pci_controller *, int);
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_cistruct pci_space {
2462306a36Sopenharmony_ci	unsigned long start;
2562306a36Sopenharmony_ci	unsigned long end;
2662306a36Sopenharmony_ci	unsigned long base;
2762306a36Sopenharmony_ci};
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci/*
3062306a36Sopenharmony_ci * Structure of a PCI controller (host bridge)
3162306a36Sopenharmony_ci */
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_cistruct pci_controller {
3462306a36Sopenharmony_ci	int index;			/* used for pci_controller_num */
3562306a36Sopenharmony_ci	struct pci_controller *next;
3662306a36Sopenharmony_ci	struct pci_bus *bus;
3762306a36Sopenharmony_ci	void *arch_data;
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci	int first_busno;
4062306a36Sopenharmony_ci	int last_busno;
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_ci	struct pci_ops *ops;
4362306a36Sopenharmony_ci	volatile unsigned int *cfg_addr;
4462306a36Sopenharmony_ci	volatile unsigned char *cfg_data;
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci	/* Currently, we limit ourselves to 1 IO range and 3 mem
4762306a36Sopenharmony_ci	 * ranges since the common pci_bus structure can't handle more
4862306a36Sopenharmony_ci	 */
4962306a36Sopenharmony_ci	struct resource	io_resource;
5062306a36Sopenharmony_ci	struct resource mem_resources[3];
5162306a36Sopenharmony_ci	int mem_resource_count;
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ci	/* Host bridge I/O and Memory space
5462306a36Sopenharmony_ci	 * Used for BAR placement algorithms
5562306a36Sopenharmony_ci	 */
5662306a36Sopenharmony_ci	struct pci_space io_space;
5762306a36Sopenharmony_ci	struct pci_space mem_space;
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_ci	/* Return the interrupt number fo a device. */
6062306a36Sopenharmony_ci	int (*map_irq)(struct pci_dev*, u8, u8);
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_ci};
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_cistatic inline void pcibios_init_resource(struct resource *res,
6562306a36Sopenharmony_ci		unsigned long start, unsigned long end, int flags, char *name)
6662306a36Sopenharmony_ci{
6762306a36Sopenharmony_ci	res->start = start;
6862306a36Sopenharmony_ci	res->end = end;
6962306a36Sopenharmony_ci	res->flags = flags;
7062306a36Sopenharmony_ci	res->name = name;
7162306a36Sopenharmony_ci	res->parent = NULL;
7262306a36Sopenharmony_ci	res->sibling = NULL;
7362306a36Sopenharmony_ci	res->child = NULL;
7462306a36Sopenharmony_ci}
7562306a36Sopenharmony_ci
7662306a36Sopenharmony_ci#endif	/* _XTENSA_PCI_BRIDGE_H */
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