162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * Xtensa MX interrupt distributor 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * This file is subject to the terms and conditions of the GNU General Public 562306a36Sopenharmony_ci * License. See the file "COPYING" in the main directory of this archive 662306a36Sopenharmony_ci * for more details. 762306a36Sopenharmony_ci * 862306a36Sopenharmony_ci * Copyright (C) 2008 - 2013 Tensilica Inc. 962306a36Sopenharmony_ci */ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#ifndef _XTENSA_MXREGS_H 1262306a36Sopenharmony_ci#define _XTENSA_MXREGS_H 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* 1562306a36Sopenharmony_ci * RER/WER at, as Read/write external register 1662306a36Sopenharmony_ci * at: value 1762306a36Sopenharmony_ci * as: address 1862306a36Sopenharmony_ci * 1962306a36Sopenharmony_ci * Address Value 2062306a36Sopenharmony_ci * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p 2162306a36Sopenharmony_ci * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p 2262306a36Sopenharmony_ci * 0180 0...0m..m Clear enable specified by mask (m) 2362306a36Sopenharmony_ci * 0184 0...0m..m Set enable specified by mask (m) 2462306a36Sopenharmony_ci * 0190 0...0x..x 8-bit IPI partition register 2562306a36Sopenharmony_ci * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU 2662306a36Sopenharmony_ci * V (10-bit) Release/Version 2762306a36Sopenharmony_ci * P ( 4-bit) Number of cores - 1 2862306a36Sopenharmony_ci * U (18-bit) ID 2962306a36Sopenharmony_ci * 01a0 i.......i 32-bit ConfigID 3062306a36Sopenharmony_ci * 0200 0...0m..m RunStall core 'n' 3162306a36Sopenharmony_ci * 0220 c Cache coherency enabled 3262306a36Sopenharmony_ci */ 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci#define MIROUT(irq) (0x000 + (irq)) 3562306a36Sopenharmony_ci#define MIPICAUSE(cpu) (0x100 + (cpu)) 3662306a36Sopenharmony_ci#define MIPISET(cause) (0x140 + (cause)) 3762306a36Sopenharmony_ci#define MIENG 0x180 3862306a36Sopenharmony_ci#define MIENGSET 0x184 3962306a36Sopenharmony_ci#define MIASG 0x188 /* Read Global Assert Register */ 4062306a36Sopenharmony_ci#define MIASGSET 0x18c /* Set Global Addert Regiter */ 4162306a36Sopenharmony_ci#define MIPIPART 0x190 4262306a36Sopenharmony_ci#define SYSCFGID 0x1a0 4362306a36Sopenharmony_ci#define MPSCORE 0x200 4462306a36Sopenharmony_ci#define CCON 0x220 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci#endif /* _XTENSA_MXREGS_H */ 47