162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci#ifndef _ASM_UM_BARRIER_H_ 362306a36Sopenharmony_ci#define _ASM_UM_BARRIER_H_ 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci#include <asm/cpufeatures.h> 662306a36Sopenharmony_ci#include <asm/alternative.h> 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci/* 962306a36Sopenharmony_ci * Force strict CPU ordering. 1062306a36Sopenharmony_ci * And yes, this is required on UP too when we're talking 1162306a36Sopenharmony_ci * to devices. 1262306a36Sopenharmony_ci */ 1362306a36Sopenharmony_ci#ifdef CONFIG_X86_32 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) 1662306a36Sopenharmony_ci#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) 1762306a36Sopenharmony_ci#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci#else /* CONFIG_X86_32 */ 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define mb() asm volatile("mfence" : : : "memory") 2262306a36Sopenharmony_ci#define rmb() asm volatile("lfence" : : : "memory") 2362306a36Sopenharmony_ci#define wmb() asm volatile("sfence" : : : "memory") 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci#endif /* CONFIG_X86_32 */ 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci#include <asm-generic/barrier.h> 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci#endif 30