1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13#include <linux/kvm_host.h> 14#include "linux/lockdep.h" 15#include <linux/export.h> 16#include <linux/vmalloc.h> 17#include <linux/uaccess.h> 18#include <linux/sched/stat.h> 19 20#include <asm/processor.h> 21#include <asm/user.h> 22#include <asm/fpu/xstate.h> 23#include <asm/sgx.h> 24#include <asm/cpuid.h> 25#include "cpuid.h" 26#include "lapic.h" 27#include "mmu.h" 28#include "trace.h" 29#include "pmu.h" 30#include "xen.h" 31 32/* 33 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 34 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 35 */ 36u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 37EXPORT_SYMBOL_GPL(kvm_cpu_caps); 38 39u32 xstate_required_size(u64 xstate_bv, bool compacted) 40{ 41 int feature_bit = 0; 42 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 43 44 xstate_bv &= XFEATURE_MASK_EXTEND; 45 while (xstate_bv) { 46 if (xstate_bv & 0x1) { 47 u32 eax, ebx, ecx, edx, offset; 48 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 49 /* ECX[1]: 64B alignment in compacted form */ 50 if (compacted) 51 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 52 else 53 offset = ebx; 54 ret = max(ret, offset + eax); 55 } 56 57 xstate_bv >>= 1; 58 feature_bit++; 59 } 60 61 return ret; 62} 63 64#define F feature_bit 65 66/* Scattered Flag - For features that are scattered by cpufeatures.h. */ 67#define SF(name) \ 68({ \ 69 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 70 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ 71}) 72 73/* 74 * Magic value used by KVM when querying userspace-provided CPUID entries and 75 * doesn't care about the CPIUD index because the index of the function in 76 * question is not significant. Note, this magic value must have at least one 77 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 78 * to avoid false positives when processing guest CPUID input. 79 */ 80#define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 81 82static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 83 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 84{ 85 struct kvm_cpuid_entry2 *e; 86 int i; 87 88 /* 89 * KVM has a semi-arbitrary rule that querying the guest's CPUID model 90 * with IRQs disabled is disallowed. The CPUID model can legitimately 91 * have over one hundred entries, i.e. the lookup is slow, and IRQs are 92 * typically disabled in KVM only when KVM is in a performance critical 93 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break 94 * if this rule is violated, this assertion is purely to flag potential 95 * performance issues. If this fires, consider moving the lookup out 96 * of the hotpath, e.g. by caching information during CPUID updates. 97 */ 98 lockdep_assert_irqs_enabled(); 99 100 for (i = 0; i < nent; i++) { 101 e = &entries[i]; 102 103 if (e->function != function) 104 continue; 105 106 /* 107 * If the index isn't significant, use the first entry with a 108 * matching function. It's userspace's responsibilty to not 109 * provide "duplicate" entries in all cases. 110 */ 111 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 112 return e; 113 114 115 /* 116 * Similarly, use the first matching entry if KVM is doing a 117 * lookup (as opposed to emulating CPUID) for a function that's 118 * architecturally defined as not having a significant index. 119 */ 120 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 121 /* 122 * Direct lookups from KVM should not diverge from what 123 * KVM defines internally (the architectural behavior). 124 */ 125 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 126 return e; 127 } 128 } 129 130 return NULL; 131} 132 133static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 134 struct kvm_cpuid_entry2 *entries, 135 int nent) 136{ 137 struct kvm_cpuid_entry2 *best; 138 u64 xfeatures; 139 140 /* 141 * The existing code assumes virtual address is 48-bit or 57-bit in the 142 * canonical address checks; exit if it is ever changed. 143 */ 144 best = cpuid_entry2_find(entries, nent, 0x80000008, 145 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 146 if (best) { 147 int vaddr_bits = (best->eax & 0xff00) >> 8; 148 149 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 150 return -EINVAL; 151 } 152 153 /* 154 * Exposing dynamic xfeatures to the guest requires additional 155 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 156 */ 157 best = cpuid_entry2_find(entries, nent, 0xd, 0); 158 if (!best) 159 return 0; 160 161 xfeatures = best->eax | ((u64)best->edx << 32); 162 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 163 if (!xfeatures) 164 return 0; 165 166 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 167} 168 169/* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 170static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 171 int nent) 172{ 173 struct kvm_cpuid_entry2 *orig; 174 int i; 175 176 if (nent != vcpu->arch.cpuid_nent) 177 return -EINVAL; 178 179 for (i = 0; i < nent; i++) { 180 orig = &vcpu->arch.cpuid_entries[i]; 181 if (e2[i].function != orig->function || 182 e2[i].index != orig->index || 183 e2[i].flags != orig->flags || 184 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 185 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 186 return -EINVAL; 187 } 188 189 return 0; 190} 191 192static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 193 const char *sig) 194{ 195 struct kvm_hypervisor_cpuid cpuid = {}; 196 struct kvm_cpuid_entry2 *entry; 197 u32 base; 198 199 for_each_possible_hypervisor_cpuid_base(base) { 200 entry = kvm_find_cpuid_entry(vcpu, base); 201 202 if (entry) { 203 u32 signature[3]; 204 205 signature[0] = entry->ebx; 206 signature[1] = entry->ecx; 207 signature[2] = entry->edx; 208 209 if (!memcmp(signature, sig, sizeof(signature))) { 210 cpuid.base = base; 211 cpuid.limit = entry->eax; 212 break; 213 } 214 } 215 } 216 217 return cpuid; 218} 219 220static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 221 struct kvm_cpuid_entry2 *entries, int nent) 222{ 223 u32 base = vcpu->arch.kvm_cpuid.base; 224 225 if (!base) 226 return NULL; 227 228 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 229 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 230} 231 232static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 233{ 234 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 235 vcpu->arch.cpuid_nent); 236} 237 238void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 239{ 240 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 241 242 /* 243 * save the feature bitmap to avoid cpuid lookup for every PV 244 * operation 245 */ 246 if (best) 247 vcpu->arch.pv_cpuid.features = best->eax; 248} 249 250/* 251 * Calculate guest's supported XCR0 taking into account guest CPUID data and 252 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 253 */ 254static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 255{ 256 struct kvm_cpuid_entry2 *best; 257 258 best = cpuid_entry2_find(entries, nent, 0xd, 0); 259 if (!best) 260 return 0; 261 262 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 263} 264 265static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 266 int nent) 267{ 268 struct kvm_cpuid_entry2 *best; 269 270 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 271 if (best) { 272 /* Update OSXSAVE bit */ 273 if (boot_cpu_has(X86_FEATURE_XSAVE)) 274 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 275 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 276 277 cpuid_entry_change(best, X86_FEATURE_APIC, 278 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 279 } 280 281 best = cpuid_entry2_find(entries, nent, 7, 0); 282 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 283 cpuid_entry_change(best, X86_FEATURE_OSPKE, 284 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 285 286 best = cpuid_entry2_find(entries, nent, 0xD, 0); 287 if (best) 288 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 289 290 best = cpuid_entry2_find(entries, nent, 0xD, 1); 291 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 292 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 293 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 294 295 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 296 if (kvm_hlt_in_guest(vcpu->kvm) && best && 297 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 298 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 299 300 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 301 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 302 if (best) 303 cpuid_entry_change(best, X86_FEATURE_MWAIT, 304 vcpu->arch.ia32_misc_enable_msr & 305 MSR_IA32_MISC_ENABLE_MWAIT); 306 } 307} 308 309void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 310{ 311 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 312} 313EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 314 315static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) 316{ 317 struct kvm_cpuid_entry2 *entry; 318 319 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, 320 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 321 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 322} 323 324static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 325{ 326 struct kvm_lapic *apic = vcpu->arch.apic; 327 struct kvm_cpuid_entry2 *best; 328 bool allow_gbpages; 329 330 BUILD_BUG_ON(KVM_NR_GOVERNED_FEATURES > KVM_MAX_NR_GOVERNED_FEATURES); 331 bitmap_zero(vcpu->arch.governed_features.enabled, 332 KVM_MAX_NR_GOVERNED_FEATURES); 333 334 /* 335 * If TDP is enabled, let the guest use GBPAGES if they're supported in 336 * hardware. The hardware page walker doesn't let KVM disable GBPAGES, 337 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA 338 * walk for performance and complexity reasons. Not to mention KVM 339 * _can't_ solve the problem because GVA->GPA walks aren't visible to 340 * KVM once a TDP translation is installed. Mimic hardware behavior so 341 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. 342 * If TDP is disabled, honor *only* guest CPUID as KVM has full control 343 * and can install smaller shadow pages if the host lacks 1GiB support. 344 */ 345 allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : 346 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES); 347 if (allow_gbpages) 348 kvm_governed_feature_set(vcpu, X86_FEATURE_GBPAGES); 349 350 best = kvm_find_cpuid_entry(vcpu, 1); 351 if (best && apic) { 352 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 353 apic->lapic_timer.timer_mode_mask = 3 << 17; 354 else 355 apic->lapic_timer.timer_mode_mask = 1 << 17; 356 357 kvm_apic_set_version(vcpu); 358 } 359 360 vcpu->arch.guest_supported_xcr0 = 361 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 362 363 kvm_update_pv_runtime(vcpu); 364 365 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 366 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 367 368 kvm_pmu_refresh(vcpu); 369 vcpu->arch.cr4_guest_rsvd_bits = 370 __cr4_reserved_bits(guest_cpuid_has, vcpu); 371 372 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, 373 vcpu->arch.cpuid_nent)); 374 375 /* Invoke the vendor callback only after the above state is updated. */ 376 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 377 378 /* 379 * Except for the MMU, which needs to do its thing any vendor specific 380 * adjustments to the reserved GPA bits. 381 */ 382 kvm_mmu_after_set_cpuid(vcpu); 383} 384 385int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 386{ 387 struct kvm_cpuid_entry2 *best; 388 389 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 390 if (!best || best->eax < 0x80000008) 391 goto not_found; 392 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 393 if (best) 394 return best->eax & 0xff; 395not_found: 396 return 36; 397} 398 399/* 400 * This "raw" version returns the reserved GPA bits without any adjustments for 401 * encryption technologies that usurp bits. The raw mask should be used if and 402 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 403 */ 404u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 405{ 406 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 407} 408 409static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 410 int nent) 411{ 412 int r; 413 414 __kvm_update_cpuid_runtime(vcpu, e2, nent); 415 416 /* 417 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 418 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 419 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 420 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 421 * the core vCPU model on the fly. It would've been better to forbid any 422 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 423 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 424 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 425 * whether the supplied CPUID data is equal to what's already set. 426 */ 427 if (kvm_vcpu_has_run(vcpu)) { 428 r = kvm_cpuid_check_equal(vcpu, e2, nent); 429 if (r) 430 return r; 431 432 kvfree(e2); 433 return 0; 434 } 435 436 if (kvm_cpuid_has_hyperv(e2, nent)) { 437 r = kvm_hv_vcpu_init(vcpu); 438 if (r) 439 return r; 440 } 441 442 r = kvm_check_cpuid(vcpu, e2, nent); 443 if (r) 444 return r; 445 446 kvfree(vcpu->arch.cpuid_entries); 447 vcpu->arch.cpuid_entries = e2; 448 vcpu->arch.cpuid_nent = nent; 449 450 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 451 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 452 kvm_vcpu_after_set_cpuid(vcpu); 453 454 return 0; 455} 456 457/* when an old userspace process fills a new kernel module */ 458int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 459 struct kvm_cpuid *cpuid, 460 struct kvm_cpuid_entry __user *entries) 461{ 462 int r, i; 463 struct kvm_cpuid_entry *e = NULL; 464 struct kvm_cpuid_entry2 *e2 = NULL; 465 466 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 467 return -E2BIG; 468 469 if (cpuid->nent) { 470 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 471 if (IS_ERR(e)) 472 return PTR_ERR(e); 473 474 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 475 if (!e2) { 476 r = -ENOMEM; 477 goto out_free_cpuid; 478 } 479 } 480 for (i = 0; i < cpuid->nent; i++) { 481 e2[i].function = e[i].function; 482 e2[i].eax = e[i].eax; 483 e2[i].ebx = e[i].ebx; 484 e2[i].ecx = e[i].ecx; 485 e2[i].edx = e[i].edx; 486 e2[i].index = 0; 487 e2[i].flags = 0; 488 e2[i].padding[0] = 0; 489 e2[i].padding[1] = 0; 490 e2[i].padding[2] = 0; 491 } 492 493 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 494 if (r) 495 kvfree(e2); 496 497out_free_cpuid: 498 kvfree(e); 499 500 return r; 501} 502 503int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 504 struct kvm_cpuid2 *cpuid, 505 struct kvm_cpuid_entry2 __user *entries) 506{ 507 struct kvm_cpuid_entry2 *e2 = NULL; 508 int r; 509 510 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 511 return -E2BIG; 512 513 if (cpuid->nent) { 514 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 515 if (IS_ERR(e2)) 516 return PTR_ERR(e2); 517 } 518 519 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 520 if (r) 521 kvfree(e2); 522 523 return r; 524} 525 526int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 527 struct kvm_cpuid2 *cpuid, 528 struct kvm_cpuid_entry2 __user *entries) 529{ 530 if (cpuid->nent < vcpu->arch.cpuid_nent) 531 return -E2BIG; 532 533 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 534 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 535 return -EFAULT; 536 537 cpuid->nent = vcpu->arch.cpuid_nent; 538 return 0; 539} 540 541/* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 542static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 543{ 544 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 545 struct kvm_cpuid_entry2 entry; 546 547 reverse_cpuid_check(leaf); 548 549 cpuid_count(cpuid.function, cpuid.index, 550 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 551 552 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 553} 554 555static __always_inline 556void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) 557{ 558 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ 559 BUILD_BUG_ON(leaf < NCAPINTS); 560 561 kvm_cpu_caps[leaf] = mask; 562 563 __kvm_cpu_cap_mask(leaf); 564} 565 566static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 567{ 568 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ 569 BUILD_BUG_ON(leaf >= NCAPINTS); 570 571 kvm_cpu_caps[leaf] &= mask; 572 573 __kvm_cpu_cap_mask(leaf); 574} 575 576void kvm_set_cpu_caps(void) 577{ 578#ifdef CONFIG_X86_64 579 unsigned int f_gbpages = F(GBPAGES); 580 unsigned int f_lm = F(LM); 581 unsigned int f_xfd = F(XFD); 582#else 583 unsigned int f_gbpages = 0; 584 unsigned int f_lm = 0; 585 unsigned int f_xfd = 0; 586#endif 587 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 588 589 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 590 sizeof(boot_cpu_data.x86_capability)); 591 592 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 593 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 594 595 kvm_cpu_cap_mask(CPUID_1_ECX, 596 /* 597 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 598 * advertised to guests via CPUID! 599 */ 600 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 601 0 /* DS-CPL, VMX, SMX, EST */ | 602 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 603 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 604 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 605 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 606 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 607 F(F16C) | F(RDRAND) 608 ); 609 /* KVM emulates x2apic in software irrespective of host support. */ 610 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 611 612 kvm_cpu_cap_mask(CPUID_1_EDX, 613 F(FPU) | F(VME) | F(DE) | F(PSE) | 614 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 615 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 616 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 617 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 618 0 /* Reserved, DS, ACPI */ | F(MMX) | 619 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 620 0 /* HTT, TM, Reserved, PBE */ 621 ); 622 623 kvm_cpu_cap_mask(CPUID_7_0_EBX, 624 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 625 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 626 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 627 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 628 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 629 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 630 F(AVX512VL)); 631 632 kvm_cpu_cap_mask(CPUID_7_ECX, 633 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 634 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 635 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 636 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 637 F(SGX_LC) | F(BUS_LOCK_DETECT) 638 ); 639 /* Set LA57 based on hardware capability. */ 640 if (cpuid_ecx(7) & F(LA57)) 641 kvm_cpu_cap_set(X86_FEATURE_LA57); 642 643 /* 644 * PKU not yet implemented for shadow paging and requires OSPKE 645 * to be set on the host. Clear it if that is not the case 646 */ 647 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 648 kvm_cpu_cap_clear(X86_FEATURE_PKU); 649 650 kvm_cpu_cap_mask(CPUID_7_EDX, 651 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 652 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 653 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 654 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 655 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) 656 ); 657 658 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 659 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 660 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 661 662 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 663 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 664 if (boot_cpu_has(X86_FEATURE_STIBP)) 665 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 666 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 667 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 668 669 kvm_cpu_cap_mask(CPUID_7_1_EAX, 670 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | 671 F(FZRM) | F(FSRS) | F(FSRC) | 672 F(AMX_FP16) | F(AVX_IFMA) 673 ); 674 675 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, 676 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) | 677 F(AMX_COMPLEX) 678 ); 679 680 kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, 681 F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) | 682 F(BHI_CTRL) | F(MCDT_NO) 683 ); 684 685 kvm_cpu_cap_mask(CPUID_D_1_EAX, 686 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 687 ); 688 689 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, 690 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) 691 ); 692 693 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 694 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 695 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 696 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 697 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 698 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 699 ); 700 701 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 702 F(FPU) | F(VME) | F(DE) | F(PSE) | 703 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 704 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 705 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 706 F(PAT) | F(PSE36) | 0 /* Reserved */ | 707 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 708 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 709 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 710 ); 711 712 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 713 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 714 715 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, 716 SF(CONSTANT_TSC) 717 ); 718 719 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 720 F(CLZERO) | F(XSAVEERPTR) | 721 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 722 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 723 F(AMD_PSFD) 724 ); 725 726 /* 727 * AMD has separate bits for each SPEC_CTRL bit. 728 * arch/x86/kernel/cpu/bugs.c is kind enough to 729 * record that in cpufeatures so use them. 730 */ 731 if (boot_cpu_has(X86_FEATURE_IBPB)) 732 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 733 if (boot_cpu_has(X86_FEATURE_IBRS)) 734 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 735 if (boot_cpu_has(X86_FEATURE_STIBP)) 736 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 737 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 738 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 739 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 740 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 741 /* 742 * The preference is to use SPEC CTRL MSR instead of the 743 * VIRT_SPEC MSR. 744 */ 745 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 746 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 747 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 748 749 /* 750 * Hide all SVM features by default, SVM will set the cap bits for 751 * features it emulates and/or exposes for L1. 752 */ 753 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 754 755 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 756 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 757 F(SME_COHERENT)); 758 759 kvm_cpu_cap_mask(CPUID_8000_0021_EAX, 760 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | 761 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ 762 ); 763 764 if (cpu_feature_enabled(X86_FEATURE_SRSO_NO)) 765 kvm_cpu_cap_set(X86_FEATURE_SRSO_NO); 766 767 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, 768 F(PERFMON_V2) 769 ); 770 771 /* 772 * Synthesize "LFENCE is serializing" into the AMD-defined entry in 773 * KVM's supported CPUID if the feature is reported as supported by the 774 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long 775 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most 776 * CPUs that support SSE2. On CPUs that don't support AMD's leaf, 777 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing 778 * the mask with the raw host CPUID, and reporting support in AMD's 779 * leaf can make it easier for userspace to detect the feature. 780 */ 781 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 782 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); 783 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 784 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 785 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); 786 787 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 788 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 789 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 790 F(PMM) | F(PMM_EN) 791 ); 792 793 /* 794 * Hide RDTSCP and RDPID if either feature is reported as supported but 795 * probing MSR_TSC_AUX failed. This is purely a sanity check and 796 * should never happen, but the guest will likely crash if RDTSCP or 797 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 798 * the past. For example, the sanity check may fire if this instance of 799 * KVM is running as L1 on top of an older, broken KVM. 800 */ 801 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 802 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 803 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 804 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 805 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 806 } 807} 808EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 809 810struct kvm_cpuid_array { 811 struct kvm_cpuid_entry2 *entries; 812 int maxnent; 813 int nent; 814}; 815 816static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 817{ 818 if (array->nent >= array->maxnent) 819 return NULL; 820 821 return &array->entries[array->nent++]; 822} 823 824static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 825 u32 function, u32 index) 826{ 827 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 828 829 if (!entry) 830 return NULL; 831 832 memset(entry, 0, sizeof(*entry)); 833 entry->function = function; 834 entry->index = index; 835 switch (function & 0xC0000000) { 836 case 0x40000000: 837 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 838 return entry; 839 840 case 0x80000000: 841 /* 842 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 843 * would result in out-of-bounds calls to do_host_cpuid. 844 */ 845 { 846 static int max_cpuid_80000000; 847 if (!READ_ONCE(max_cpuid_80000000)) 848 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 849 if (function > READ_ONCE(max_cpuid_80000000)) 850 return entry; 851 } 852 break; 853 854 default: 855 break; 856 } 857 858 cpuid_count(entry->function, entry->index, 859 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 860 861 if (cpuid_function_is_indexed(function)) 862 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 863 864 return entry; 865} 866 867static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 868{ 869 struct kvm_cpuid_entry2 *entry; 870 871 if (array->nent >= array->maxnent) 872 return -E2BIG; 873 874 entry = &array->entries[array->nent]; 875 entry->function = func; 876 entry->index = 0; 877 entry->flags = 0; 878 879 switch (func) { 880 case 0: 881 entry->eax = 7; 882 ++array->nent; 883 break; 884 case 1: 885 entry->ecx = F(MOVBE); 886 ++array->nent; 887 break; 888 case 7: 889 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 890 entry->eax = 0; 891 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 892 entry->ecx = F(RDPID); 893 ++array->nent; 894 break; 895 default: 896 break; 897 } 898 899 return 0; 900} 901 902static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 903{ 904 struct kvm_cpuid_entry2 *entry; 905 int r, i, max_idx; 906 907 /* all calls to cpuid_count() should be made on the same cpu */ 908 get_cpu(); 909 910 r = -E2BIG; 911 912 entry = do_host_cpuid(array, function, 0); 913 if (!entry) 914 goto out; 915 916 switch (function) { 917 case 0: 918 /* Limited to the highest leaf implemented in KVM. */ 919 entry->eax = min(entry->eax, 0x1fU); 920 break; 921 case 1: 922 cpuid_entry_override(entry, CPUID_1_EDX); 923 cpuid_entry_override(entry, CPUID_1_ECX); 924 break; 925 case 2: 926 /* 927 * On ancient CPUs, function 2 entries are STATEFUL. That is, 928 * CPUID(function=2, index=0) may return different results each 929 * time, with the least-significant byte in EAX enumerating the 930 * number of times software should do CPUID(2, 0). 931 * 932 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 933 * idiotic. Intel's SDM states that EAX & 0xff "will always 934 * return 01H. Software should ignore this value and not 935 * interpret it as an informational descriptor", while AMD's 936 * APM states that CPUID(2) is reserved. 937 * 938 * WARN if a frankenstein CPU that supports virtualization and 939 * a stateful CPUID.0x2 is encountered. 940 */ 941 WARN_ON_ONCE((entry->eax & 0xff) > 1); 942 break; 943 /* functions 4 and 0x8000001d have additional index. */ 944 case 4: 945 case 0x8000001d: 946 /* 947 * Read entries until the cache type in the previous entry is 948 * zero, i.e. indicates an invalid entry. 949 */ 950 for (i = 1; entry->eax & 0x1f; ++i) { 951 entry = do_host_cpuid(array, function, i); 952 if (!entry) 953 goto out; 954 } 955 break; 956 case 6: /* Thermal management */ 957 entry->eax = 0x4; /* allow ARAT */ 958 entry->ebx = 0; 959 entry->ecx = 0; 960 entry->edx = 0; 961 break; 962 /* function 7 has additional index. */ 963 case 7: 964 max_idx = entry->eax = min(entry->eax, 2u); 965 cpuid_entry_override(entry, CPUID_7_0_EBX); 966 cpuid_entry_override(entry, CPUID_7_ECX); 967 cpuid_entry_override(entry, CPUID_7_EDX); 968 969 /* KVM only supports up to 0x7.2, capped above via min(). */ 970 if (max_idx >= 1) { 971 entry = do_host_cpuid(array, function, 1); 972 if (!entry) 973 goto out; 974 975 cpuid_entry_override(entry, CPUID_7_1_EAX); 976 cpuid_entry_override(entry, CPUID_7_1_EDX); 977 entry->ebx = 0; 978 entry->ecx = 0; 979 } 980 if (max_idx >= 2) { 981 entry = do_host_cpuid(array, function, 2); 982 if (!entry) 983 goto out; 984 985 cpuid_entry_override(entry, CPUID_7_2_EDX); 986 entry->ecx = 0; 987 entry->ebx = 0; 988 entry->eax = 0; 989 } 990 break; 991 case 0xa: { /* Architectural Performance Monitoring */ 992 union cpuid10_eax eax; 993 union cpuid10_edx edx; 994 995 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 996 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 997 break; 998 } 999 1000 eax.split.version_id = kvm_pmu_cap.version; 1001 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 1002 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 1003 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 1004 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 1005 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 1006 1007 if (kvm_pmu_cap.version) 1008 edx.split.anythread_deprecated = 1; 1009 edx.split.reserved1 = 0; 1010 edx.split.reserved2 = 0; 1011 1012 entry->eax = eax.full; 1013 entry->ebx = kvm_pmu_cap.events_mask; 1014 entry->ecx = 0; 1015 entry->edx = edx.full; 1016 break; 1017 } 1018 case 0x1f: 1019 case 0xb: 1020 /* 1021 * No topology; a valid topology is indicated by the presence 1022 * of subleaf 1. 1023 */ 1024 entry->eax = entry->ebx = entry->ecx = 0; 1025 break; 1026 case 0xd: { 1027 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 1028 u64 permitted_xss = kvm_caps.supported_xss; 1029 1030 entry->eax &= permitted_xcr0; 1031 entry->ebx = xstate_required_size(permitted_xcr0, false); 1032 entry->ecx = entry->ebx; 1033 entry->edx &= permitted_xcr0 >> 32; 1034 if (!permitted_xcr0) 1035 break; 1036 1037 entry = do_host_cpuid(array, function, 1); 1038 if (!entry) 1039 goto out; 1040 1041 cpuid_entry_override(entry, CPUID_D_1_EAX); 1042 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 1043 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1044 true); 1045 else { 1046 WARN_ON_ONCE(permitted_xss != 0); 1047 entry->ebx = 0; 1048 } 1049 entry->ecx &= permitted_xss; 1050 entry->edx &= permitted_xss >> 32; 1051 1052 for (i = 2; i < 64; ++i) { 1053 bool s_state; 1054 if (permitted_xcr0 & BIT_ULL(i)) 1055 s_state = false; 1056 else if (permitted_xss & BIT_ULL(i)) 1057 s_state = true; 1058 else 1059 continue; 1060 1061 entry = do_host_cpuid(array, function, i); 1062 if (!entry) 1063 goto out; 1064 1065 /* 1066 * The supported check above should have filtered out 1067 * invalid sub-leafs. Only valid sub-leafs should 1068 * reach this point, and they should have a non-zero 1069 * save state size. Furthermore, check whether the 1070 * processor agrees with permitted_xcr0/permitted_xss 1071 * on whether this is an XCR0- or IA32_XSS-managed area. 1072 */ 1073 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1074 --array->nent; 1075 continue; 1076 } 1077 1078 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1079 entry->ecx &= ~BIT_ULL(2); 1080 entry->edx = 0; 1081 } 1082 break; 1083 } 1084 case 0x12: 1085 /* Intel SGX */ 1086 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1087 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1088 break; 1089 } 1090 1091 /* 1092 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1093 * and max enclave sizes. The SGX sub-features and MISCSELECT 1094 * are restricted by kernel and KVM capabilities (like most 1095 * feature flags), while enclave size is unrestricted. 1096 */ 1097 cpuid_entry_override(entry, CPUID_12_EAX); 1098 entry->ebx &= SGX_MISC_EXINFO; 1099 1100 entry = do_host_cpuid(array, function, 1); 1101 if (!entry) 1102 goto out; 1103 1104 /* 1105 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1106 * feature flags. Advertise all supported flags, including 1107 * privileged attributes that require explicit opt-in from 1108 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1109 * expected to derive it from supported XCR0. 1110 */ 1111 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1112 entry->ebx &= 0; 1113 break; 1114 /* Intel PT */ 1115 case 0x14: 1116 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1117 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1118 break; 1119 } 1120 1121 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1122 if (!do_host_cpuid(array, function, i)) 1123 goto out; 1124 } 1125 break; 1126 /* Intel AMX TILE */ 1127 case 0x1d: 1128 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1129 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1130 break; 1131 } 1132 1133 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1134 if (!do_host_cpuid(array, function, i)) 1135 goto out; 1136 } 1137 break; 1138 case 0x1e: /* TMUL information */ 1139 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1140 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1141 break; 1142 } 1143 break; 1144 case KVM_CPUID_SIGNATURE: { 1145 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1146 entry->eax = KVM_CPUID_FEATURES; 1147 entry->ebx = sigptr[0]; 1148 entry->ecx = sigptr[1]; 1149 entry->edx = sigptr[2]; 1150 break; 1151 } 1152 case KVM_CPUID_FEATURES: 1153 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1154 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1155 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1156 (1 << KVM_FEATURE_ASYNC_PF) | 1157 (1 << KVM_FEATURE_PV_EOI) | 1158 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1159 (1 << KVM_FEATURE_PV_UNHALT) | 1160 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1161 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1162 (1 << KVM_FEATURE_PV_SEND_IPI) | 1163 (1 << KVM_FEATURE_POLL_CONTROL) | 1164 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1165 (1 << KVM_FEATURE_ASYNC_PF_INT); 1166 1167 if (sched_info_on()) 1168 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1169 1170 entry->ebx = 0; 1171 entry->ecx = 0; 1172 entry->edx = 0; 1173 break; 1174 case 0x80000000: 1175 entry->eax = min(entry->eax, 0x80000022); 1176 /* 1177 * Serializing LFENCE is reported in a multitude of ways, and 1178 * NullSegClearsBase is not reported in CPUID on Zen2; help 1179 * userspace by providing the CPUID leaf ourselves. 1180 * 1181 * However, only do it if the host has CPUID leaf 0x8000001d. 1182 * QEMU thinks that it can query the host blindly for that 1183 * CPUID leaf if KVM reports that it supports 0x8000001d or 1184 * above. The processor merrily returns values from the 1185 * highest Intel leaf which QEMU tries to use as the guest's 1186 * 0x8000001d. Even worse, this can result in an infinite 1187 * loop if said highest leaf has no subleaves indexed by ECX. 1188 */ 1189 if (entry->eax >= 0x8000001d && 1190 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1191 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1192 entry->eax = max(entry->eax, 0x80000021); 1193 break; 1194 case 0x80000001: 1195 entry->ebx &= ~GENMASK(27, 16); 1196 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1197 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1198 break; 1199 case 0x80000005: 1200 /* Pass host L1 cache and TLB info. */ 1201 break; 1202 case 0x80000006: 1203 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1204 entry->edx &= ~GENMASK(17, 16); 1205 break; 1206 case 0x80000007: /* Advanced power management */ 1207 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1208 1209 /* mask against host */ 1210 entry->edx &= boot_cpu_data.x86_power; 1211 entry->eax = entry->ebx = entry->ecx = 0; 1212 break; 1213 case 0x80000008: { 1214 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1215 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1216 unsigned phys_as = entry->eax & 0xff; 1217 1218 /* 1219 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1220 * the guest operates in the same PA space as the host, i.e. 1221 * reductions in MAXPHYADDR for memory encryption affect shadow 1222 * paging, too. 1223 * 1224 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1225 * provided, use the raw bare metal MAXPHYADDR as reductions to 1226 * the HPAs do not affect GPAs. 1227 */ 1228 if (!tdp_enabled) 1229 g_phys_as = boot_cpu_data.x86_phys_bits; 1230 else if (!g_phys_as) 1231 g_phys_as = phys_as; 1232 1233 entry->eax = g_phys_as | (virt_as << 8); 1234 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1235 entry->edx = 0; 1236 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1237 break; 1238 } 1239 case 0x8000000A: 1240 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1241 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1242 break; 1243 } 1244 entry->eax = 1; /* SVM revision 1 */ 1245 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1246 ASID emulation to nested SVM */ 1247 entry->ecx = 0; /* Reserved */ 1248 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1249 break; 1250 case 0x80000019: 1251 entry->ecx = entry->edx = 0; 1252 break; 1253 case 0x8000001a: 1254 entry->eax &= GENMASK(2, 0); 1255 entry->ebx = entry->ecx = entry->edx = 0; 1256 break; 1257 case 0x8000001e: 1258 /* Do not return host topology information. */ 1259 entry->eax = entry->ebx = entry->ecx = 0; 1260 entry->edx = 0; /* reserved */ 1261 break; 1262 case 0x8000001F: 1263 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1264 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1265 } else { 1266 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1267 /* Clear NumVMPL since KVM does not support VMPL. */ 1268 entry->ebx &= ~GENMASK(31, 12); 1269 /* 1270 * Enumerate '0' for "PA bits reduction", the adjusted 1271 * MAXPHYADDR is enumerated directly (see 0x80000008). 1272 */ 1273 entry->ebx &= ~GENMASK(11, 6); 1274 } 1275 break; 1276 case 0x80000020: 1277 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1278 break; 1279 case 0x80000021: 1280 entry->ebx = entry->ecx = entry->edx = 0; 1281 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1282 break; 1283 /* AMD Extended Performance Monitoring and Debug */ 1284 case 0x80000022: { 1285 union cpuid_0x80000022_ebx ebx; 1286 1287 entry->ecx = entry->edx = 0; 1288 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { 1289 entry->eax = entry->ebx; 1290 break; 1291 } 1292 1293 cpuid_entry_override(entry, CPUID_8000_0022_EAX); 1294 1295 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 1296 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; 1297 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) 1298 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; 1299 else 1300 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; 1301 1302 entry->ebx = ebx.full; 1303 break; 1304 } 1305 /*Add support for Centaur's CPUID instruction*/ 1306 case 0xC0000000: 1307 /*Just support up to 0xC0000004 now*/ 1308 entry->eax = min(entry->eax, 0xC0000004); 1309 break; 1310 case 0xC0000001: 1311 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1312 break; 1313 case 3: /* Processor serial number */ 1314 case 5: /* MONITOR/MWAIT */ 1315 case 0xC0000002: 1316 case 0xC0000003: 1317 case 0xC0000004: 1318 default: 1319 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1320 break; 1321 } 1322 1323 r = 0; 1324 1325out: 1326 put_cpu(); 1327 1328 return r; 1329} 1330 1331static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1332 unsigned int type) 1333{ 1334 if (type == KVM_GET_EMULATED_CPUID) 1335 return __do_cpuid_func_emulated(array, func); 1336 1337 return __do_cpuid_func(array, func); 1338} 1339 1340#define CENTAUR_CPUID_SIGNATURE 0xC0000000 1341 1342static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1343 unsigned int type) 1344{ 1345 u32 limit; 1346 int r; 1347 1348 if (func == CENTAUR_CPUID_SIGNATURE && 1349 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1350 return 0; 1351 1352 r = do_cpuid_func(array, func, type); 1353 if (r) 1354 return r; 1355 1356 limit = array->entries[array->nent - 1].eax; 1357 for (func = func + 1; func <= limit; ++func) { 1358 r = do_cpuid_func(array, func, type); 1359 if (r) 1360 break; 1361 } 1362 1363 return r; 1364} 1365 1366static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1367 __u32 num_entries, unsigned int ioctl_type) 1368{ 1369 int i; 1370 __u32 pad[3]; 1371 1372 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1373 return false; 1374 1375 /* 1376 * We want to make sure that ->padding is being passed clean from 1377 * userspace in case we want to use it for something in the future. 1378 * 1379 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1380 * have to give ourselves satisfied only with the emulated side. /me 1381 * sheds a tear. 1382 */ 1383 for (i = 0; i < num_entries; i++) { 1384 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1385 return true; 1386 1387 if (pad[0] || pad[1] || pad[2]) 1388 return true; 1389 } 1390 return false; 1391} 1392 1393int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1394 struct kvm_cpuid_entry2 __user *entries, 1395 unsigned int type) 1396{ 1397 static const u32 funcs[] = { 1398 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1399 }; 1400 1401 struct kvm_cpuid_array array = { 1402 .nent = 0, 1403 }; 1404 int r, i; 1405 1406 if (cpuid->nent < 1) 1407 return -E2BIG; 1408 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1409 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1410 1411 if (sanity_check_entries(entries, cpuid->nent, type)) 1412 return -EINVAL; 1413 1414 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1415 if (!array.entries) 1416 return -ENOMEM; 1417 1418 array.maxnent = cpuid->nent; 1419 1420 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1421 r = get_cpuid_func(&array, funcs[i], type); 1422 if (r) 1423 goto out_free; 1424 } 1425 cpuid->nent = array.nent; 1426 1427 if (copy_to_user(entries, array.entries, 1428 array.nent * sizeof(struct kvm_cpuid_entry2))) 1429 r = -EFAULT; 1430 1431out_free: 1432 kvfree(array.entries); 1433 return r; 1434} 1435 1436struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1437 u32 function, u32 index) 1438{ 1439 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1440 function, index); 1441} 1442EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1443 1444struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1445 u32 function) 1446{ 1447 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1448 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1449} 1450EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1451 1452/* 1453 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1454 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1455 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1456 * range. Centaur/VIA follows Intel semantics. 1457 * 1458 * A leaf is considered out-of-range if its function is higher than the maximum 1459 * supported leaf of its associated class or if its associated class does not 1460 * exist. 1461 * 1462 * There are three primary classes to be considered, with their respective 1463 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1464 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1465 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1466 * 1467 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1468 * - Hypervisor: 0x40000000 - 0x4fffffff 1469 * - Extended: 0x80000000 - 0xbfffffff 1470 * - Centaur: 0xc0000000 - 0xcfffffff 1471 * 1472 * The Hypervisor class is further subdivided into sub-classes that each act as 1473 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1474 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1475 * CPUID sub-classes are: 1476 * 1477 * - HyperV: 0x40000000 - 0x400000ff 1478 * - KVM: 0x40000100 - 0x400001ff 1479 */ 1480static struct kvm_cpuid_entry2 * 1481get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1482{ 1483 struct kvm_cpuid_entry2 *basic, *class; 1484 u32 function = *fn_ptr; 1485 1486 basic = kvm_find_cpuid_entry(vcpu, 0); 1487 if (!basic) 1488 return NULL; 1489 1490 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1491 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1492 return NULL; 1493 1494 if (function >= 0x40000000 && function <= 0x4fffffff) 1495 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1496 else if (function >= 0xc0000000) 1497 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1498 else 1499 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1500 1501 if (class && function <= class->eax) 1502 return NULL; 1503 1504 /* 1505 * Leaf specific adjustments are also applied when redirecting to the 1506 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1507 * entry for CPUID.0xb.index (see below), then the output value for EDX 1508 * needs to be pulled from CPUID.0xb.1. 1509 */ 1510 *fn_ptr = basic->eax; 1511 1512 /* 1513 * The class does not exist or the requested function is out of range; 1514 * the effective CPUID entry is the max basic leaf. Note, the index of 1515 * the original requested leaf is observed! 1516 */ 1517 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1518} 1519 1520bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1521 u32 *ecx, u32 *edx, bool exact_only) 1522{ 1523 u32 orig_function = *eax, function = *eax, index = *ecx; 1524 struct kvm_cpuid_entry2 *entry; 1525 bool exact, used_max_basic = false; 1526 1527 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1528 exact = !!entry; 1529 1530 if (!entry && !exact_only) { 1531 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1532 used_max_basic = !!entry; 1533 } 1534 1535 if (entry) { 1536 *eax = entry->eax; 1537 *ebx = entry->ebx; 1538 *ecx = entry->ecx; 1539 *edx = entry->edx; 1540 if (function == 7 && index == 0) { 1541 u64 data; 1542 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1543 (data & TSX_CTRL_CPUID_CLEAR)) 1544 *ebx &= ~(F(RTM) | F(HLE)); 1545 } else if (function == 0x80000007) { 1546 if (kvm_hv_invtsc_suppressed(vcpu)) 1547 *edx &= ~SF(CONSTANT_TSC); 1548 } 1549 } else { 1550 *eax = *ebx = *ecx = *edx = 0; 1551 /* 1552 * When leaf 0BH or 1FH is defined, CL is pass-through 1553 * and EDX is always the x2APIC ID, even for undefined 1554 * subleaves. Index 1 will exist iff the leaf is 1555 * implemented, so we pass through CL iff leaf 1 1556 * exists. EDX can be copied from any existing index. 1557 */ 1558 if (function == 0xb || function == 0x1f) { 1559 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1560 if (entry) { 1561 *ecx = index & 0xff; 1562 *edx = entry->edx; 1563 } 1564 } 1565 } 1566 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1567 used_max_basic); 1568 return exact; 1569} 1570EXPORT_SYMBOL_GPL(kvm_cpuid); 1571 1572int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1573{ 1574 u32 eax, ebx, ecx, edx; 1575 1576 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1577 return 1; 1578 1579 eax = kvm_rax_read(vcpu); 1580 ecx = kvm_rcx_read(vcpu); 1581 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1582 kvm_rax_write(vcpu, eax); 1583 kvm_rbx_write(vcpu, ebx); 1584 kvm_rcx_write(vcpu, ecx); 1585 kvm_rdx_write(vcpu, edx); 1586 return kvm_skip_emulated_instruction(vcpu); 1587} 1588EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1589