162306a36Sopenharmony_ci#ifndef _ASM_INTEL_DS_H 262306a36Sopenharmony_ci#define _ASM_INTEL_DS_H 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci#include <linux/percpu-defs.h> 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#define BTS_BUFFER_SIZE (PAGE_SIZE << 4) 762306a36Sopenharmony_ci#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci/* The maximal number of PEBS events: */ 1062306a36Sopenharmony_ci#define MAX_PEBS_EVENTS_FMT4 8 1162306a36Sopenharmony_ci#define MAX_PEBS_EVENTS 32 1262306a36Sopenharmony_ci#define MAX_FIXED_PEBS_EVENTS 16 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* 1562306a36Sopenharmony_ci * A debug store configuration. 1662306a36Sopenharmony_ci * 1762306a36Sopenharmony_ci * We only support architectures that use 64bit fields. 1862306a36Sopenharmony_ci */ 1962306a36Sopenharmony_cistruct debug_store { 2062306a36Sopenharmony_ci u64 bts_buffer_base; 2162306a36Sopenharmony_ci u64 bts_index; 2262306a36Sopenharmony_ci u64 bts_absolute_maximum; 2362306a36Sopenharmony_ci u64 bts_interrupt_threshold; 2462306a36Sopenharmony_ci u64 pebs_buffer_base; 2562306a36Sopenharmony_ci u64 pebs_index; 2662306a36Sopenharmony_ci u64 pebs_absolute_maximum; 2762306a36Sopenharmony_ci u64 pebs_interrupt_threshold; 2862306a36Sopenharmony_ci u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS]; 2962306a36Sopenharmony_ci} __aligned(PAGE_SIZE); 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ciDECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_cistruct debug_store_buffers { 3462306a36Sopenharmony_ci char bts_buffer[BTS_BUFFER_SIZE]; 3562306a36Sopenharmony_ci char pebs_buffer[PEBS_BUFFER_SIZE]; 3662306a36Sopenharmony_ci}; 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci#endif 39