162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Intel MID specific setup code 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * (C) Copyright 2009, 2021 Intel Corporation 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci#ifndef _ASM_X86_INTEL_MID_H 862306a36Sopenharmony_ci#define _ASM_X86_INTEL_MID_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#include <linux/pci.h> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciextern int intel_mid_pci_init(void); 1362306a36Sopenharmony_ciextern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1462306a36Sopenharmony_ciextern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev); 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciextern void intel_mid_pwr_power_off(void); 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci#define INTEL_MID_PWR_LSS_OFFSET 4 1962306a36Sopenharmony_ci#define INTEL_MID_PWR_LSS_TYPE (1 << 7) 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ciextern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#endif /* _ASM_X86_INTEL_MID_H */ 24