1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_DESC_H 3#define _ASM_X86_DESC_H 4 5#include <asm/desc_defs.h> 6#include <asm/ldt.h> 7#include <asm/mmu.h> 8#include <asm/fixmap.h> 9#include <asm/irq_vectors.h> 10#include <asm/cpu_entry_area.h> 11 12#include <linux/debug_locks.h> 13#include <linux/smp.h> 14#include <linux/percpu.h> 15 16static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info) 17{ 18 desc->limit0 = info->limit & 0x0ffff; 19 20 desc->base0 = (info->base_addr & 0x0000ffff); 21 desc->base1 = (info->base_addr & 0x00ff0000) >> 16; 22 23 desc->type = (info->read_exec_only ^ 1) << 1; 24 desc->type |= info->contents << 2; 25 /* Set the ACCESS bit so it can be mapped RO */ 26 desc->type |= 1; 27 28 desc->s = 1; 29 desc->dpl = 0x3; 30 desc->p = info->seg_not_present ^ 1; 31 desc->limit1 = (info->limit & 0xf0000) >> 16; 32 desc->avl = info->useable; 33 desc->d = info->seg_32bit; 34 desc->g = info->limit_in_pages; 35 36 desc->base2 = (info->base_addr & 0xff000000) >> 24; 37 /* 38 * Don't allow setting of the lm bit. It would confuse 39 * user_64bit_mode and would get overridden by sysret anyway. 40 */ 41 desc->l = 0; 42} 43 44struct gdt_page { 45 struct desc_struct gdt[GDT_ENTRIES]; 46} __attribute__((aligned(PAGE_SIZE))); 47 48DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); 49 50/* Provide the original GDT */ 51static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu) 52{ 53 return per_cpu(gdt_page, cpu).gdt; 54} 55 56/* Provide the current original GDT */ 57static inline struct desc_struct *get_current_gdt_rw(void) 58{ 59 return this_cpu_ptr(&gdt_page)->gdt; 60} 61 62/* Provide the fixmap address of the remapped GDT */ 63static inline struct desc_struct *get_cpu_gdt_ro(int cpu) 64{ 65 return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt; 66} 67 68/* Provide the current read-only GDT */ 69static inline struct desc_struct *get_current_gdt_ro(void) 70{ 71 return get_cpu_gdt_ro(smp_processor_id()); 72} 73 74/* Provide the physical address of the GDT page. */ 75static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu) 76{ 77 return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu)); 78} 79 80static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 81 unsigned dpl, unsigned ist, unsigned seg) 82{ 83 gate->offset_low = (u16) func; 84 gate->bits.p = 1; 85 gate->bits.dpl = dpl; 86 gate->bits.zero = 0; 87 gate->bits.type = type; 88 gate->offset_middle = (u16) (func >> 16); 89#ifdef CONFIG_X86_64 90 gate->segment = __KERNEL_CS; 91 gate->bits.ist = ist; 92 gate->reserved = 0; 93 gate->offset_high = (u32) (func >> 32); 94#else 95 gate->segment = seg; 96 gate->bits.ist = 0; 97#endif 98} 99 100static inline int desc_empty(const void *ptr) 101{ 102 const u32 *desc = ptr; 103 104 return !(desc[0] | desc[1]); 105} 106 107#ifdef CONFIG_PARAVIRT_XXL 108#include <asm/paravirt.h> 109#else 110#define load_TR_desc() native_load_tr_desc() 111#define load_gdt(dtr) native_load_gdt(dtr) 112#define load_idt(dtr) native_load_idt(dtr) 113#define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) 114#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) 115 116#define store_gdt(dtr) native_store_gdt(dtr) 117#define store_tr(tr) (tr = native_store_tr()) 118 119#define load_TLS(t, cpu) native_load_tls(t, cpu) 120#define set_ldt native_set_ldt 121 122#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc) 123#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type) 124#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g) 125 126static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 127{ 128} 129 130static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) 131{ 132} 133#endif /* CONFIG_PARAVIRT_XXL */ 134 135#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) 136 137static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate) 138{ 139 memcpy(&idt[entry], gate, sizeof(*gate)); 140} 141 142static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc) 143{ 144 memcpy(&ldt[entry], desc, 8); 145} 146 147static inline void 148native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type) 149{ 150 unsigned int size; 151 152 switch (type) { 153 case DESC_TSS: size = sizeof(tss_desc); break; 154 case DESC_LDT: size = sizeof(ldt_desc); break; 155 default: size = sizeof(*gdt); break; 156 } 157 158 memcpy(&gdt[entry], desc, size); 159} 160 161static inline void set_tssldt_descriptor(void *d, unsigned long addr, 162 unsigned type, unsigned size) 163{ 164 struct ldttss_desc *desc = d; 165 166 memset(desc, 0, sizeof(*desc)); 167 168 desc->limit0 = (u16) size; 169 desc->base0 = (u16) addr; 170 desc->base1 = (addr >> 16) & 0xFF; 171 desc->type = type; 172 desc->p = 1; 173 desc->limit1 = (size >> 16) & 0xF; 174 desc->base2 = (addr >> 24) & 0xFF; 175#ifdef CONFIG_X86_64 176 desc->base3 = (u32) (addr >> 32); 177#endif 178} 179 180static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr) 181{ 182 struct desc_struct *d = get_cpu_gdt_rw(cpu); 183 tss_desc tss; 184 185 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, 186 __KERNEL_TSS_LIMIT); 187 write_gdt_entry(d, entry, &tss, DESC_TSS); 188} 189 190#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) 191 192static inline void native_set_ldt(const void *addr, unsigned int entries) 193{ 194 if (likely(entries == 0)) 195 asm volatile("lldt %w0"::"q" (0)); 196 else { 197 unsigned cpu = smp_processor_id(); 198 ldt_desc ldt; 199 200 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, 201 entries * LDT_ENTRY_SIZE - 1); 202 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT, 203 &ldt, DESC_LDT); 204 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 205 } 206} 207 208static inline void native_load_gdt(const struct desc_ptr *dtr) 209{ 210 asm volatile("lgdt %0"::"m" (*dtr)); 211} 212 213static __always_inline void native_load_idt(const struct desc_ptr *dtr) 214{ 215 asm volatile("lidt %0"::"m" (*dtr)); 216} 217 218static inline void native_store_gdt(struct desc_ptr *dtr) 219{ 220 asm volatile("sgdt %0":"=m" (*dtr)); 221} 222 223static inline void store_idt(struct desc_ptr *dtr) 224{ 225 asm volatile("sidt %0":"=m" (*dtr)); 226} 227 228static inline void native_gdt_invalidate(void) 229{ 230 const struct desc_ptr invalid_gdt = { 231 .address = 0, 232 .size = 0 233 }; 234 235 native_load_gdt(&invalid_gdt); 236} 237 238static inline void native_idt_invalidate(void) 239{ 240 const struct desc_ptr invalid_idt = { 241 .address = 0, 242 .size = 0 243 }; 244 245 native_load_idt(&invalid_idt); 246} 247 248/* 249 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is 250 * a read-only remapping. To prevent a page fault, the GDT is switched to the 251 * original writeable version when needed. 252 */ 253#ifdef CONFIG_X86_64 254static inline void native_load_tr_desc(void) 255{ 256 struct desc_ptr gdt; 257 int cpu = raw_smp_processor_id(); 258 bool restore = 0; 259 struct desc_struct *fixmap_gdt; 260 261 native_store_gdt(&gdt); 262 fixmap_gdt = get_cpu_gdt_ro(cpu); 263 264 /* 265 * If the current GDT is the read-only fixmap, swap to the original 266 * writeable version. Swap back at the end. 267 */ 268 if (gdt.address == (unsigned long)fixmap_gdt) { 269 load_direct_gdt(cpu); 270 restore = 1; 271 } 272 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 273 if (restore) 274 load_fixmap_gdt(cpu); 275} 276#else 277static inline void native_load_tr_desc(void) 278{ 279 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); 280} 281#endif 282 283static inline unsigned long native_store_tr(void) 284{ 285 unsigned long tr; 286 287 asm volatile("str %0":"=r" (tr)); 288 289 return tr; 290} 291 292static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) 293{ 294 struct desc_struct *gdt = get_cpu_gdt_rw(cpu); 295 unsigned int i; 296 297 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) 298 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; 299} 300 301DECLARE_PER_CPU(bool, __tss_limit_invalid); 302 303static inline void force_reload_TR(void) 304{ 305 struct desc_struct *d = get_current_gdt_rw(); 306 tss_desc tss; 307 308 memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc)); 309 310 /* 311 * LTR requires an available TSS, and the TSS is currently 312 * busy. Make it be available so that LTR will work. 313 */ 314 tss.type = DESC_TSS; 315 write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS); 316 317 load_TR_desc(); 318 this_cpu_write(__tss_limit_invalid, false); 319} 320 321/* 322 * Call this if you need the TSS limit to be correct, which should be the case 323 * if and only if you have TIF_IO_BITMAP set or you're switching to a task 324 * with TIF_IO_BITMAP set. 325 */ 326static inline void refresh_tss_limit(void) 327{ 328 DEBUG_LOCKS_WARN_ON(preemptible()); 329 330 if (unlikely(this_cpu_read(__tss_limit_invalid))) 331 force_reload_TR(); 332} 333 334/* 335 * If you do something evil that corrupts the cached TSS limit (I'm looking 336 * at you, VMX exits), call this function. 337 * 338 * The optimization here is that the TSS limit only matters for Linux if the 339 * IO bitmap is in use. If the TSS limit gets forced to its minimum value, 340 * everything works except that IO bitmap will be ignored and all CPL 3 IO 341 * instructions will #GP, which is exactly what we want for normal tasks. 342 */ 343static inline void invalidate_tss_limit(void) 344{ 345 DEBUG_LOCKS_WARN_ON(preemptible()); 346 347 if (unlikely(test_thread_flag(TIF_IO_BITMAP))) 348 force_reload_TR(); 349 else 350 this_cpu_write(__tss_limit_invalid, true); 351} 352 353/* This intentionally ignores lm, since 32-bit apps don't have that field. */ 354#define LDT_empty(info) \ 355 ((info)->base_addr == 0 && \ 356 (info)->limit == 0 && \ 357 (info)->contents == 0 && \ 358 (info)->read_exec_only == 1 && \ 359 (info)->seg_32bit == 0 && \ 360 (info)->limit_in_pages == 0 && \ 361 (info)->seg_not_present == 1 && \ 362 (info)->useable == 0) 363 364/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */ 365static inline bool LDT_zero(const struct user_desc *info) 366{ 367 return (info->base_addr == 0 && 368 info->limit == 0 && 369 info->contents == 0 && 370 info->read_exec_only == 0 && 371 info->seg_32bit == 0 && 372 info->limit_in_pages == 0 && 373 info->seg_not_present == 0 && 374 info->useable == 0); 375} 376 377static inline void clear_LDT(void) 378{ 379 set_ldt(NULL, 0); 380} 381 382static inline unsigned long get_desc_base(const struct desc_struct *desc) 383{ 384 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); 385} 386 387static inline void set_desc_base(struct desc_struct *desc, unsigned long base) 388{ 389 desc->base0 = base & 0xffff; 390 desc->base1 = (base >> 16) & 0xff; 391 desc->base2 = (base >> 24) & 0xff; 392} 393 394static inline unsigned long get_desc_limit(const struct desc_struct *desc) 395{ 396 return desc->limit0 | (desc->limit1 << 16); 397} 398 399static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit) 400{ 401 desc->limit0 = limit & 0xffff; 402 desc->limit1 = (limit >> 16) & 0xf; 403} 404 405void alloc_intr_gate(unsigned int n, const void *addr); 406 407static inline void init_idt_data(struct idt_data *data, unsigned int n, 408 const void *addr) 409{ 410 BUG_ON(n > 0xFF); 411 412 memset(data, 0, sizeof(*data)); 413 data->vector = n; 414 data->addr = addr; 415 data->segment = __KERNEL_CS; 416 data->bits.type = GATE_INTERRUPT; 417 data->bits.p = 1; 418} 419 420static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d) 421{ 422 unsigned long addr = (unsigned long) d->addr; 423 424 gate->offset_low = (u16) addr; 425 gate->segment = (u16) d->segment; 426 gate->bits = d->bits; 427 gate->offset_middle = (u16) (addr >> 16); 428#ifdef CONFIG_X86_64 429 gate->offset_high = (u32) (addr >> 32); 430 gate->reserved = 0; 431#endif 432} 433 434extern unsigned long system_vectors[]; 435 436extern void load_current_idt(void); 437extern void idt_setup_early_handler(void); 438extern void idt_setup_early_traps(void); 439extern void idt_setup_traps(void); 440extern void idt_setup_apic_and_irq_gates(void); 441extern bool idt_is_f00f_address(unsigned long address); 442 443#ifdef CONFIG_X86_64 444extern void idt_setup_early_pf(void); 445#else 446static inline void idt_setup_early_pf(void) { } 447#endif 448 449extern void idt_invalidate(void); 450 451#endif /* _ASM_X86_DESC_H */ 452