162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
262306a36Sopenharmony_ci#ifndef _SPARC64_PSRCOMPAT_H
362306a36Sopenharmony_ci#define _SPARC64_PSRCOMPAT_H
462306a36Sopenharmony_ci
562306a36Sopenharmony_ci#include <asm/pstate.h>
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci/* Old 32-bit PSR fields for the compatibility conversion code. */
862306a36Sopenharmony_ci#define PSR_CWP     0x0000001f         /* current window pointer     */
962306a36Sopenharmony_ci#define PSR_ET      0x00000020         /* enable traps field         */
1062306a36Sopenharmony_ci#define PSR_PS      0x00000040         /* previous privilege level   */
1162306a36Sopenharmony_ci#define PSR_S       0x00000080         /* current privilege level    */
1262306a36Sopenharmony_ci#define PSR_PIL     0x00000f00         /* processor interrupt level  */
1362306a36Sopenharmony_ci#define PSR_EF      0x00001000         /* enable floating point      */
1462306a36Sopenharmony_ci#define PSR_EC      0x00002000         /* enable co-processor        */
1562306a36Sopenharmony_ci#define PSR_SYSCALL 0x00004000         /* inside of a syscall        */
1662306a36Sopenharmony_ci#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
1762306a36Sopenharmony_ci#define PSR_ICC     0x00f00000         /* integer condition codes    */
1862306a36Sopenharmony_ci#define PSR_C       0x00100000         /* carry bit                  */
1962306a36Sopenharmony_ci#define PSR_V       0x00200000         /* overflow bit               */
2062306a36Sopenharmony_ci#define PSR_Z       0x00400000         /* zero bit                   */
2162306a36Sopenharmony_ci#define PSR_N       0x00800000         /* negative bit               */
2262306a36Sopenharmony_ci#define PSR_VERS    0x0f000000         /* cpu-version field          */
2362306a36Sopenharmony_ci#define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci#define PSR_V8PLUS  0xff000000         /* fake impl/ver, meaning a 64bit CPU is present */
2662306a36Sopenharmony_ci#define PSR_XCC	    0x000f0000         /* if PSR_V8PLUS, this is %xcc */
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_cistatic inline unsigned int tstate_to_psr(unsigned long tstate)
2962306a36Sopenharmony_ci{
3062306a36Sopenharmony_ci	return ((tstate & TSTATE_CWP)			|
3162306a36Sopenharmony_ci		PSR_S					|
3262306a36Sopenharmony_ci		((tstate & TSTATE_ICC) >> 12)		|
3362306a36Sopenharmony_ci		((tstate & TSTATE_XCC) >> 20)		|
3462306a36Sopenharmony_ci		((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
3562306a36Sopenharmony_ci		PSR_V8PLUS);
3662306a36Sopenharmony_ci}
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_cistatic inline unsigned long psr_to_tstate_icc(unsigned int psr)
3962306a36Sopenharmony_ci{
4062306a36Sopenharmony_ci	unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
4162306a36Sopenharmony_ci	if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
4262306a36Sopenharmony_ci		tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
4362306a36Sopenharmony_ci	return tstate;
4462306a36Sopenharmony_ci}
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci#endif /* !(_SPARC64_PSRCOMPAT_H) */
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